Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T5 T6 T7 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        unreachable          mask <= ppc_out;
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T5 T6 T7 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T5 T6 T7 
128                             end
                        MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T4 T5 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T5 T11 T13 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T4 T5 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        unreachable          mask <= ppc_out;
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T5 T11 T13 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T5 T11 T13 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T11,T13
1	0	Covered	T5,T11,T13

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Covered	T5,T11,T13

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T42,T43,T52

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T42,T43,T52
1	0	Covered	T42,T43,T52

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Unreachable
1	1	Covered	T42,T43,T52

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T11,T13

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T11,T13
1	0	Covered	T5,T6,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T5,T6,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T11,T13
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==> (Unreachable)  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==> (Unreachable)
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T6,T11
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T4

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T11
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	761380461	610681775	0	0
CheckNGreaterZero_A	2868	2868	0	0
GntImpliesReady_A	761380461	3758459	0	0
GntImpliesValid_A	761380461	3758459	0	0
GrantKnown_A	761380461	610681775	0	0
IdxKnown_A	761380461	610681775	0	0
IndexIsCorrect_A	761380461	3758459	0	0
LockArbDecision_A	761380461	0	0	0
NoReadyValidNoGrant_A	761380461	0	0	0
ReadyAndValidImplyGrant_A	761380461	3758459	0	0
ReqAndReadyImplyGrant_A	761380461	3758459	0	0
ReqImpliesValid_A	761380461	3758459	0	0
ReqStaysHighUntilGranted0_M	761380461	0	0	0
RoundRobin_A	761380461	2	0	956
ValidKnown_A	761380461	610681775	0	0
gen_data_port_assertion.DataFlow_A	761380461	3758459	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761380461	610681775	0	0
T1	4135	3777	0	0
T2	1305	1228	0	0
T3	1321	1234	0	0
T4	8286	8203	0	0
T5	10645	10264	0	0
T6	154169	91663	0	0
T7	14251	12856	0	0
T8	45016	30925	0	0
T9	3090	3031	0	0
T10	5714	4162	0	0
T11	145282	70992	0	0
T13	520950	257880	0	0
T14	842	360	0	0
T15	5136	2568	0	0
T16	30290	29328	0	0
T17	17278	17278	0	0
T19	1568	1568	0	0
T21	0	123990	0	0
T25	0	115904	0	0
T26	0	216	0	0
T27	0	105272	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2868	2868	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761380461	3758459	0	0
T5	10645	332	0	0
T6	91836	832	0	0
T7	12939	832	0	0
T8	31009	832	0	0
T9	3090	0	0	0
T10	5714	0	0	0
T11	164187	2463	0	0
T12	1975	0	0	0
T13	423777	7178	0	0
T14	421	0	0	0
T15	2568	225	0	0
T16	30290	832	0	0
T17	17278	832	0	0
T36	817	0	0	0
T37	0	832	0	0
T38	0	94	0	0
T42	56992	1544	0	0
T43	0	1290	0	0
T44	0	35	0	0
T45	96201	3589	0	0
T46	0	119	0	0
T48	0	2562	0	0
T50	9362	0	0	0
T52	0	3109	0	0
T60	0	6	0	0
T68	0	2125	0	0
T69	0	9	0	0
T70	26466	0	0	0
T71	1182	0	0	0
T72	14544	0	0	0
T73	16592	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761380461	3758459	0	0
T5	10645	332	0	0
T6	91836	832	0	0
T7	12939	832	0	0
T8	31009	832	0	0
T9	3090	0	0	0
T10	5714	0	0	0
T11	164187	2463	0	0
T12	1975	0	0	0
T13	423777	7178	0	0
T14	421	0	0	0
T15	2568	225	0	0
T16	30290	832	0	0
T17	17278	832	0	0
T36	817	0	0	0
T37	0	832	0	0
T38	0	94	0	0
T42	56992	1544	0	0
T43	0	1290	0	0
T44	0	35	0	0
T45	96201	3589	0	0
T46	0	119	0	0
T48	0	2562	0	0
T50	9362	0	0	0
T52	0	3109	0	0
T60	0	6	0	0
T68	0	2125	0	0
T69	0	9	0	0
T70	26466	0	0	0
T71	1182	0	0	0
T72	14544	0	0	0
T73	16592	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761380461	610681775	0	0
T1	4135	3777	0	0
T2	1305	1228	0	0
T3	1321	1234	0	0
T4	8286	8203	0	0
T5	10645	10264	0	0
T6	154169	91663	0	0
T7	14251	12856	0	0
T8	45016	30925	0	0
T9	3090	3031	0	0
T10	5714	4162	0	0
T11	145282	70992	0	0
T13	520950	257880	0	0
T14	842	360	0	0
T15	5136	2568	0	0
T16	30290	29328	0	0
T17	17278	17278	0	0
T19	1568	1568	0	0
T21	0	123990	0	0
T25	0	115904	0	0
T26	0	216	0	0
T27	0	105272	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761380461	610681775	0	0
T1	4135	3777	0	0
T2	1305	1228	0	0
T3	1321	1234	0	0
T4	8286	8203	0	0
T5	10645	10264	0	0
T6	154169	91663	0	0
T7	14251	12856	0	0
T8	45016	30925	0	0
T9	3090	3031	0	0
T10	5714	4162	0	0
T11	145282	70992	0	0
T13	520950	257880	0	0
T14	842	360	0	0
T15	5136	2568	0	0
T16	30290	29328	0	0
T17	17278	17278	0	0
T19	1568	1568	0	0
T21	0	123990	0	0
T25	0	115904	0	0
T26	0	216	0	0
T27	0	105272	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761380461	3758459	0	0
T5	10645	332	0	0
T6	91836	832	0	0
T7	12939	832	0	0
T8	31009	832	0	0
T9	3090	0	0	0
T10	5714	0	0	0
T11	164187	2463	0	0
T12	1975	0	0	0
T13	423777	7178	0	0
T14	421	0	0	0
T15	2568	225	0	0
T16	30290	832	0	0
T17	17278	832	0	0
T36	817	0	0	0
T37	0	832	0	0
T38	0	94	0	0
T42	56992	1544	0	0
T43	0	1290	0	0
T44	0	35	0	0
T45	96201	3589	0	0
T46	0	119	0	0
T48	0	2562	0	0
T50	9362	0	0	0
T52	0	3109	0	0
T60	0	6	0	0
T68	0	2125	0	0
T69	0	9	0	0
T70	26466	0	0	0
T71	1182	0	0	0
T72	14544	0	0	0
T73	16592	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761380461	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761380461	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761380461	3758459	0	0
T5	10645	332	0	0
T6	91836	832	0	0
T7	12939	832	0	0
T8	31009	832	0	0
T9	3090	0	0	0
T10	5714	0	0	0
T11	164187	2463	0	0
T12	1975	0	0	0
T13	423777	7178	0	0
T14	421	0	0	0
T15	2568	225	0	0
T16	30290	832	0	0
T17	17278	832	0	0
T36	817	0	0	0
T37	0	832	0	0
T38	0	94	0	0
T42	56992	1544	0	0
T43	0	1290	0	0
T44	0	35	0	0
T45	96201	3589	0	0
T46	0	119	0	0
T48	0	2562	0	0
T50	9362	0	0	0
T52	0	3109	0	0
T60	0	6	0	0
T68	0	2125	0	0
T69	0	9	0	0
T70	26466	0	0	0
T71	1182	0	0	0
T72	14544	0	0	0
T73	16592	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761380461	3758459	0	0
T5	10645	332	0	0
T6	91836	832	0	0
T7	12939	832	0	0
T8	31009	832	0	0
T9	3090	0	0	0
T10	5714	0	0	0
T11	164187	2463	0	0
T12	1975	0	0	0
T13	423777	7178	0	0
T14	421	0	0	0
T15	2568	225	0	0
T16	30290	832	0	0
T17	17278	832	0	0
T36	817	0	0	0
T37	0	832	0	0
T38	0	94	0	0
T42	56992	1544	0	0
T43	0	1290	0	0
T44	0	35	0	0
T45	96201	3589	0	0
T46	0	119	0	0
T48	0	2562	0	0
T50	9362	0	0	0
T52	0	3109	0	0
T60	0	6	0	0
T68	0	2125	0	0
T69	0	9	0	0
T70	26466	0	0	0
T71	1182	0	0	0
T72	14544	0	0	0
T73	16592	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761380461	3758459	0	0
T5	10645	332	0	0
T6	91836	832	0	0
T7	12939	832	0	0
T8	31009	832	0	0
T9	3090	0	0	0
T10	5714	0	0	0
T11	164187	2463	0	0
T12	1975	0	0	0
T13	423777	7178	0	0
T14	421	0	0	0
T15	2568	225	0	0
T16	30290	832	0	0
T17	17278	832	0	0
T36	817	0	0	0
T37	0	832	0	0
T38	0	94	0	0
T42	56992	1544	0	0
T43	0	1290	0	0
T44	0	35	0	0
T45	96201	3589	0	0
T46	0	119	0	0
T48	0	2562	0	0
T50	9362	0	0	0
T52	0	3109	0	0
T60	0	6	0	0
T68	0	2125	0	0
T69	0	9	0	0
T70	26466	0	0	0
T71	1182	0	0	0
T72	14544	0	0	0
T73	16592	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	761380461	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761380461	2	0	956
T74	432399	1	0	1
T75	458756	1	0	1
T76	696616	0	0	1
T77	532621	0	0	1
T78	741960	0	0	1
T79	895048	0	0	1
T80	100837	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761380461	610681775	0	0
T1	4135	3777	0	0
T2	1305	1228	0	0
T3	1321	1234	0	0
T4	8286	8203	0	0
T5	10645	10264	0	0
T6	154169	91663	0	0
T7	14251	12856	0	0
T8	45016	30925	0	0
T9	3090	3031	0	0
T10	5714	4162	0	0
T11	145282	70992	0	0
T13	520950	257880	0	0
T14	842	360	0	0
T15	5136	2568	0	0
T16	30290	29328	0	0
T17	17278	17278	0	0
T19	1568	1568	0	0
T21	0	123990	0	0
T25	0	115904	0	0
T26	0	216	0	0
T27	0	105272	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761380461	3758459	0	0
T5	10645	332	0	0
T6	91836	832	0	0
T7	12939	832	0	0
T8	31009	832	0	0
T9	3090	0	0	0
T10	5714	0	0	0
T11	164187	2463	0	0
T12	1975	0	0	0
T13	423777	7178	0	0
T14	421	0	0	0
T15	2568	225	0	0
T16	30290	832	0	0
T17	17278	832	0	0
T36	817	0	0	0
T37	0	832	0	0
T38	0	94	0	0
T42	56992	1544	0	0
T43	0	1290	0	0
T44	0	35	0	0
T45	96201	3589	0	0
T46	0	119	0	0
T48	0	2562	0	0
T50	9362	0	0	0
T52	0	3109	0	0
T60	0	6	0	0
T68	0	2125	0	0
T69	0	9	0	0
T70	26466	0	0	0
T71	1182	0	0	0
T72	14544	0	0	0
T73	16592	0	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T4 T5 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T5 T11 T13 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T4 T5 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        unreachable          mask <= ppc_out;
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T5 T11 T13 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T5 T11 T13 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T11,T13
1	0	Covered	T5,T11,T13

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Covered	T5,T11,T13

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==> (Unreachable)  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==> (Unreachable)
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T11,T13
0	0	1	Unreachable
0	0	0	Covered	T1,T4,T5

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T5,T11,T13
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T5,T11,T13
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	149299706	28013552	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	149299706	629879	0	0
GntImpliesValid_A	149299706	629879	0	0
GrantKnown_A	149299706	28013552	0	0
IdxKnown_A	149299706	28013552	0	0
IndexIsCorrect_A	149299706	629879	0	0
LockArbDecision_A	149299706	0	0	0
NoReadyValidNoGrant_A	149299706	0	0	0
ReadyAndValidImplyGrant_A	149299706	629879	0	0
ReqAndReadyImplyGrant_A	149299706	629879	0	0
ReqImpliesValid_A	149299706	629879	0	0
ReqStaysHighUntilGranted0_M	149299706	0	0	0
RoundRobin_A	149299706	0	0	0
ValidKnown_A	149299706	28013552	0	0
gen_data_port_assertion.DataFlow_A	149299706	629879	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149299706	28013552	0	0
T1	1059	792	0	0
T4	720	720	0	0
T5	6506	6224	0	0
T6	62333	0	0	0
T7	1312	0	0	0
T8	14007	0	0	0
T11	72641	70992	0	0
T13	260475	257880	0	0
T14	421	360	0	0
T15	2568	2568	0	0
T25	0	115904	0	0
T26	0	216	0	0
T27	0	105272	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149299706	629879	0	0
T5	6506	216	0	0
T6	62333	0	0	0
T7	1312	0	0	0
T8	14007	0	0	0
T11	72641	1744	0	0
T13	260475	4931	0	0
T14	421	0	0	0
T15	2568	157	0	0
T16	30290	0	0	0
T17	17278	0	0	0
T38	0	94	0	0
T44	0	35	0	0
T45	0	3589	0	0
T46	0	119	0	0
T68	0	2125	0	0
T69	0	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149299706	629879	0	0
T5	6506	216	0	0
T6	62333	0	0	0
T7	1312	0	0	0
T8	14007	0	0	0
T11	72641	1744	0	0
T13	260475	4931	0	0
T14	421	0	0	0
T15	2568	157	0	0
T16	30290	0	0	0
T17	17278	0	0	0
T38	0	94	0	0
T44	0	35	0	0
T45	0	3589	0	0
T46	0	119	0	0
T68	0	2125	0	0
T69	0	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149299706	28013552	0	0
T1	1059	792	0	0
T4	720	720	0	0
T5	6506	6224	0	0
T6	62333	0	0	0
T7	1312	0	0	0
T8	14007	0	0	0
T11	72641	70992	0	0
T13	260475	257880	0	0
T14	421	360	0	0
T15	2568	2568	0	0
T25	0	115904	0	0
T26	0	216	0	0
T27	0	105272	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149299706	28013552	0	0
T1	1059	792	0	0
T4	720	720	0	0
T5	6506	6224	0	0
T6	62333	0	0	0
T7	1312	0	0	0
T8	14007	0	0	0
T11	72641	70992	0	0
T13	260475	257880	0	0
T14	421	360	0	0
T15	2568	2568	0	0
T25	0	115904	0	0
T26	0	216	0	0
T27	0	105272	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149299706	629879	0	0
T5	6506	216	0	0
T6	62333	0	0	0
T7	1312	0	0	0
T8	14007	0	0	0
T11	72641	1744	0	0
T13	260475	4931	0	0
T14	421	0	0	0
T15	2568	157	0	0
T16	30290	0	0	0
T17	17278	0	0	0
T38	0	94	0	0
T44	0	35	0	0
T45	0	3589	0	0
T46	0	119	0	0
T68	0	2125	0	0
T69	0	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149299706	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149299706	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149299706	629879	0	0
T5	6506	216	0	0
T6	62333	0	0	0
T7	1312	0	0	0
T8	14007	0	0	0
T11	72641	1744	0	0
T13	260475	4931	0	0
T14	421	0	0	0
T15	2568	157	0	0
T16	30290	0	0	0
T17	17278	0	0	0
T38	0	94	0	0
T44	0	35	0	0
T45	0	3589	0	0
T46	0	119	0	0
T68	0	2125	0	0
T69	0	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149299706	629879	0	0
T5	6506	216	0	0
T6	62333	0	0	0
T7	1312	0	0	0
T8	14007	0	0	0
T11	72641	1744	0	0
T13	260475	4931	0	0
T14	421	0	0	0
T15	2568	157	0	0
T16	30290	0	0	0
T17	17278	0	0	0
T38	0	94	0	0
T44	0	35	0	0
T45	0	3589	0	0
T46	0	119	0	0
T68	0	2125	0	0
T69	0	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149299706	629879	0	0
T5	6506	216	0	0
T6	62333	0	0	0
T7	1312	0	0	0
T8	14007	0	0	0
T11	72641	1744	0	0
T13	260475	4931	0	0
T14	421	0	0	0
T15	2568	157	0	0
T16	30290	0	0	0
T17	17278	0	0	0
T38	0	94	0	0
T44	0	35	0	0
T45	0	3589	0	0
T46	0	119	0	0
T68	0	2125	0	0
T69	0	9	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	149299706	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149299706	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149299706	28013552	0	0
T1	1059	792	0	0
T4	720	720	0	0
T5	6506	6224	0	0
T6	62333	0	0	0
T7	1312	0	0	0
T8	14007	0	0	0
T11	72641	70992	0	0
T13	260475	257880	0	0
T14	421	360	0	0
T15	2568	2568	0	0
T25	0	115904	0	0
T26	0	216	0	0
T27	0	105272	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149299706	629879	0	0
T5	6506	216	0	0
T6	62333	0	0	0
T7	1312	0	0	0
T8	14007	0	0	0
T11	72641	1744	0	0
T13	260475	4931	0	0
T14	421	0	0	0
T15	2568	157	0	0
T16	30290	0	0	0
T17	17278	0	0	0
T38	0	94	0	0
T44	0	35	0	0
T45	0	3589	0	0
T46	0	119	0	0
T68	0	2125	0	0
T69	0	9	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T6 T7 T8 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T42 T43 T52 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T6 T7 T8 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        unreachable          mask <= ppc_out;
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T42 T43 T52 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T42 T43 T52 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T42,T43,T52

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T42,T43,T52
1	0	Covered	T42,T43,T52

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Unreachable
1	1	Covered	T42,T43,T52

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T52
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==> (Unreachable)  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==> (Unreachable)
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T42,T43,T52
0	0	1	Unreachable
0	0	0	Covered	T6,T7,T8

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T52
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T52
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	149299706	119975098	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	149299706	899241	0	0
GntImpliesValid_A	149299706	899241	0	0
GrantKnown_A	149299706	119975098	0	0
IdxKnown_A	149299706	119975098	0	0
IndexIsCorrect_A	149299706	899241	0	0
LockArbDecision_A	149299706	0	0	0
NoReadyValidNoGrant_A	149299706	0	0	0
ReadyAndValidImplyGrant_A	149299706	899241	0	0
ReqAndReadyImplyGrant_A	149299706	899241	0	0
ReqImpliesValid_A	149299706	899241	0	0
ReqStaysHighUntilGranted0_M	149299706	0	0	0
RoundRobin_A	149299706	0	0	0
ValidKnown_A	149299706	119975098	0	0
gen_data_port_assertion.DataFlow_A	149299706	899241	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149299706	119975098	0	0
T6	62333	62216	0	0
T7	1312	1312	0	0
T8	14007	13976	0	0
T11	72641	0	0	0
T13	260475	0	0	0
T14	421	0	0	0
T15	2568	0	0	0
T16	30290	29328	0	0
T17	17278	17278	0	0
T19	1568	1568	0	0
T21	0	123990	0	0
T22	0	19312	0	0
T23	0	144	0	0
T24	0	16844	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149299706	899241	0	0
T42	56992	1544	0	0
T43	0	1290	0	0
T45	96201	0	0	0
T46	2036	0	0	0
T47	13238	0	0	0
T48	0	2562	0	0
T50	9362	0	0	0
T52	0	3109	0	0
T55	81081	0	0	0
T59	0	5751	0	0
T60	0	6	0	0
T64	0	9127	0	0
T70	26466	0	0	0
T71	1182	0	0	0
T72	14544	0	0	0
T73	16592	0	0	0
T81	0	3848	0	0
T82	0	10	0	0
T83	0	516	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149299706	899241	0	0
T42	56992	1544	0	0
T43	0	1290	0	0
T45	96201	0	0	0
T46	2036	0	0	0
T47	13238	0	0	0
T48	0	2562	0	0
T50	9362	0	0	0
T52	0	3109	0	0
T55	81081	0	0	0
T59	0	5751	0	0
T60	0	6	0	0
T64	0	9127	0	0
T70	26466	0	0	0
T71	1182	0	0	0
T72	14544	0	0	0
T73	16592	0	0	0
T81	0	3848	0	0
T82	0	10	0	0
T83	0	516	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149299706	119975098	0	0
T6	62333	62216	0	0
T7	1312	1312	0	0
T8	14007	13976	0	0
T11	72641	0	0	0
T13	260475	0	0	0
T14	421	0	0	0
T15	2568	0	0	0
T16	30290	29328	0	0
T17	17278	17278	0	0
T19	1568	1568	0	0
T21	0	123990	0	0
T22	0	19312	0	0
T23	0	144	0	0
T24	0	16844	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149299706	119975098	0	0
T6	62333	62216	0	0
T7	1312	1312	0	0
T8	14007	13976	0	0
T11	72641	0	0	0
T13	260475	0	0	0
T14	421	0	0	0
T15	2568	0	0	0
T16	30290	29328	0	0
T17	17278	17278	0	0
T19	1568	1568	0	0
T21	0	123990	0	0
T22	0	19312	0	0
T23	0	144	0	0
T24	0	16844	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149299706	899241	0	0
T42	56992	1544	0	0
T43	0	1290	0	0
T45	96201	0	0	0
T46	2036	0	0	0
T47	13238	0	0	0
T48	0	2562	0	0
T50	9362	0	0	0
T52	0	3109	0	0
T55	81081	0	0	0
T59	0	5751	0	0
T60	0	6	0	0
T64	0	9127	0	0
T70	26466	0	0	0
T71	1182	0	0	0
T72	14544	0	0	0
T73	16592	0	0	0
T81	0	3848	0	0
T82	0	10	0	0
T83	0	516	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149299706	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149299706	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149299706	899241	0	0
T42	56992	1544	0	0
T43	0	1290	0	0
T45	96201	0	0	0
T46	2036	0	0	0
T47	13238	0	0	0
T48	0	2562	0	0
T50	9362	0	0	0
T52	0	3109	0	0
T55	81081	0	0	0
T59	0	5751	0	0
T60	0	6	0	0
T64	0	9127	0	0
T70	26466	0	0	0
T71	1182	0	0	0
T72	14544	0	0	0
T73	16592	0	0	0
T81	0	3848	0	0
T82	0	10	0	0
T83	0	516	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149299706	899241	0	0
T42	56992	1544	0	0
T43	0	1290	0	0
T45	96201	0	0	0
T46	2036	0	0	0
T47	13238	0	0	0
T48	0	2562	0	0
T50	9362	0	0	0
T52	0	3109	0	0
T55	81081	0	0	0
T59	0	5751	0	0
T60	0	6	0	0
T64	0	9127	0	0
T70	26466	0	0	0
T71	1182	0	0	0
T72	14544	0	0	0
T73	16592	0	0	0
T81	0	3848	0	0
T82	0	10	0	0
T83	0	516	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149299706	899241	0	0
T42	56992	1544	0	0
T43	0	1290	0	0
T45	96201	0	0	0
T46	2036	0	0	0
T47	13238	0	0	0
T48	0	2562	0	0
T50	9362	0	0	0
T52	0	3109	0	0
T55	81081	0	0	0
T59	0	5751	0	0
T60	0	6	0	0
T64	0	9127	0	0
T70	26466	0	0	0
T71	1182	0	0	0
T72	14544	0	0	0
T73	16592	0	0	0
T81	0	3848	0	0
T82	0	10	0	0
T83	0	516	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	149299706	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149299706	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149299706	119975098	0	0
T6	62333	62216	0	0
T7	1312	1312	0	0
T8	14007	13976	0	0
T11	72641	0	0	0
T13	260475	0	0	0
T14	421	0	0	0
T15	2568	0	0	0
T16	30290	29328	0	0
T17	17278	17278	0	0
T19	1568	1568	0	0
T21	0	123990	0	0
T22	0	19312	0	0
T23	0	144	0	0
T24	0	16844	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149299706	899241	0	0
T42	56992	1544	0	0
T43	0	1290	0	0
T45	96201	0	0	0
T46	2036	0	0	0
T47	13238	0	0	0
T48	0	2562	0	0
T50	9362	0	0	0
T52	0	3109	0	0
T55	81081	0	0	0
T59	0	5751	0	0
T60	0	6	0	0
T64	0	9127	0	0
T70	26466	0	0	0
T71	1182	0	0	0
T72	14544	0	0	0
T73	16592	0	0	0
T81	0	3848	0	0
T82	0	10	0	0
T83	0	516	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T5 T6 T7 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        unreachable          mask <= ppc_out;
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T5 T6 T7 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T5 T6 T7 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T11,T13

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T11,T13
1	0	Covered	T5,T6,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T5,T6,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T11,T13
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==> (Unreachable)  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==> (Unreachable)
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T6,T7
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	462781049	462693125	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	462781049	2229339	0	0
GntImpliesValid_A	462781049	2229339	0	0
GrantKnown_A	462781049	462693125	0	0
IdxKnown_A	462781049	462693125	0	0
IndexIsCorrect_A	462781049	2229339	0	0
LockArbDecision_A	462781049	0	0	0
NoReadyValidNoGrant_A	462781049	0	0	0
ReadyAndValidImplyGrant_A	462781049	2229339	0	0
ReqAndReadyImplyGrant_A	462781049	2229339	0	0
ReqImpliesValid_A	462781049	2229339	0	0
ReqStaysHighUntilGranted0_M	462781049	0	0	0
RoundRobin_A	462781049	2	0	956
ValidKnown_A	462781049	462693125	0	0
gen_data_port_assertion.DataFlow_A	462781049	2229339	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462781049	462693125	0	0
T1	3076	2985	0	0
T2	1305	1228	0	0
T3	1321	1234	0	0
T4	7566	7483	0	0
T5	4139	4040	0	0
T6	29503	29447	0	0
T7	11627	11544	0	0
T8	17002	16949	0	0
T9	3090	3031	0	0
T10	5714	4162	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462781049	2229339	0	0
T5	4139	116	0	0
T6	29503	832	0	0
T7	11627	832	0	0
T8	17002	832	0	0
T9	3090	0	0	0
T10	5714	0	0	0
T11	91546	719	0	0
T12	1975	0	0	0
T13	163302	2247	0	0
T15	0	68	0	0
T16	0	832	0	0
T17	0	832	0	0
T36	817	0	0	0
T37	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462781049	2229339	0	0
T5	4139	116	0	0
T6	29503	832	0	0
T7	11627	832	0	0
T8	17002	832	0	0
T9	3090	0	0	0
T10	5714	0	0	0
T11	91546	719	0	0
T12	1975	0	0	0
T13	163302	2247	0	0
T15	0	68	0	0
T16	0	832	0	0
T17	0	832	0	0
T36	817	0	0	0
T37	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462781049	462693125	0	0
T1	3076	2985	0	0
T2	1305	1228	0	0
T3	1321	1234	0	0
T4	7566	7483	0	0
T5	4139	4040	0	0
T6	29503	29447	0	0
T7	11627	11544	0	0
T8	17002	16949	0	0
T9	3090	3031	0	0
T10	5714	4162	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462781049	462693125	0	0
T1	3076	2985	0	0
T2	1305	1228	0	0
T3	1321	1234	0	0
T4	7566	7483	0	0
T5	4139	4040	0	0
T6	29503	29447	0	0
T7	11627	11544	0	0
T8	17002	16949	0	0
T9	3090	3031	0	0
T10	5714	4162	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462781049	2229339	0	0
T5	4139	116	0	0
T6	29503	832	0	0
T7	11627	832	0	0
T8	17002	832	0	0
T9	3090	0	0	0
T10	5714	0	0	0
T11	91546	719	0	0
T12	1975	0	0	0
T13	163302	2247	0	0
T15	0	68	0	0
T16	0	832	0	0
T17	0	832	0	0
T36	817	0	0	0
T37	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462781049	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462781049	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462781049	2229339	0	0
T5	4139	116	0	0
T6	29503	832	0	0
T7	11627	832	0	0
T8	17002	832	0	0
T9	3090	0	0	0
T10	5714	0	0	0
T11	91546	719	0	0
T12	1975	0	0	0
T13	163302	2247	0	0
T15	0	68	0	0
T16	0	832	0	0
T17	0	832	0	0
T36	817	0	0	0
T37	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462781049	2229339	0	0
T5	4139	116	0	0
T6	29503	832	0	0
T7	11627	832	0	0
T8	17002	832	0	0
T9	3090	0	0	0
T10	5714	0	0	0
T11	91546	719	0	0
T12	1975	0	0	0
T13	163302	2247	0	0
T15	0	68	0	0
T16	0	832	0	0
T17	0	832	0	0
T36	817	0	0	0
T37	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462781049	2229339	0	0
T5	4139	116	0	0
T6	29503	832	0	0
T7	11627	832	0	0
T8	17002	832	0	0
T9	3090	0	0	0
T10	5714	0	0	0
T11	91546	719	0	0
T12	1975	0	0	0
T13	163302	2247	0	0
T15	0	68	0	0
T16	0	832	0	0
T17	0	832	0	0
T36	817	0	0	0
T37	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	462781049	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462781049	2	0	956
T74	432399	1	0	1
T75	458756	1	0	1
T76	696616	0	0	1
T77	532621	0	0	1
T78	741960	0	0	1
T79	895048	0	0	1
T80	100837	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462781049	462693125	0	0
T1	3076	2985	0	0
T2	1305	1228	0	0
T3	1321	1234	0	0
T4	7566	7483	0	0
T5	4139	4040	0	0
T6	29503	29447	0	0
T7	11627	11544	0	0
T8	17002	16949	0	0
T9	3090	3031	0	0
T10	5714	4162	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462781049	2229339	0	0
T5	4139	116	0	0
T6	29503	832	0	0
T7	11627	832	0	0
T8	17002	832	0	0
T9	3090	0	0	0
T10	5714	0	0	0
T11	91546	719	0	0
T12	1975	0	0	0
T13	163302	2247	0	0
T15	0	68	0	0
T16	0	832	0	0
T17	0	832	0	0
T36	817	0	0	0
T37	0	832	0	0