Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4030550	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4655955

1

T4

9

T5

1

T6

393

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4811690	1			T1	79		T2	1		T3	1
values[0x0]	1936594	1			T4	6		T6	183		T7	440
values[0x1]	1938221	1			T4	4		T5	1		T6	193

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2856032	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5830473

1

T1

31

T3

1

T4

10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	31854	1			T7	6		T9	7		T10	14
valid_sources[0x01]	29332	1			T9	1		T10	7		T11	7
valid_sources[0x02]	33090	1			T9	2		T10	14		T11	8
valid_sources[0x03]	33109	1			T7	8		T9	3		T10	6
valid_sources[0x04]	32214	1			T7	9		T9	2		T10	11
valid_sources[0x05]	31217	1			T7	4		T9	2		T10	4
valid_sources[0x06]	33483	1			T5	1		T7	2		T9	5
valid_sources[0x07]	34931	1			T6	9		T7	8		T9	2
valid_sources[0x08]	33555	1			T7	5		T9	5		T10	14
valid_sources[0x09]	32292	1			T6	1		T7	6		T9	4
valid_sources[0x0a]	36056	1			T7	1		T9	11		T10	11
valid_sources[0x0b]	33974	1			T9	1		T10	20		T11	3
valid_sources[0x0c]	31103	1			T7	17		T9	8		T10	11
valid_sources[0x0d]	37032	1			T9	4		T10	10		T11	11
valid_sources[0x0e]	34740	1			T9	5		T10	9		T11	5
valid_sources[0x0f]	33610	1			T7	2		T9	6		T10	15
valid_sources[0x10]	32835	1			T9	9		T10	13		T11	9
valid_sources[0x11]	30863	1			T9	5		T10	13		T11	5
valid_sources[0x12]	34733	1			T7	4		T10	11		T11	6
valid_sources[0x13]	32242	1			T7	2		T10	14		T11	7
valid_sources[0x14]	30551	1			T7	4		T9	5		T10	9
valid_sources[0x15]	32587	1			T9	3		T10	13		T11	11
valid_sources[0x16]	36622	1			T9	6		T10	5		T11	10
valid_sources[0x17]	33915	1			T9	3		T10	13		T11	7
valid_sources[0x18]	31599	1			T9	2		T10	8		T11	4
valid_sources[0x19]	36867	1			T6	19		T9	1		T10	12
valid_sources[0x1a]	30783	1			T7	6		T9	3		T10	13
valid_sources[0x1b]	33482	1			T7	1		T10	11		T11	8
valid_sources[0x1c]	34897	1			T9	2		T10	13		T11	6
valid_sources[0x1d]	35917	1			T7	2		T9	3		T10	14
valid_sources[0x1e]	30164	1			T9	6		T10	13		T11	5
valid_sources[0x1f]	36043	1			T7	8		T9	3		T10	9
valid_sources[0x20]	32742	1			T7	4		T9	2		T10	4
valid_sources[0x21]	30548	1			T7	4		T9	2		T10	10
valid_sources[0x22]	32646	1			T7	6		T9	7		T10	10
valid_sources[0x23]	36102	1			T7	8		T9	6		T10	8
valid_sources[0x24]	32812	1			T7	1		T9	2		T10	8
valid_sources[0x25]	31086	1			T9	2		T10	9		T11	5
valid_sources[0x26]	33167	1			T7	4		T9	5		T10	15
valid_sources[0x27]	42182	1			T6	13		T7	1		T9	1
valid_sources[0x28]	33440	1			T7	5		T9	4		T10	9
valid_sources[0x29]	31456	1			T7	8		T10	15		T11	7
valid_sources[0x2a]	35401	1			T7	12		T9	6		T10	12
valid_sources[0x2b]	35776	1			T6	48		T7	2		T9	5
valid_sources[0x2c]	31857	1			T7	8		T9	1		T10	12
valid_sources[0x2d]	42213	1			T7	10		T9	3		T10	11
valid_sources[0x2e]	43263	1			T6	1		T7	8		T9	3
valid_sources[0x2f]	31918	1			T7	11		T9	1		T10	3
valid_sources[0x30]	40542	1			T7	4		T9	5		T10	9
valid_sources[0x31]	32669	1			T7	2		T9	3		T10	15
valid_sources[0x32]	37194	1			T7	7		T10	7		T11	8
valid_sources[0x33]	31985	1			T7	3		T9	9		T10	11
valid_sources[0x34]	31065	1			T7	1		T9	4		T10	17
valid_sources[0x35]	31710	1			T7	1		T9	1		T10	18
valid_sources[0x36]	31437	1			T6	8		T7	1		T9	3
valid_sources[0x37]	31711	1			T7	2		T9	7		T10	11
valid_sources[0x38]	32022	1			T7	1		T9	3		T10	12
valid_sources[0x39]	32097	1			T6	18		T7	7		T9	4
valid_sources[0x3a]	33909	1			T7	1		T9	4		T10	13
valid_sources[0x3b]	37488	1			T6	17		T7	1		T9	3
valid_sources[0x3c]	33203	1			T7	2		T9	3		T10	14
valid_sources[0x3d]	31391	1			T7	1		T9	5		T10	15
valid_sources[0x3e]	34279	1			T7	5		T9	2		T10	9
valid_sources[0x3f]	32014	1			T7	11		T9	4		T10	9
valid_sources[0x40]	30565	1			T7	1		T9	2		T10	11
valid_sources[0x41]	33010	1			T7	2		T9	3		T10	11
valid_sources[0x42]	34880	1			T7	7		T9	4		T10	18
valid_sources[0x43]	31890	1			T7	2		T9	3		T10	13
valid_sources[0x44]	35213	1			T7	3		T9	2		T10	12
valid_sources[0x45]	33236	1			T7	1		T9	5		T10	12
valid_sources[0x46]	44759	1			T9	8		T10	13		T11	6
valid_sources[0x47]	35449	1			T6	12		T7	7		T9	6
valid_sources[0x48]	32067	1			T7	6		T9	6		T10	12
valid_sources[0x49]	35342	1			T7	8		T9	1		T10	5
valid_sources[0x4a]	30648	1			T6	50		T7	8		T9	3
valid_sources[0x4b]	33183	1			T6	34		T7	5		T9	3
valid_sources[0x4c]	34946	1			T6	11		T7	6		T9	5
valid_sources[0x4d]	30657	1			T7	2		T9	3		T10	7
valid_sources[0x4e]	30178	1			T9	4		T10	6		T11	8
valid_sources[0x4f]	34297	1			T7	3		T9	6		T10	14
valid_sources[0x50]	31276	1			T6	4		T7	2		T10	11
valid_sources[0x51]	31033	1			T7	3		T9	2		T10	13
valid_sources[0x52]	32650	1			T9	2		T10	15		T11	10
valid_sources[0x53]	38146	1			T7	5		T9	4		T10	12
valid_sources[0x54]	35856	1			T9	1		T10	14		T11	9
valid_sources[0x55]	32423	1			T7	5		T9	4		T10	8
valid_sources[0x56]	31761	1			T7	7		T9	2		T10	12
valid_sources[0x57]	35811	1			T7	1		T9	3		T10	5
valid_sources[0x58]	35135	1			T7	2		T9	5		T10	7
valid_sources[0x59]	30694	1			T2	1		T7	2		T9	3
valid_sources[0x5a]	31085	1			T7	2		T9	3		T10	10
valid_sources[0x5b]	30757	1			T9	3		T10	12		T11	9
valid_sources[0x5c]	32852	1			T6	26		T9	6		T10	6
valid_sources[0x5d]	34126	1			T6	1		T9	2		T10	11
valid_sources[0x5e]	32101	1			T7	1		T9	6		T10	15
valid_sources[0x5f]	29775	1			T9	7		T10	15		T11	10
valid_sources[0x60]	29594	1			T7	1		T9	8		T10	11
valid_sources[0x61]	29039	1			T7	4		T9	5		T10	12
valid_sources[0x62]	33142	1			T7	3		T9	11		T10	9
valid_sources[0x63]	32392	1			T7	14		T9	1		T10	9
valid_sources[0x64]	31754	1			T6	11		T7	6		T9	1
valid_sources[0x65]	30576	1			T7	1		T10	14		T11	5
valid_sources[0x66]	39651	1			T9	7		T10	11		T11	10
valid_sources[0x67]	33608	1			T7	2		T9	7		T10	14
valid_sources[0x68]	31398	1			T7	1		T9	5		T10	10
valid_sources[0x69]	30540	1			T10	10		T11	6		T13	14
valid_sources[0x6a]	32687	1			T7	4		T9	3		T10	10
valid_sources[0x6b]	33894	1			T7	1		T9	7		T10	8
valid_sources[0x6c]	31917	1			T7	6		T9	2		T10	16
valid_sources[0x6d]	33378	1			T7	2		T9	2		T10	22
valid_sources[0x6e]	31919	1			T9	4		T10	16		T11	11
valid_sources[0x6f]	31261	1			T7	3		T9	1		T10	7
valid_sources[0x70]	34247	1			T7	9		T9	6		T10	3
valid_sources[0x71]	31562	1			T9	2		T10	13		T11	6
valid_sources[0x72]	32867	1			T7	4		T9	2		T10	10
valid_sources[0x73]	34219	1			T10	11		T11	5		T13	15
valid_sources[0x74]	65578	1			T9	5		T10	10		T11	4
valid_sources[0x75]	33328	1			T6	41		T7	1		T10	11
valid_sources[0x76]	34438	1			T7	1		T9	7		T10	13
valid_sources[0x77]	30714	1			T7	6		T9	5		T10	15
valid_sources[0x78]	32235	1			T6	57		T7	2		T9	2
valid_sources[0x79]	36559	1			T7	2		T9	5		T10	9
valid_sources[0x7a]	40289	1			T7	6		T9	3		T10	5
valid_sources[0x7b]	34349	1			T7	1		T9	5		T10	14
valid_sources[0x7c]	34100	1			T7	4		T9	4		T10	26
valid_sources[0x7d]	35369	1			T9	3		T10	7		T11	11
valid_sources[0x7e]	37713	1			T6	32		T7	2		T9	6
valid_sources[0x7f]	44478	1			T7	10		T9	1		T10	8
valid_sources[0x80]	33355	1			T6	33		T7	4		T9	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1151370

1

T4

1

T5

1

T6

93

values[0x0]

all_enables

biggest_size

1765275

1

T4

5

T6

155

T7

438

values[0x1]

all_enables

biggest_size

1739310

1

T4

3

T6

145

T7

441