Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

4056288

1

T1

79

T2

1

T3

1

full_word

4657407

1

T4

9

T5

1

T6

393

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8713275	1			T1	79		T2	1		T3	1
auto[TlIntgErrCmd]	129	1			T114	10		T115	5		T116	4
auto[TlIntgErrData]	132	1			T114	8		T115	6		T116	11
auto[TlIntgErrBoth]	159	1			T114	12		T115	9		T116	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4816941

1

T1

79

T2

1

T3

1

auto[1]

3896754

1

T4

10

T5

1

T6

376

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3664950	1			T1	79		T2	1		T3	1
auto[TlIntgErrNone]	partial	auto[1]	390946	1			T4	2		T5	1		T6	76
auto[TlIntgErrNone]	full_word	auto[0]	1151798	1			T4	1		T5	1		T6	93
auto[TlIntgErrNone]	full_word	auto[1]	3505581	1			T4	8		T6	300		T7	879
auto[TlIntgErrCmd]	partial	auto[0]	45	1			T114	3		T115	5		T116	4
auto[TlIntgErrCmd]	partial	auto[1]	74	1			T114	6		T126	6		T203	3
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T114	1		T203	1		T174	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T204	1		T205	1		T206	1
auto[TlIntgErrData]	partial	auto[0]	60	1			T114	4		T115	1		T116	5
auto[TlIntgErrData]	partial	auto[1]	61	1			T114	3		T115	5		T116	4
auto[TlIntgErrData]	full_word	auto[0]	4	1			T126	1		T201	1		T207	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T114	1		T116	2		T126	2
auto[TlIntgErrBoth]	partial	auto[0]	76	1			T114	8		T115	3		T116	1
auto[TlIntgErrBoth]	partial	auto[1]	76	1			T114	4		T115	5		T116	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T115	1		T206	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T116	2		T204	1		T206	1