Module Definition
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Module Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.52 95.20 84.31 97.00 90.62 95.45 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.52 95.20 84.31 97.00 90.62 95.45 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_upload.u_payloadptr_clr_psync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.37 100.00 86.11 100.00 95.74 100.00 u_upload


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00

Line Coverage for Module : prim_pulse_sync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T3  32 1/1 src_level <= 1'b0; Tests: T1 T2 T3  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T4 T6 T7  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T3  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T3  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T3  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T3 

Cond Coverage for Module : prim_pulse_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T6,T7
01CoveredT12,T13,T45
10CoveredT12,T13,T45
11CoveredT12,T13,T45

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT12,T13,T45
10CoveredT12,T13,T45
11CoveredT12,T13,T45

Branch Coverage for Module : prim_pulse_sync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T4,T6,T7


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_pulse_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1489308231 2945 0 0
SrcPulseCheck_M 487616589 2945 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1489308231 2945 0 0
T12 344816 7 0 0
T13 121233 2 0 0
T14 1020699 0 0 0
T15 699483 0 0 0
T16 16977 0 0 0
T17 5916 0 0 0
T23 0 18 0 0
T24 78324 0 0 0
T25 15666 0 0 0
T26 3036 0 0 0
T27 369399 0 0 0
T40 0 11 0 0
T41 0 15 0 0
T44 0 6 0 0
T45 0 7 0 0
T46 0 7 0 0
T51 0 6 0 0
T52 0 1 0 0
T59 0 1 0 0
T63 0 2 0 0
T88 0 2 0 0
T90 3483 0 0 0
T109 0 7 0 0
T111 0 7 0 0
T163 0 7 0 0
T164 0 1 0 0
T165 0 7 0 0
T166 0 15 0 0
T167 0 2 0 0
T168 0 2 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 487616589 2945 0 0
T12 43406 7 0 0
T13 271758 2 0 0
T14 123540 0 0 0
T15 95967 0 0 0
T18 560985 0 0 0
T19 53535 0 0 0
T23 0 18 0 0
T24 271014 0 0 0
T25 2649 0 0 0
T26 1368 0 0 0
T27 251568 0 0 0
T40 0 11 0 0
T41 0 15 0 0
T44 0 6 0 0
T45 0 7 0 0
T46 0 7 0 0
T51 0 6 0 0
T52 0 1 0 0
T59 0 1 0 0
T63 0 2 0 0
T69 29568 0 0 0
T88 0 2 0 0
T109 0 7 0 0
T111 0 7 0 0
T163 0 7 0 0
T164 0 1 0 0
T165 0 7 0 0
T166 0 15 0 0
T167 0 2 0 0
T168 0 2 0 0

Line Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T3  32 1/1 src_level <= 1'b0; Tests: T1 T2 T3  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T4 T6 T7  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T3  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T3  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T3  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T6,T7
01CoveredT12,T45,T46
10CoveredT12,T45,T46
11CoveredT12,T45,T46

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT12,T45,T46
10CoveredT12,T45,T46
11CoveredT12,T45,T46

Branch Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T4,T6,T7


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 496436077 169 0 0
SrcPulseCheck_M 162538863 169 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 496436077 169 0 0
T12 172408 2 0 0
T13 40411 0 0 0
T14 340233 0 0 0
T15 233161 0 0 0
T16 5659 0 0 0
T17 1972 0 0 0
T24 26108 0 0 0
T25 5222 0 0 0
T26 1012 0 0 0
T45 0 2 0 0
T46 0 2 0 0
T90 1161 0 0 0
T109 0 2 0 0
T111 0 2 0 0
T163 0 2 0 0
T165 0 2 0 0
T166 0 8 0 0
T167 0 2 0 0
T168 0 2 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 162538863 169 0 0
T12 21703 2 0 0
T13 90586 0 0 0
T14 41180 0 0 0
T15 31989 0 0 0
T18 186995 0 0 0
T19 17845 0 0 0
T24 90338 0 0 0
T25 883 0 0 0
T26 456 0 0 0
T27 83856 0 0 0
T45 0 2 0 0
T46 0 2 0 0
T109 0 2 0 0
T111 0 2 0 0
T163 0 2 0 0
T165 0 2 0 0
T166 0 8 0 0
T167 0 2 0 0
T168 0 2 0 0

Line Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T3  32 1/1 src_level <= 1'b0; Tests: T1 T2 T3  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T4 T6 T7  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T3  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T3  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T3  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T6,T7
01CoveredT12,T45,T46
10CoveredT12,T45,T46
11CoveredT12,T45,T46

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT12,T45,T46
10CoveredT12,T45,T46
11CoveredT12,T45,T46

Branch Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T4,T6,T7


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 496436077 313 0 0
SrcPulseCheck_M 162538863 313 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 496436077 313 0 0
T12 172408 5 0 0
T13 40411 0 0 0
T14 340233 0 0 0
T15 233161 0 0 0
T16 5659 0 0 0
T17 1972 0 0 0
T24 26108 0 0 0
T25 5222 0 0 0
T26 1012 0 0 0
T45 0 5 0 0
T46 0 5 0 0
T52 0 1 0 0
T90 1161 0 0 0
T109 0 5 0 0
T111 0 5 0 0
T163 0 5 0 0
T164 0 1 0 0
T165 0 5 0 0
T166 0 7 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 162538863 313 0 0
T12 21703 5 0 0
T13 90586 0 0 0
T14 41180 0 0 0
T15 31989 0 0 0
T18 186995 0 0 0
T19 17845 0 0 0
T24 90338 0 0 0
T25 883 0 0 0
T26 456 0 0 0
T27 83856 0 0 0
T45 0 5 0 0
T46 0 5 0 0
T52 0 1 0 0
T109 0 5 0 0
T111 0 5 0 0
T163 0 5 0 0
T164 0 1 0 0
T165 0 5 0 0
T166 0 7 0 0

Line Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00

30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 31 1/1 if (!rst_src_ni) begin Tests: T1 T2 T3  32 1/1 src_level <= 1'b0; Tests: T1 T2 T3  33 end else begin 34 1/1 src_level <= src_level ^ src_pulse_i; Tests: T4 T6 T7  35 end 36 end 37 38 39 // source active must come far enough such that the destination domain has time 40 // to create a valid pulse. 41 `ifdef INC_ASSERT 42 //VCS coverage off 43 // pragma coverage off 44 45 // source active flag tracks whether there is an ongoing "toggle" event. 46 // Until this toggle event is accepted by the destination domain (negative edge of 47 // of the pulse output), the source side cannot toggle again. 48 logic effective_rst_n; 49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o; 50 51 logic src_active_flag_d, src_active_flag_q; 52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q; 53 54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 55 unreachable if (!effective_rst_n) begin 56 unreachable src_active_flag_q <= '0; 57 end else begin 58 unreachable src_active_flag_q <= src_active_flag_d; 59 end 60 end 61 62 //VCS coverage on 63 // pragma coverage on 64 65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni) 66 `endif 67 68 ////////////////////////////////////////////////////////// 69 // synchronize level signal to destination clock domain // 70 ////////////////////////////////////////////////////////// 71 logic dst_level; 72 73 prim_flop_2sync #(.Width(1)) prim_flop_2sync ( 74 // source clock domain 75 .d_i (src_level), 76 // destination clock domain 77 .clk_i (clk_dst_i), 78 .rst_ni (rst_dst_ni), 79 .q_o (dst_level) 80 ); 81 82 //////////////////////////////////////// 83 // convert level signal back to pulse // 84 //////////////////////////////////////// 85 logic dst_level_q; 86 87 // delay dst_level by 1 cycle 88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 89 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T3  90 1/1 dst_level_q <= 1'b0; Tests: T1 T2 T3  91 end else begin 92 1/1 dst_level_q <= dst_level; Tests: T1 T2 T3  93 end 94 end 95 96 // edge detection 97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT4,T6,T7
01CoveredT13,T41,T40
10CoveredT13,T41,T40
11CoveredT13,T41,T40

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT13,T41,T40
10CoveredT13,T41,T40
11CoveredT13,T41,T40

Branch Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00


31 if (!rst_src_ni) begin -1- 32 src_level <= 1'b0; ==> 33 end else begin 34 src_level <= src_level ^ src_pulse_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T4,T6,T7


89 if (!rst_dst_ni) begin -1- 90 dst_level_q <= 1'b0; ==> 91 end else begin 92 dst_level_q <= dst_level; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 496436077 2463 0 0
SrcPulseCheck_M 162538863 2463 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 496436077 2463 0 0
T13 40411 2 0 0
T14 340233 0 0 0
T15 233161 0 0 0
T16 5659 0 0 0
T17 1972 0 0 0
T23 0 18 0 0
T24 26108 0 0 0
T25 5222 0 0 0
T26 1012 0 0 0
T27 369399 0 0 0
T40 0 11 0 0
T41 0 15 0 0
T44 0 6 0 0
T51 0 6 0 0
T59 0 1 0 0
T63 0 2 0 0
T88 0 2 0 0
T89 0 6 0 0
T90 1161 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 162538863 2463 0 0
T13 90586 2 0 0
T14 41180 0 0 0
T15 31989 0 0 0
T18 186995 0 0 0
T19 17845 0 0 0
T23 0 18 0 0
T24 90338 0 0 0
T25 883 0 0 0
T26 456 0 0 0
T27 83856 0 0 0
T40 0 11 0 0
T41 0 15 0 0
T44 0 6 0 0
T51 0 6 0 0
T59 0 1 0 0
T63 0 2 0 0
T69 29568 0 0 0
T88 0 2 0 0
T89 0 6 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%