Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	498654727	3127483	0	0
DepthKnown_A	498654727	498521483	0	0
RvalidKnown_A	498654727	498521483	0	0
WreadyKnown_A	498654727	498521483	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	3127483	0	0
T7	21948	1669	0	0
T8	199299	0	0	0
T9	161030	832	0	0
T10	52079	832	0	0
T11	50752	1663	0	0
T12	172408	832	0	0
T13	40411	3328	0	0
T14	340233	832	0	0
T15	233161	832	0	0
T16	5659	0	0	0
T18	0	1663	0	0
T19	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	498521483	0	0
T1	1887	1813	0	0
T2	7816	5431	0	0
T3	703	625	0	0
T4	1835	1765	0	0
T5	1281	1186	0	0
T6	35957	35883	0	0
T7	21948	21894	0	0
T8	199299	199205	0	0
T9	161030	160931	0	0
T10	52079	52007	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	498521483	0	0
T1	1887	1813	0	0
T2	7816	5431	0	0
T3	703	625	0	0
T4	1835	1765	0	0
T5	1281	1186	0	0
T6	35957	35883	0	0
T7	21948	21894	0	0
T8	199299	199205	0	0
T9	161030	160931	0	0
T10	52079	52007	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	498521483	0	0
T1	1887	1813	0	0
T2	7816	5431	0	0
T3	703	625	0	0
T4	1835	1765	0	0
T5	1281	1186	0	0
T6	35957	35883	0	0
T7	21948	21894	0	0
T8	199299	199205	0	0
T9	161030	160931	0	0
T10	52079	52007	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	498654727	3247096	0	0
DepthKnown_A	498654727	498521483	0	0
RvalidKnown_A	498654727	498521483	0	0
WreadyKnown_A	498654727	498521483	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	3247096	0	0
T7	21948	839	0	0
T8	199299	0	0	0
T9	161030	832	0	0
T10	52079	3800	0	0
T11	50752	832	0	0
T12	172408	832	0	0
T13	40411	3328	0	0
T14	340233	3783	0	0
T15	233161	2663	0	0
T16	5659	0	0	0
T18	0	832	0	0
T19	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	498521483	0	0
T1	1887	1813	0	0
T2	7816	5431	0	0
T3	703	625	0	0
T4	1835	1765	0	0
T5	1281	1186	0	0
T6	35957	35883	0	0
T7	21948	21894	0	0
T8	199299	199205	0	0
T9	161030	160931	0	0
T10	52079	52007	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	498521483	0	0
T1	1887	1813	0	0
T2	7816	5431	0	0
T3	703	625	0	0
T4	1835	1765	0	0
T5	1281	1186	0	0
T6	35957	35883	0	0
T7	21948	21894	0	0
T8	199299	199205	0	0
T9	161030	160931	0	0
T10	52079	52007	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	498521483	0	0
T1	1887	1813	0	0
T2	7816	5431	0	0
T3	703	625	0	0
T4	1835	1765	0	0
T5	1281	1186	0	0
T6	35957	35883	0	0
T7	21948	21894	0	0
T8	199299	199205	0	0
T9	161030	160931	0	0
T10	52079	52007	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	498654727	203241	0	0
DepthKnown_A	498654727	498521483	0	0
RvalidKnown_A	498654727	498521483	0	0
WreadyKnown_A	498654727	498521483	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	203241	0	0
T6	35957	67	0	0
T7	21948	0	0	0
T8	199299	0	0	0
T9	161030	0	0	0
T10	52079	0	0	0
T11	50752	0	0	0
T12	172408	0	0	0
T13	40411	0	0	0
T14	340233	0	0	0
T15	233161	0	0	0
T24	0	261	0	0
T26	0	2	0	0
T31	0	80	0	0
T36	0	218	0	0
T40	0	416	0	0
T41	0	380	0	0
T42	0	219	0	0
T43	0	19	0	0
T44	0	806	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	498521483	0	0
T1	1887	1813	0	0
T2	7816	5431	0	0
T3	703	625	0	0
T4	1835	1765	0	0
T5	1281	1186	0	0
T6	35957	35883	0	0
T7	21948	21894	0	0
T8	199299	199205	0	0
T9	161030	160931	0	0
T10	52079	52007	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	498521483	0	0
T1	1887	1813	0	0
T2	7816	5431	0	0
T3	703	625	0	0
T4	1835	1765	0	0
T5	1281	1186	0	0
T6	35957	35883	0	0
T7	21948	21894	0	0
T8	199299	199205	0	0
T9	161030	160931	0	0
T10	52079	52007	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	498521483	0	0
T1	1887	1813	0	0
T2	7816	5431	0	0
T3	703	625	0	0
T4	1835	1765	0	0
T5	1281	1186	0	0
T6	35957	35883	0	0
T7	21948	21894	0	0
T8	199299	199205	0	0
T9	161030	160931	0	0
T10	52079	52007	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	498654727	419075	0	0
DepthKnown_A	498654727	498521483	0	0
RvalidKnown_A	498654727	498521483	0	0
WreadyKnown_A	498654727	498521483	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	419075	0	0
T6	35957	67	0	0
T7	21948	0	0	0
T8	199299	0	0	0
T9	161030	0	0	0
T10	52079	0	0	0
T11	50752	0	0	0
T12	172408	0	0	0
T13	40411	0	0	0
T14	340233	0	0	0
T15	233161	0	0	0
T24	0	261	0	0
T26	0	2	0	0
T31	0	394	0	0
T36	0	1057	0	0
T40	0	1936	0	0
T41	0	380	0	0
T42	0	219	0	0
T43	0	19	0	0
T44	0	806	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	498521483	0	0
T1	1887	1813	0	0
T2	7816	5431	0	0
T3	703	625	0	0
T4	1835	1765	0	0
T5	1281	1186	0	0
T6	35957	35883	0	0
T7	21948	21894	0	0
T8	199299	199205	0	0
T9	161030	160931	0	0
T10	52079	52007	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	498521483	0	0
T1	1887	1813	0	0
T2	7816	5431	0	0
T3	703	625	0	0
T4	1835	1765	0	0
T5	1281	1186	0	0
T6	35957	35883	0	0
T7	21948	21894	0	0
T8	199299	199205	0	0
T9	161030	160931	0	0
T10	52079	52007	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	498521483	0	0
T1	1887	1813	0	0
T2	7816	5431	0	0
T3	703	625	0	0
T4	1835	1765	0	0
T5	1281	1186	0	0
T6	35957	35883	0	0
T7	21948	21894	0	0
T8	199299	199205	0	0
T9	161030	160931	0	0
T10	52079	52007	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	498654727	6879962	0	0
DepthKnown_A	498654727	498521483	0	0
RvalidKnown_A	498654727	498521483	0	0
WreadyKnown_A	498654727	498521483	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	6879962	0	0
T1	1887	79	0	0
T2	7816	1	0	0
T3	703	1	0	0
T4	1835	11	0	0
T5	1281	2	0	0
T6	35957	852	0	0
T7	21948	55	0	0
T8	199299	499	0	0
T9	161030	71	0	0
T10	52079	1968	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	498521483	0	0
T1	1887	1813	0	0
T2	7816	5431	0	0
T3	703	625	0	0
T4	1835	1765	0	0
T5	1281	1186	0	0
T6	35957	35883	0	0
T7	21948	21894	0	0
T8	199299	199205	0	0
T9	161030	160931	0	0
T10	52079	52007	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	498521483	0	0
T1	1887	1813	0	0
T2	7816	5431	0	0
T3	703	625	0	0
T4	1835	1765	0	0
T5	1281	1186	0	0
T6	35957	35883	0	0
T7	21948	21894	0	0
T8	199299	199205	0	0
T9	161030	160931	0	0
T10	52079	52007	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	498521483	0	0
T1	1887	1813	0	0
T2	7816	5431	0	0
T3	703	625	0	0
T4	1835	1765	0	0
T5	1281	1186	0	0
T6	35957	35883	0	0
T7	21948	21894	0	0
T8	199299	199205	0	0
T9	161030	160931	0	0
T10	52079	52007	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	498654727	12675231	0	0
DepthKnown_A	498654727	498521483	0	0
RvalidKnown_A	498654727	498521483	0	0
WreadyKnown_A	498654727	498521483	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	12675231	0	0
T1	1887	332	0	0
T2	7816	1	0	0
T3	703	1	0	0
T4	1835	11	0	0
T5	1281	2	0	0
T6	35957	851	0	0
T7	21948	233	0	0
T8	199299	499	0	0
T9	161030	71	0	0
T10	52079	8506	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	498521483	0	0
T1	1887	1813	0	0
T2	7816	5431	0	0
T3	703	625	0	0
T4	1835	1765	0	0
T5	1281	1186	0	0
T6	35957	35883	0	0
T7	21948	21894	0	0
T8	199299	199205	0	0
T9	161030	160931	0	0
T10	52079	52007	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	498521483	0	0
T1	1887	1813	0	0
T2	7816	5431	0	0
T3	703	625	0	0
T4	1835	1765	0	0
T5	1281	1186	0	0
T6	35957	35883	0	0
T7	21948	21894	0	0
T8	199299	199205	0	0
T9	161030	160931	0	0
T10	52079	52007	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	498521483	0	0
T1	1887	1813	0	0
T2	7816	5431	0	0
T3	703	625	0	0
T4	1835	1765	0	0
T5	1281	1186	0	0
T6	35957	35883	0	0
T7	21948	21894	0	0
T8	199299	199205	0	0
T9	161030	160931	0	0
T10	52079	52007	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0