Unified Coverage Report :: Module :: prim_slicer

Module : prim_slicer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_slicer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_hw_reg_slice	100.00	100.00					100.00

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Module Instance : tb.dut.u_spi_tpm.u_hw_reg_slice

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.79	99.29	91.20		91.67	96.77	100.00	u_spi_tpm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

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Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_slicer

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	25	1	1	100.00
CONT_ASSIGN	27	1	1	100.00

24                      
25         1/1            assign unrolled_data = UnrollW'(data_i);
           Tests:       T1 T2 T3 
26                      
27         1/1            assign data_o = unrolled_data[sel_i*OutW+:OutW];
           Tests:       T1 T2 T3 

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Assert Coverage for Module : prim_slicer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

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Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ValidWidth_A	956	956	0	0

ValidWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0