Unified Coverage Report :: Module :: spi_device_csr_assert_fpv

Module : spi_device_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_spi_device_csr_assert_0/spi_device_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.spi_device_csr_assert	100.00						100.00

---

Module Instance : tb.dut.spi_device_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : spi_device_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	58	58	100.00	58	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	58	58	100.00	58	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	498654727	3509	0	0
addr_swap_data_rd_A	498654727	629	0	0
addr_swap_mask_rd_A	498654727	562	0	0
cfg_rd_A	498654727	1237	0	0
cmd_filter_0_rd_A	498654727	7078	0	0
cmd_filter_1_rd_A	498654727	7064	0	0
cmd_filter_2_rd_A	498654727	6510	0	0
cmd_filter_3_rd_A	498654727	5947	0	0
cmd_filter_4_rd_A	498654727	7179	0	0
cmd_filter_5_rd_A	498654727	6842	0	0
cmd_filter_6_rd_A	498654727	6225	0	0
cmd_filter_7_rd_A	498654727	6879	0	0
cmd_info_0_rd_A	498654727	2828	0	0
cmd_info_10_rd_A	498654727	3020	0	0
cmd_info_11_rd_A	498654727	2975	0	0
cmd_info_12_rd_A	498654727	3206	0	0
cmd_info_13_rd_A	498654727	3270	0	0
cmd_info_14_rd_A	498654727	3302	0	0
cmd_info_15_rd_A	498654727	3225	0	0
cmd_info_16_rd_A	498654727	3424	0	0
cmd_info_17_rd_A	498654727	3074	0	0
cmd_info_18_rd_A	498654727	3324	0	0
cmd_info_19_rd_A	498654727	3423	0	0
cmd_info_1_rd_A	498654727	3300	0	0
cmd_info_20_rd_A	498654727	3095	0	0
cmd_info_21_rd_A	498654727	3525	0	0
cmd_info_22_rd_A	498654727	3066	0	0
cmd_info_23_rd_A	498654727	3641	0	0
cmd_info_2_rd_A	498654727	3017	0	0
cmd_info_3_rd_A	498654727	2494	0	0
cmd_info_4_rd_A	498654727	3173	0	0
cmd_info_5_rd_A	498654727	3580	0	0
cmd_info_6_rd_A	498654727	3458	0	0
cmd_info_7_rd_A	498654727	3145	0	0
cmd_info_8_rd_A	498654727	2994	0	0
cmd_info_9_rd_A	498654727	3357	0	0
cmd_info_en4b_rd_A	498654727	888	0	0
cmd_info_ex4b_rd_A	498654727	810	0	0
cmd_info_wrdi_rd_A	498654727	852	0	0
cmd_info_wren_rd_A	498654727	828	0	0
intercept_en_rd_A	498654727	1328	0	0
intr_enable_rd_A	498654727	2663	0	0
jedec_cc_rd_A	498654727	915	0	0
jedec_id_rd_A	498654727	956	0	0
mailbox_addr_rd_A	498654727	630	0	0
payload_swap_data_rd_A	498654727	707	0	0
payload_swap_mask_rd_A	498654727	580	0	0
read_threshold_rd_A	498654727	645	0	0
tpm_access_0_rd_A	498654727	1278	0	0
tpm_access_1_rd_A	498654727	764	0	0
tpm_cfg_rd_A	498654727	1574	0	0
tpm_did_vid_rd_A	498654727	889	0	0
tpm_int_enable_rd_A	498654727	514	0	0
tpm_int_status_rd_A	498654727	599	0	0
tpm_int_vector_rd_A	498654727	703	0	0
tpm_intf_capability_rd_A	498654727	674	0	0
tpm_rid_rd_A	498654727	614	0	0
tpm_sts_rd_A	498654727	656	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	3509	0	0
T93	5716	188	0	0
T94	10092	119	0	0
T95	15435	9	0	0
T112	10081	88	0	0
T113	2844	83	0	0
T114	29700	3	0	0
T123	9050	80	0	0
T129	4026	9	0	0
T131	4146	15	0	0
T132	12389	3	0	0

addr_swap_data_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	629	0	0
T95	15435	14	0	0
T103	2340	7	0	0
T125	13918	18	0	0
T140	4173	7	0	0
T144	10672	12	0	0
T169	6728	5	0	0
T170	4435	7	0	0
T171	5687	2	0	0
T172	6793	8	0	0
T173	7310	4	0	0

addr_swap_mask_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	562	0	0
T95	15435	26	0	0
T103	2340	5	0	0
T125	13918	37	0	0
T140	4173	17	0	0
T144	10672	17	0	0
T147	4356	3	0	0
T169	6728	15	0	0
T170	4435	6	0	0
T172	6793	4	0	0
T173	7310	7	0	0

cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	1237	0	0
T95	15435	63	0	0
T124	24421	6	0	0
T125	13918	53	0	0
T140	4173	6	0	0
T144	10672	34	0	0
T147	4356	1	0	0
T169	6728	29	0	0
T170	4435	4	0	0
T171	5687	12	0	0
T172	6793	12	0	0

cmd_filter_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	7078	0	0
T95	15435	254	0	0
T103	2340	3	0	0
T125	13918	244	0	0
T140	4173	14	0	0
T144	10672	251	0	0
T147	4356	96	0	0
T169	6728	124	0	0
T170	4435	7	0	0
T171	5687	3	0	0
T172	6793	1	0	0

cmd_filter_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	7064	0	0
T95	15435	161	0	0
T103	2340	1	0	0
T125	13918	224	0	0
T140	4173	16	0	0
T144	10672	128	0	0
T147	4356	107	0	0
T169	6728	16	0	0
T170	4435	2	0	0
T172	6793	12	0	0
T173	7310	10	0	0

cmd_filter_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	6510	0	0
T95	15435	128	0	0
T125	13918	169	0	0
T140	4173	18	0	0
T144	10672	250	0	0
T147	4356	108	0	0
T169	6728	136	0	0
T170	4435	3	0	0
T171	5687	144	0	0
T172	6793	10	0	0
T173	7310	77	0	0

cmd_filter_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	5947	0	0
T95	15435	287	0	0
T103	2340	6	0	0
T125	13918	21	0	0
T140	4173	13	0	0
T144	10672	267	0	0
T147	4356	117	0	0
T169	6728	144	0	0
T170	4435	7	0	0
T171	5687	13	0	0
T172	6793	5	0	0

cmd_filter_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	7179	0	0
T95	15435	384	0	0
T103	2340	2	0	0
T125	13918	235	0	0
T140	4173	9	0	0
T144	10672	14	0	0
T169	6728	152	0	0
T170	4435	113	0	0
T171	5687	152	0	0
T172	6793	11	0	0
T173	7310	129	0	0

cmd_filter_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	6842	0	0
T95	15435	32	0	0
T103	2340	4	0	0
T125	13918	154	0	0
T140	4173	6	0	0
T144	10672	134	0	0
T147	4356	110	0	0
T169	6728	135	0	0
T170	4435	6	0	0
T171	5687	13	0	0
T172	6793	23	0	0

cmd_filter_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	6225	0	0
T95	15435	141	0	0
T125	13918	128	0	0
T140	4173	7	0	0
T144	10672	136	0	0
T169	6728	123	0	0
T171	5687	143	0	0
T172	6793	1	0	0
T173	7310	104	0	0
T174	64325	698	0	0
T175	17108	41	0	0

cmd_filter_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	6879	0	0
T95	15435	264	0	0
T103	2340	2	0	0
T125	13918	237	0	0
T140	4173	16	0	0
T144	10672	257	0	0
T147	4356	111	0	0
T169	6728	256	0	0
T170	4435	119	0	0
T171	5687	6	0	0
T172	6793	25	0	0

cmd_info_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	2828	0	0
T95	15435	133	0	0
T125	13918	57	0	0
T140	4173	7	0	0
T144	10672	81	0	0
T169	6728	9	0	0
T170	4435	8	0	0
T171	5687	5	0	0
T172	6793	18	0	0
T173	7310	17	0	0
T174	64325	286	0	0

cmd_info_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	3020	0	0
T95	15435	77	0	0
T103	2340	5	0	0
T125	13918	142	0	0
T140	4173	10	0	0
T144	10672	70	0	0
T169	6728	5	0	0
T170	4435	6	0	0
T171	5687	79	0	0
T172	6793	12	0	0
T173	7310	29	0	0

cmd_info_11_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	2975	0	0
T95	15435	53	0	0
T103	2340	7	0	0
T125	13918	53	0	0
T140	4173	10	0	0
T144	10672	80	0	0
T147	4356	2	0	0
T169	6728	109	0	0
T170	4435	7	0	0
T171	5687	11	0	0
T172	6793	2	0	0

cmd_info_12_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	3206	0	0
T95	15435	26	0	0
T103	2340	9	0	0
T124	24421	10	0	0
T125	13918	69	0	0
T140	4173	12	0	0
T144	10672	55	0	0
T147	4356	50	0	0
T169	6728	8	0	0
T170	4435	37	0	0
T171	5687	29	0	0

cmd_info_13_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	3270	0	0
T95	15435	75	0	0
T125	13918	58	0	0
T140	4173	10	0	0
T144	10672	61	0	0
T147	4356	63	0	0
T169	6728	9	0	0
T170	4435	55	0	0
T171	5687	12	0	0
T172	6793	24	0	0
T173	7310	30	0	0

cmd_info_14_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	3302	0	0
T95	15435	96	0	0
T103	2340	3	0	0
T125	13918	79	0	0
T140	4173	5	0	0
T144	10672	47	0	0
T147	4356	39	0	0
T169	6728	53	0	0
T170	4435	68	0	0
T171	5687	56	0	0
T172	6793	12	0	0

cmd_info_15_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	3225	0	0
T95	15435	77	0	0
T103	2340	2	0	0
T125	13918	86	0	0
T140	4173	12	0	0
T144	10672	81	0	0
T147	4356	6	0	0
T169	6728	57	0	0
T170	4435	49	0	0
T171	5687	47	0	0
T172	6793	13	0	0

cmd_info_16_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	3424	0	0
T95	15435	115	0	0
T103	2340	3	0	0
T125	13918	68	0	0
T140	4173	21	0	0
T144	10672	83	0	0
T147	4356	63	0	0
T169	6728	4	0	0
T170	4435	1	0	0
T171	5687	3	0	0
T172	6793	5	0	0

cmd_info_17_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	3074	0	0
T95	15435	121	0	0
T103	2340	5	0	0
T125	13918	104	0	0
T140	4173	13	0	0
T144	10672	147	0	0
T147	4356	31	0	0
T169	6728	54	0	0
T170	4435	58	0	0
T171	5687	55	0	0
T172	6793	8	0	0

cmd_info_18_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	3324	0	0
T95	15435	173	0	0
T103	2340	6	0	0
T125	13918	54	0	0
T140	4173	9	0	0
T144	10672	79	0	0
T169	6728	47	0	0
T170	4435	1	0	0
T171	5687	47	0	0
T172	6793	20	0	0
T173	7310	33	0	0

cmd_info_19_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	3423	0	0
T95	15435	176	0	0
T122	19005	7	0	0
T125	13918	110	0	0
T140	4173	4	0	0
T144	10672	99	0	0
T147	4356	46	0	0
T169	6728	80	0	0
T170	4435	68	0	0
T171	5687	13	0	0
T172	6793	15	0	0

cmd_info_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	3300	0	0
T95	15435	39	0	0
T103	2340	7	0	0
T125	13918	91	0	0
T140	4173	14	0	0
T144	10672	34	0	0
T147	4356	59	0	0
T169	6728	72	0	0
T170	4435	2	0	0
T172	6793	9	0	0
T173	7310	45	0	0

cmd_info_20_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	3095	0	0
T95	15435	105	0	0
T122	19005	1	0	0
T125	13918	18	0	0
T140	4173	9	0	0
T144	10672	129	0	0
T169	6728	46	0	0
T170	4435	47	0	0
T171	5687	48	0	0
T172	6793	18	0	0
T173	7310	29	0	0

cmd_info_21_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	3525	0	0
T95	15435	72	0	0
T103	2340	9	0	0
T122	19005	6	0	0
T125	13918	78	0	0
T128	17425	3	0	0
T140	4173	11	0	0
T144	10672	118	0	0
T169	6728	130	0	0
T170	4435	39	0	0
T171	5687	59	0	0

cmd_info_22_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	3066	0	0
T95	15435	29	0	0
T103	2340	4	0	0
T125	13918	29	0	0
T140	4173	6	0	0
T144	10672	54	0	0
T147	4356	17	0	0
T169	6728	4	0	0
T170	4435	5	0	0
T171	5687	50	0	0
T172	6793	12	0	0

cmd_info_23_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	3641	0	0
T95	15435	120	0	0
T103	2340	3	0	0
T125	13918	107	0	0
T140	4173	17	0	0
T144	10672	84	0	0
T147	4356	38	0	0
T169	6728	59	0	0
T170	4435	5	0	0
T171	5687	56	0	0
T172	6793	6	0	0

cmd_info_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	3017	0	0
T95	15435	18	0	0
T103	2340	7	0	0
T125	13918	81	0	0
T140	4173	13	0	0
T144	10672	15	0	0
T147	4356	1	0	0
T169	6728	66	0	0
T170	4435	2	0	0
T171	5687	47	0	0
T172	6793	15	0	0

cmd_info_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	2494	0	0
T95	15435	98	0	0
T103	2340	5	0	0
T125	13918	21	0	0
T140	4173	18	0	0
T144	10672	45	0	0
T147	4356	33	0	0
T169	6728	5	0	0
T171	5687	8	0	0
T174	64325	200	0	0
T175	17108	22	0	0

cmd_info_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	3173	0	0
T95	15435	63	0	0
T103	2340	3	0	0
T125	13918	105	0	0
T140	4173	15	0	0
T144	10672	98	0	0
T147	4356	43	0	0
T169	6728	48	0	0
T170	4435	20	0	0
T171	5687	56	0	0
T172	6793	10	0	0

cmd_info_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	3580	0	0
T95	15435	77	0	0
T103	2340	3	0	0
T125	13918	162	0	0
T140	4173	13	0	0
T144	10672	63	0	0
T169	6728	11	0	0
T170	4435	63	0	0
T171	5687	62	0	0
T172	6793	18	0	0
T173	7310	20	0	0

cmd_info_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	3458	0	0
T95	15435	71	0	0
T103	2340	3	0	0
T125	13918	91	0	0
T140	4173	14	0	0
T144	10672	77	0	0
T169	6728	67	0	0
T170	4435	43	0	0
T171	5687	63	0	0
T172	6793	32	0	0
T173	7310	2	0	0

cmd_info_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	3145	0	0
T95	15435	96	0	0
T103	2340	2	0	0
T125	13918	85	0	0
T140	4173	11	0	0
T144	10672	97	0	0
T147	4356	32	0	0
T169	6728	56	0	0
T170	4435	45	0	0
T171	5687	11	0	0
T172	6793	15	0	0

cmd_info_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	2994	0	0
T95	15435	159	0	0
T103	2340	4	0	0
T125	13918	69	0	0
T140	4173	13	0	0
T144	10672	67	0	0
T147	4356	41	0	0
T169	6728	67	0	0
T170	4435	61	0	0
T171	5687	13	0	0
T172	6793	13	0	0

cmd_info_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	3357	0	0
T95	15435	71	0	0
T103	2340	5	0	0
T125	13918	98	0	0
T140	4173	13	0	0
T144	10672	41	0	0
T147	4356	49	0	0
T169	6728	7	0	0
T170	4435	63	0	0
T171	5687	61	0	0
T172	6793	16	0	0

cmd_info_en4b_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	888	0	0
T95	15435	30	0	0
T103	2340	2	0	0
T125	13918	28	0	0
T140	4173	11	0	0
T144	10672	15	0	0
T147	4356	4	0	0
T169	6728	10	0	0
T170	4435	1	0	0
T171	5687	9	0	0
T172	6793	31	0	0

cmd_info_ex4b_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	810	0	0
T95	15435	33	0	0
T103	2340	6	0	0
T125	13918	25	0	0
T140	4173	16	0	0
T144	10672	15	0	0
T147	4356	9	0	0
T169	6728	7	0	0
T170	4435	1	0	0
T171	5687	6	0	0
T172	6793	26	0	0

cmd_info_wrdi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	852	0	0
T95	15435	36	0	0
T103	2340	2	0	0
T125	13918	20	0	0
T140	4173	5	0	0
T144	10672	24	0	0
T169	6728	4	0	0
T170	4435	6	0	0
T171	5687	11	0	0
T172	6793	7	0	0
T174	64325	61	0	0

cmd_info_wren_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	828	0	0
T95	15435	10	0	0
T125	13918	17	0	0
T140	4173	1	0	0
T144	10672	9	0	0
T147	4356	9	0	0
T169	6728	18	0	0
T170	4435	6	0	0
T171	5687	14	0	0
T172	6793	28	0	0
T174	64325	59	0	0

intercept_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	1328	0	0
T95	15435	48	0	0
T103	2340	3	0	0
T125	13918	16	0	0
T140	4173	20	0	0
T144	10672	33	0	0
T147	4356	11	0	0
T169	6728	37	0	0
T170	4435	9	0	0
T171	5687	7	0	0
T172	6793	16	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	2663	0	0
T33	6693	22	0	0
T34	0	55	0	0
T71	0	7	0	0
T85	0	50	0	0
T97	100182	0	0	0
T176	0	3	0	0
T177	0	71	0	0
T178	0	26	0	0
T179	0	47	0	0
T180	0	42	0	0
T181	0	22	0	0
T182	1125	0	0	0
T183	1316	0	0	0
T184	42252	0	0	0
T185	84102	0	0	0
T186	374186	0	0	0
T187	1071	0	0	0
T188	373861	0	0	0
T189	7817	0	0	0

jedec_cc_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	915	0	0
T95	15435	25	0	0
T103	2340	6	0	0
T125	13918	30	0	0
T140	4173	11	0	0
T144	10672	15	0	0
T147	4356	11	0	0
T169	6728	14	0	0
T170	4435	5	0	0
T171	5687	14	0	0
T172	6793	15	0	0

jedec_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	956	0	0
T95	15435	18	0	0
T125	13918	36	0	0
T140	4173	8	0	0
T144	10672	15	0	0
T147	4356	13	0	0
T169	6728	10	0	0
T170	4435	8	0	0
T171	5687	17	0	0
T172	6793	37	0	0
T173	7310	3	0	0

mailbox_addr_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	630	0	0
T95	15435	22	0	0
T103	2340	9	0	0
T125	13918	20	0	0
T140	4173	5	0	0
T144	10672	12	0	0
T169	6728	6	0	0
T170	4435	7	0	0
T171	5687	7	0	0
T172	6793	8	0	0
T173	7310	7	0	0

payload_swap_data_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	707	0	0
T95	15435	17	0	0
T103	2340	8	0	0
T125	13918	28	0	0
T140	4173	8	0	0
T144	10672	11	0	0
T147	4356	2	0	0
T169	6728	13	0	0
T170	4435	7	0	0
T171	5687	14	0	0
T172	6793	13	0	0

payload_swap_mask_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	580	0	0
T95	15435	17	0	0
T103	2340	3	0	0
T125	13918	18	0	0
T140	4173	15	0	0
T144	10672	12	0	0
T147	4356	1	0	0
T169	6728	7	0	0
T170	4435	2	0	0
T171	5687	3	0	0
T172	6793	14	0	0

read_threshold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	645	0	0
T95	15435	13	0	0
T103	2340	2	0	0
T125	13918	15	0	0
T140	4173	22	0	0
T144	10672	23	0	0
T147	4356	3	0	0
T169	6728	13	0	0
T170	4435	9	0	0
T171	5687	9	0	0
T172	6793	11	0	0

tpm_access_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	1278	0	0
T95	15435	49	0	0
T103	2340	3	0	0
T124	24421	9	0	0
T125	13918	35	0	0
T140	4173	7	0	0
T144	10672	14	0	0
T147	4356	22	0	0
T169	6728	44	0	0
T170	4435	5	0	0
T171	5687	6	0	0

tpm_access_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	764	0	0
T95	15435	35	0	0
T103	2340	1	0	0
T125	13918	30	0	0
T140	4173	4	0	0
T144	10672	20	0	0
T147	4356	8	0	0
T169	6728	8	0	0
T171	5687	17	0	0
T172	6793	32	0	0
T174	64325	29	0	0

tpm_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	1574	0	0
T95	15435	14	0	0
T103	2340	6	0	0
T125	13918	33	0	0
T140	4173	10	0	0
T144	10672	46	0	0
T169	6728	36	0	0
T170	4435	19	0	0
T171	5687	26	0	0
T172	6793	7	0	0
T173	7310	5	0	0

tpm_did_vid_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	889	0	0
T95	15435	13	0	0
T103	2340	5	0	0
T125	13918	39	0	0
T140	4173	13	0	0
T144	10672	20	0	0
T169	6728	20	0	0
T170	4435	2	0	0
T171	5687	5	0	0
T172	6793	8	0	0
T173	7310	7	0	0

tpm_int_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	514	0	0
T95	15435	16	0	0
T103	2340	3	0	0
T125	13918	28	0	0
T140	4173	12	0	0
T144	10672	15	0	0
T147	4356	3	0	0
T170	4435	3	0	0
T171	5687	9	0	0
T172	6793	3	0	0
T173	7310	7	0	0

tpm_int_status_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	599	0	0
T95	15435	25	0	0
T103	2340	6	0	0
T125	13918	21	0	0
T140	4173	12	0	0
T144	10672	9	0	0
T147	4356	5	0	0
T169	6728	3	0	0
T170	4435	2	0	0
T171	5687	9	0	0
T172	6793	24	0	0

tpm_int_vector_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	703	0	0
T95	15435	36	0	0
T103	2340	1	0	0
T122	19005	2	0	0
T125	13918	23	0	0
T140	4173	17	0	0
T144	10672	22	0	0
T147	4356	1	0	0
T169	6728	12	0	0
T170	4435	9	0	0
T171	5687	9	0	0

tpm_intf_capability_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	674	0	0
T95	15435	32	0	0
T103	2340	7	0	0
T125	13918	15	0	0
T140	4173	10	0	0
T144	10672	3	0	0
T147	4356	2	0	0
T169	6728	9	0	0
T170	4435	5	0	0
T171	5687	3	0	0
T172	6793	11	0	0

tpm_rid_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	614	0	0
T95	15435	16	0	0
T103	2340	1	0	0
T125	13918	21	0	0
T140	4173	10	0	0
T144	10672	2	0	0
T169	6728	4	0	0
T170	4435	3	0	0
T171	5687	7	0	0
T172	6793	7	0	0
T173	7310	3	0	0

tpm_sts_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498654727	656	0	0
T95	15435	24	0	0
T103	2340	6	0	0
T125	13918	30	0	0
T140	4173	8	0	0
T144	10672	13	0	0
T147	4356	3	0	0
T169	6728	9	0	0
T170	4435	4	0	0
T171	5687	3	0	0
T172	6793	4	0	0