Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3867036	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4529531

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4610134	1			T1	1		T2	73		T3	1
values[0x0]	1892006	1			T4	13		T5	15		T6	437
values[0x1]	1894427	1			T4	12		T5	20		T6	472

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2740084	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5656483

1

T1

1

T2

20

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	30784	1			T6	3		T7	7		T8	5
valid_sources[0x01]	32731	1			T6	2		T7	4		T8	6
valid_sources[0x02]	30622	1			T6	5		T8	5		T9	6
valid_sources[0x03]	34253	1			T5	4		T6	2		T7	26
valid_sources[0x04]	31040	1			T6	3		T8	9		T9	9
valid_sources[0x05]	33032	1			T6	9		T8	4		T9	6
valid_sources[0x06]	34383	1			T6	2		T7	7		T8	1
valid_sources[0x07]	34068	1			T6	2		T7	4		T8	5
valid_sources[0x08]	30021	1			T6	5		T8	4		T9	7
valid_sources[0x09]	33659	1			T6	6		T7	6		T8	2
valid_sources[0x0a]	32354	1			T6	6		T8	7		T9	10
valid_sources[0x0b]	33258	1			T6	1		T8	2		T9	5
valid_sources[0x0c]	34958	1			T6	5		T8	16		T9	13
valid_sources[0x0d]	34291	1			T5	6		T6	1		T8	3
valid_sources[0x0e]	32109	1			T5	4		T6	8		T8	10
valid_sources[0x0f]	33068	1			T2	6		T5	8		T6	2
valid_sources[0x10]	29932	1			T6	3		T8	4		T9	18
valid_sources[0x11]	30647	1			T6	7		T7	8		T8	3
valid_sources[0x12]	29104	1			T5	3		T6	5		T7	4
valid_sources[0x13]	34221	1			T5	1		T6	3		T8	2
valid_sources[0x14]	30032	1			T5	9		T6	4		T8	2
valid_sources[0x15]	33332	1			T6	8		T7	1		T8	10
valid_sources[0x16]	29827	1			T6	4		T7	3		T8	5
valid_sources[0x17]	32280	1			T6	6		T7	4		T8	6
valid_sources[0x18]	29209	1			T4	1		T6	7		T7	4
valid_sources[0x19]	30523	1			T6	5		T7	21		T8	7
valid_sources[0x1a]	30352	1			T6	4		T7	1		T8	4
valid_sources[0x1b]	35286	1			T6	4		T7	4		T8	6
valid_sources[0x1c]	33000	1			T5	14		T6	2		T8	4
valid_sources[0x1d]	32253	1			T6	6		T8	5		T9	13
valid_sources[0x1e]	31045	1			T4	1		T6	7		T8	4
valid_sources[0x1f]	35226	1			T6	7		T7	2		T8	7
valid_sources[0x20]	50972	1			T5	4		T6	5		T8	6
valid_sources[0x21]	32282	1			T5	1		T6	3		T7	1
valid_sources[0x22]	31446	1			T6	1		T7	3		T8	5
valid_sources[0x23]	30868	1			T6	3		T7	1		T8	4
valid_sources[0x24]	32463	1			T5	7		T6	2		T8	6
valid_sources[0x25]	31669	1			T2	7		T6	4		T8	1
valid_sources[0x26]	35526	1			T8	8		T9	18		T11	97
valid_sources[0x27]	30107	1			T5	13		T6	9		T7	5
valid_sources[0x28]	31785	1			T5	19		T6	8		T7	25
valid_sources[0x29]	33781	1			T5	1		T6	3		T8	8
valid_sources[0x2a]	31606	1			T6	7		T8	6		T9	6
valid_sources[0x2b]	30804	1			T6	7		T7	15		T8	6
valid_sources[0x2c]	29213	1			T5	9		T6	6		T7	2
valid_sources[0x2d]	31616	1			T6	7		T8	3		T9	12
valid_sources[0x2e]	29389	1			T6	7		T8	1		T9	8
valid_sources[0x2f]	32745	1			T5	4		T6	4		T8	7
valid_sources[0x30]	37760	1			T5	8		T6	6		T7	3
valid_sources[0x31]	35349	1			T6	3		T8	2		T9	12
valid_sources[0x32]	30068	1			T6	3		T7	9		T8	6
valid_sources[0x33]	31939	1			T6	8		T7	5		T8	7
valid_sources[0x34]	30982	1			T5	6		T6	4		T8	3
valid_sources[0x35]	55413	1			T6	6		T8	2		T9	5
valid_sources[0x36]	28872	1			T6	3		T7	1		T8	3
valid_sources[0x37]	31186	1			T5	1		T6	10		T8	9
valid_sources[0x38]	30617	1			T6	6		T8	3		T9	14
valid_sources[0x39]	31878	1			T6	3		T7	3		T8	4
valid_sources[0x3a]	30979	1			T6	5		T7	2		T8	2
valid_sources[0x3b]	31083	1			T6	7		T8	7		T9	3
valid_sources[0x3c]	29191	1			T6	5		T7	7		T8	7
valid_sources[0x3d]	31433	1			T1	1		T6	6		T7	5
valid_sources[0x3e]	33975	1			T6	6		T7	2		T8	6
valid_sources[0x3f]	30902	1			T5	8		T6	2		T8	8
valid_sources[0x40]	31312	1			T6	5		T8	9		T9	8
valid_sources[0x41]	33845	1			T6	7		T7	2		T8	3
valid_sources[0x42]	32158	1			T5	1		T6	7		T7	1
valid_sources[0x43]	36671	1			T6	7		T8	2		T9	22
valid_sources[0x44]	35916	1			T6	2		T7	1		T8	7
valid_sources[0x45]	32137	1			T6	4		T7	5		T8	10
valid_sources[0x46]	35724	1			T6	4		T7	3		T8	4
valid_sources[0x47]	56944	1			T5	6		T6	3		T7	1
valid_sources[0x48]	32514	1			T4	7		T6	1		T8	5
valid_sources[0x49]	30239	1			T6	6		T8	7		T9	12
valid_sources[0x4a]	35672	1			T2	2		T6	6		T7	2
valid_sources[0x4b]	29966	1			T6	2		T7	2		T8	8
valid_sources[0x4c]	31940	1			T5	3		T6	9		T8	9
valid_sources[0x4d]	31286	1			T6	5		T8	1		T9	1
valid_sources[0x4e]	28897	1			T6	2		T7	5		T8	7
valid_sources[0x4f]	29828	1			T6	4		T7	3		T8	1
valid_sources[0x50]	31571	1			T6	8		T7	4		T8	5
valid_sources[0x51]	29990	1			T5	5		T6	6		T8	1
valid_sources[0x52]	32989	1			T6	3		T7	12		T8	9
valid_sources[0x53]	31215	1			T6	2		T8	5		T9	19
valid_sources[0x54]	31088	1			T6	4		T8	7		T9	11
valid_sources[0x55]	29605	1			T6	4		T8	5		T9	16
valid_sources[0x56]	31531	1			T6	4		T7	4		T8	3
valid_sources[0x57]	36686	1			T5	5		T6	10		T8	5
valid_sources[0x58]	34879	1			T6	1		T8	8		T9	9
valid_sources[0x59]	33219	1			T6	9		T8	1		T9	15
valid_sources[0x5a]	31370	1			T4	3		T6	10		T8	5
valid_sources[0x5b]	37212	1			T6	8		T8	4		T9	18
valid_sources[0x5c]	38213	1			T6	5		T7	1		T8	1
valid_sources[0x5d]	31879	1			T6	4		T7	10		T8	4
valid_sources[0x5e]	32560	1			T6	6		T7	2		T8	8
valid_sources[0x5f]	29666	1			T5	2		T6	2		T8	5
valid_sources[0x60]	33052	1			T5	3		T6	8		T8	6
valid_sources[0x61]	32450	1			T5	8		T6	11		T7	9
valid_sources[0x62]	30068	1			T6	4		T7	13		T8	11
valid_sources[0x63]	30863	1			T6	6		T7	6		T8	10
valid_sources[0x64]	29647	1			T6	4		T8	5		T9	9
valid_sources[0x65]	33677	1			T6	6		T7	2		T8	2
valid_sources[0x66]	31751	1			T6	6		T8	7		T9	12
valid_sources[0x67]	34241	1			T6	3		T8	4		T9	4
valid_sources[0x68]	33067	1			T5	3		T6	5		T7	9
valid_sources[0x69]	33057	1			T6	7		T7	2		T8	4
valid_sources[0x6a]	35666	1			T6	6		T7	3		T8	8
valid_sources[0x6b]	30730	1			T5	1		T6	5		T8	6
valid_sources[0x6c]	29753	1			T6	6		T8	5		T9	11
valid_sources[0x6d]	31071	1			T6	3		T8	1		T9	20
valid_sources[0x6e]	30480	1			T6	6		T8	4		T9	17
valid_sources[0x6f]	30385	1			T5	3		T6	5		T7	3
valid_sources[0x70]	36419	1			T5	1		T6	6		T8	5
valid_sources[0x71]	32768	1			T5	4		T6	5		T8	4
valid_sources[0x72]	34692	1			T6	1		T8	6		T9	20
valid_sources[0x73]	32854	1			T5	4		T6	5		T8	8
valid_sources[0x74]	30167	1			T8	8		T9	1		T13	1
valid_sources[0x75]	29797	1			T6	4		T8	3		T9	17
valid_sources[0x76]	31940	1			T5	13		T6	5		T7	15
valid_sources[0x77]	36125	1			T6	7		T7	15		T8	7
valid_sources[0x78]	31079	1			T6	4		T8	3		T9	14
valid_sources[0x79]	77521	1			T6	13		T8	3		T9	9
valid_sources[0x7a]	31869	1			T6	5		T7	1		T8	7
valid_sources[0x7b]	45787	1			T5	4		T6	4		T7	2
valid_sources[0x7c]	31531	1			T4	4		T6	1		T7	10
valid_sources[0x7d]	30397	1			T2	16		T6	4		T7	43
valid_sources[0x7e]	29105	1			T6	6		T8	10		T9	3
valid_sources[0x7f]	30053	1			T4	1		T5	10		T6	3
valid_sources[0x80]	37538	1			T6	3		T7	3		T8	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1102013

1

T1

1

T2

1

T3

1

values[0x0]

all_enables

biggest_size

1726412

1

T4

9

T5

11

T6

437

values[0x1]

all_enables

biggest_size

1701106

1

T4

8

T5

10

T6

470