Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3892019

1

T2

72

T4

9

T5

372

full_word

4531048

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8422637	1			T1	1		T2	73		T3	1
auto[TlIntgErrCmd]	152	1			T93	10		T112	6		T113	8
auto[TlIntgErrData]	145	1			T93	4		T112	7		T113	5
auto[TlIntgErrBoth]	133	1			T93	6		T112	7		T113	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4616418

1

T1

1

T2

73

T3

1

auto[1]

3806649

1

T4

25

T5

35

T6

909

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3513761	1			T2	72		T4	1		T5	358
auto[TlIntgErrNone]	partial	auto[1]	377857	1			T4	8		T5	14		T6	2
auto[TlIntgErrNone]	full_word	auto[0]	1102465	1			T1	1		T2	1		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	3428554	1			T4	17		T5	21		T6	907
auto[TlIntgErrCmd]	partial	auto[0]	50	1			T93	4		T112	2		T113	4
auto[TlIntgErrCmd]	partial	auto[1]	91	1			T93	6		T112	3		T113	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T198	1		T199	1		T200	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T112	1		T198	1		T199	1
auto[TlIntgErrData]	partial	auto[0]	68	1			T93	3		T112	1		T113	2
auto[TlIntgErrData]	partial	auto[1]	66	1			T93	1		T112	6		T113	2
auto[TlIntgErrData]	full_word	auto[0]	6	1			T199	1		T197	2		T201	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T113	1		T199	1		T202	1
auto[TlIntgErrBoth]	partial	auto[0]	59	1			T93	2		T112	3		T113	3
auto[TlIntgErrBoth]	partial	auto[1]	67	1			T93	3		T112	4		T113	3
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T93	1		T113	1		T127	1
auto[TlIntgErrBoth]	full_word	auto[1]	1	1			T198	1		-	-		-	-