Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	526040200	3080718	0	0
DepthKnown_A	526040200	525908365	0	0
RvalidKnown_A	526040200	525908365	0	0
WreadyKnown_A	526040200	525908365	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526040200	3080718	0	0
T6	21011	1667	0	0
T7	58789	1663	0	0
T8	28351	1664	0	0
T9	57487	1663	0	0
T10	14410	0	0	0
T11	87946	1664	0	0
T12	116251	1663	0	0
T13	1582	0	0	0
T14	102034	3201	0	0
T16	0	832	0	0
T17	0	832	0	0
T18	0	1663	0	0
T23	1282	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526040200	525908365	0	0
T1	9228	6823	0	0
T2	1365	1299	0	0
T3	1315	1219	0	0
T4	2369	2273	0	0
T5	9234	9153	0	0
T6	21011	20950	0	0
T7	58789	58692	0	0
T8	28351	28296	0	0
T9	57487	57394	0	0
T10	14410	12837	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526040200	525908365	0	0
T1	9228	6823	0	0
T2	1365	1299	0	0
T3	1315	1219	0	0
T4	2369	2273	0	0
T5	9234	9153	0	0
T6	21011	20950	0	0
T7	58789	58692	0	0
T8	28351	28296	0	0
T9	57487	57394	0	0
T10	14410	12837	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526040200	525908365	0	0
T1	9228	6823	0	0
T2	1365	1299	0	0
T3	1315	1219	0	0
T4	2369	2273	0	0
T5	9234	9153	0	0
T6	21011	20950	0	0
T7	58789	58692	0	0
T8	28351	28296	0	0
T9	57487	57394	0	0
T10	14410	12837	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	526040200	3358277	0	0
DepthKnown_A	526040200	525908365	0	0
RvalidKnown_A	526040200	525908365	0	0
WreadyKnown_A	526040200	525908365	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526040200	3358277	0	0
T6	21011	836	0	0
T7	58789	832	0	0
T8	28351	833	0	0
T9	57487	832	0	0
T10	14410	0	0	0
T11	87946	833	0	0
T12	116251	832	0	0
T13	1582	0	0	0
T14	102034	1605	0	0
T16	0	2624	0	0
T17	0	3749	0	0
T18	0	832	0	0
T23	1282	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526040200	525908365	0	0
T1	9228	6823	0	0
T2	1365	1299	0	0
T3	1315	1219	0	0
T4	2369	2273	0	0
T5	9234	9153	0	0
T6	21011	20950	0	0
T7	58789	58692	0	0
T8	28351	28296	0	0
T9	57487	57394	0	0
T10	14410	12837	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526040200	525908365	0	0
T1	9228	6823	0	0
T2	1365	1299	0	0
T3	1315	1219	0	0
T4	2369	2273	0	0
T5	9234	9153	0	0
T6	21011	20950	0	0
T7	58789	58692	0	0
T8	28351	28296	0	0
T9	57487	57394	0	0
T10	14410	12837	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526040200	525908365	0	0
T1	9228	6823	0	0
T2	1365	1299	0	0
T3	1315	1219	0	0
T4	2369	2273	0	0
T5	9234	9153	0	0
T6	21011	20950	0	0
T7	58789	58692	0	0
T8	28351	28296	0	0
T9	57487	57394	0	0
T10	14410	12837	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	526040200	207029	0	0
DepthKnown_A	526040200	525908365	0	0
RvalidKnown_A	526040200	525908365	0	0
WreadyKnown_A	526040200	525908365	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526040200	207029	0	0
T5	9234	9	0	0
T6	21011	0	0	0
T7	58789	0	0	0
T8	28351	0	0	0
T9	57487	0	0	0
T10	14410	0	0	0
T11	87946	0	0	0
T12	116251	128	0	0
T13	1582	0	0	0
T15	0	471	0	0
T23	1282	0	0	0
T25	0	33	0	0
T27	0	343	0	0
T30	0	20	0	0
T37	0	324	0	0
T38	0	256	0	0
T39	0	957	0	0
T40	0	550	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526040200	525908365	0	0
T1	9228	6823	0	0
T2	1365	1299	0	0
T3	1315	1219	0	0
T4	2369	2273	0	0
T5	9234	9153	0	0
T6	21011	20950	0	0
T7	58789	58692	0	0
T8	28351	28296	0	0
T9	57487	57394	0	0
T10	14410	12837	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526040200	525908365	0	0
T1	9228	6823	0	0
T2	1365	1299	0	0
T3	1315	1219	0	0
T4	2369	2273	0	0
T5	9234	9153	0	0
T6	21011	20950	0	0
T7	58789	58692	0	0
T8	28351	28296	0	0
T9	57487	57394	0	0
T10	14410	12837	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526040200	525908365	0	0
T1	9228	6823	0	0
T2	1365	1299	0	0
T3	1315	1219	0	0
T4	2369	2273	0	0
T5	9234	9153	0	0
T6	21011	20950	0	0
T7	58789	58692	0	0
T8	28351	28296	0	0
T9	57487	57394	0	0
T10	14410	12837	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	526040200	491387	0	0
DepthKnown_A	526040200	525908365	0	0
RvalidKnown_A	526040200	525908365	0	0
WreadyKnown_A	526040200	525908365	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526040200	491387	0	0
T5	9234	9	0	0
T6	21011	0	0	0
T7	58789	0	0	0
T8	28351	0	0	0
T9	57487	0	0	0
T10	14410	0	0	0
T11	87946	0	0	0
T12	116251	128	0	0
T13	1582	0	0	0
T15	0	2179	0	0
T23	1282	0	0	0
T25	0	33	0	0
T27	0	343	0	0
T30	0	107	0	0
T37	0	324	0	0
T38	0	1099	0	0
T39	0	2874	0	0
T40	0	550	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526040200	525908365	0	0
T1	9228	6823	0	0
T2	1365	1299	0	0
T3	1315	1219	0	0
T4	2369	2273	0	0
T5	9234	9153	0	0
T6	21011	20950	0	0
T7	58789	58692	0	0
T8	28351	28296	0	0
T9	57487	57394	0	0
T10	14410	12837	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526040200	525908365	0	0
T1	9228	6823	0	0
T2	1365	1299	0	0
T3	1315	1219	0	0
T4	2369	2273	0	0
T5	9234	9153	0	0
T6	21011	20950	0	0
T7	58789	58692	0	0
T8	28351	28296	0	0
T9	57487	57394	0	0
T10	14410	12837	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526040200	525908365	0	0
T1	9228	6823	0	0
T2	1365	1299	0	0
T3	1315	1219	0	0
T4	2369	2273	0	0
T5	9234	9153	0	0
T6	21011	20950	0	0
T7	58789	58692	0	0
T8	28351	28296	0	0
T9	57487	57394	0	0
T10	14410	12837	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	526040200	6655878	0	0
DepthKnown_A	526040200	525908365	0	0
RvalidKnown_A	526040200	525908365	0	0
WreadyKnown_A	526040200	525908365	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526040200	6655878	0	0
T1	9228	1	0	0
T2	1365	73	0	0
T3	1315	1	0	0
T4	2369	26	0	0
T5	9234	398	0	0
T6	21011	405	0	0
T7	58789	53	0	0
T8	28351	542	0	0
T9	57487	1957	0	0
T10	14410	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526040200	525908365	0	0
T1	9228	6823	0	0
T2	1365	1299	0	0
T3	1315	1219	0	0
T4	2369	2273	0	0
T5	9234	9153	0	0
T6	21011	20950	0	0
T7	58789	58692	0	0
T8	28351	28296	0	0
T9	57487	57394	0	0
T10	14410	12837	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526040200	525908365	0	0
T1	9228	6823	0	0
T2	1365	1299	0	0
T3	1315	1219	0	0
T4	2369	2273	0	0
T5	9234	9153	0	0
T6	21011	20950	0	0
T7	58789	58692	0	0
T8	28351	28296	0	0
T9	57487	57394	0	0
T10	14410	12837	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526040200	525908365	0	0
T1	9228	6823	0	0
T2	1365	1299	0	0
T3	1315	1219	0	0
T4	2369	2273	0	0
T5	9234	9153	0	0
T6	21011	20950	0	0
T7	58789	58692	0	0
T8	28351	28296	0	0
T9	57487	57394	0	0
T10	14410	12837	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	526040200	13969365	0	0
DepthKnown_A	526040200	525908365	0	0
RvalidKnown_A	526040200	525908365	0	0
WreadyKnown_A	526040200	525908365	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526040200	13969365	0	0
T1	9228	4	0	0
T2	1365	182	0	0
T3	1315	1	0	0
T4	2369	26	0	0
T5	9234	398	0	0
T6	21011	1826	0	0
T7	58789	124	0	0
T8	28351	2283	0	0
T9	57487	5827	0	0
T10	14410	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526040200	525908365	0	0
T1	9228	6823	0	0
T2	1365	1299	0	0
T3	1315	1219	0	0
T4	2369	2273	0	0
T5	9234	9153	0	0
T6	21011	20950	0	0
T7	58789	58692	0	0
T8	28351	28296	0	0
T9	57487	57394	0	0
T10	14410	12837	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526040200	525908365	0	0
T1	9228	6823	0	0
T2	1365	1299	0	0
T3	1315	1219	0	0
T4	2369	2273	0	0
T5	9234	9153	0	0
T6	21011	20950	0	0
T7	58789	58692	0	0
T8	28351	28296	0	0
T9	57487	57394	0	0
T10	14410	12837	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	526040200	525908365	0	0
T1	9228	6823	0	0
T2	1365	1299	0	0
T3	1315	1219	0	0
T4	2369	2273	0	0
T5	9234	9153	0	0
T6	21011	20950	0	0
T7	58789	58692	0	0
T8	28351	28296	0	0
T9	57487	57394	0	0
T10	14410	12837	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0