Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
3446 |
0 |
0 |
T92 |
7749 |
225 |
0 |
0 |
T93 |
19695 |
2 |
0 |
0 |
T94 |
14521 |
5 |
0 |
0 |
T110 |
6624 |
210 |
0 |
0 |
T111 |
6989 |
176 |
0 |
0 |
T112 |
53531 |
2 |
0 |
0 |
T113 |
19461 |
2 |
0 |
0 |
T120 |
3738 |
62 |
0 |
0 |
T124 |
10382 |
2 |
0 |
0 |
T130 |
5520 |
1 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
1593 |
0 |
0 |
T94 |
14521 |
7 |
0 |
0 |
T99 |
2088 |
3 |
0 |
0 |
T100 |
3024 |
1 |
0 |
0 |
T124 |
10382 |
10 |
0 |
0 |
T127 |
68361 |
83 |
0 |
0 |
T130 |
5520 |
1 |
0 |
0 |
T165 |
6603 |
25 |
0 |
0 |
T166 |
8285 |
9 |
0 |
0 |
T167 |
102092 |
396 |
0 |
0 |
T168 |
76866 |
518 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
1776 |
0 |
0 |
T94 |
14521 |
14 |
0 |
0 |
T99 |
2088 |
3 |
0 |
0 |
T124 |
10382 |
20 |
0 |
0 |
T127 |
68361 |
88 |
0 |
0 |
T165 |
6603 |
20 |
0 |
0 |
T166 |
8285 |
14 |
0 |
0 |
T167 |
102092 |
446 |
0 |
0 |
T168 |
76866 |
525 |
0 |
0 |
T169 |
6897 |
8 |
0 |
0 |
T170 |
13746 |
24 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
2102 |
0 |
0 |
T94 |
14521 |
32 |
0 |
0 |
T100 |
3024 |
6 |
0 |
0 |
T121 |
14937 |
5 |
0 |
0 |
T124 |
10382 |
13 |
0 |
0 |
T127 |
68361 |
96 |
0 |
0 |
T130 |
5520 |
9 |
0 |
0 |
T165 |
6603 |
20 |
0 |
0 |
T166 |
8285 |
24 |
0 |
0 |
T167 |
102092 |
453 |
0 |
0 |
T168 |
76866 |
423 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
10377 |
0 |
0 |
T94 |
14521 |
176 |
0 |
0 |
T100 |
3024 |
12 |
0 |
0 |
T124 |
10382 |
13 |
0 |
0 |
T127 |
68361 |
1558 |
0 |
0 |
T130 |
5520 |
65 |
0 |
0 |
T165 |
6603 |
6 |
0 |
0 |
T166 |
8285 |
140 |
0 |
0 |
T167 |
102092 |
428 |
0 |
0 |
T168 |
76866 |
476 |
0 |
0 |
T171 |
4230 |
71 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
10575 |
0 |
0 |
T94 |
14521 |
61 |
0 |
0 |
T100 |
3024 |
3 |
0 |
0 |
T124 |
10382 |
255 |
0 |
0 |
T127 |
68361 |
2049 |
0 |
0 |
T130 |
5520 |
72 |
0 |
0 |
T165 |
6603 |
19 |
0 |
0 |
T166 |
8285 |
10 |
0 |
0 |
T167 |
102092 |
374 |
0 |
0 |
T168 |
76866 |
487 |
0 |
0 |
T169 |
6897 |
14 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
9786 |
0 |
0 |
T94 |
14521 |
152 |
0 |
0 |
T100 |
3024 |
4 |
0 |
0 |
T124 |
10382 |
123 |
0 |
0 |
T127 |
68361 |
1070 |
0 |
0 |
T165 |
6603 |
14 |
0 |
0 |
T166 |
8285 |
115 |
0 |
0 |
T167 |
102092 |
486 |
0 |
0 |
T168 |
76866 |
462 |
0 |
0 |
T169 |
6897 |
231 |
0 |
0 |
T171 |
4230 |
60 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
9823 |
0 |
0 |
T94 |
14521 |
130 |
0 |
0 |
T100 |
3024 |
3 |
0 |
0 |
T121 |
14937 |
1 |
0 |
0 |
T124 |
10382 |
123 |
0 |
0 |
T127 |
68361 |
1331 |
0 |
0 |
T130 |
5520 |
11 |
0 |
0 |
T165 |
6603 |
35 |
0 |
0 |
T166 |
8285 |
10 |
0 |
0 |
T167 |
102092 |
410 |
0 |
0 |
T168 |
76866 |
508 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
9620 |
0 |
0 |
T94 |
14521 |
170 |
0 |
0 |
T99 |
2088 |
5 |
0 |
0 |
T100 |
3024 |
6 |
0 |
0 |
T124 |
10382 |
145 |
0 |
0 |
T127 |
68361 |
1509 |
0 |
0 |
T130 |
5520 |
89 |
0 |
0 |
T165 |
6603 |
8 |
0 |
0 |
T166 |
8285 |
136 |
0 |
0 |
T167 |
102092 |
408 |
0 |
0 |
T168 |
76866 |
496 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
8173 |
0 |
0 |
T94 |
14521 |
86 |
0 |
0 |
T100 |
3024 |
17 |
0 |
0 |
T124 |
10382 |
124 |
0 |
0 |
T127 |
68361 |
1067 |
0 |
0 |
T130 |
5520 |
77 |
0 |
0 |
T165 |
6603 |
2 |
0 |
0 |
T166 |
8285 |
150 |
0 |
0 |
T167 |
102092 |
413 |
0 |
0 |
T168 |
76866 |
508 |
0 |
0 |
T169 |
6897 |
9 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
9632 |
0 |
0 |
T94 |
14521 |
85 |
0 |
0 |
T124 |
10382 |
3 |
0 |
0 |
T127 |
68361 |
1499 |
0 |
0 |
T130 |
5520 |
41 |
0 |
0 |
T166 |
8285 |
230 |
0 |
0 |
T167 |
102092 |
389 |
0 |
0 |
T168 |
76866 |
508 |
0 |
0 |
T169 |
6897 |
223 |
0 |
0 |
T170 |
13746 |
22 |
0 |
0 |
T171 |
4230 |
68 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
8830 |
0 |
0 |
T94 |
14521 |
67 |
0 |
0 |
T99 |
2088 |
4 |
0 |
0 |
T100 |
3024 |
8 |
0 |
0 |
T124 |
10382 |
122 |
0 |
0 |
T127 |
68361 |
723 |
0 |
0 |
T130 |
5520 |
99 |
0 |
0 |
T165 |
6603 |
10 |
0 |
0 |
T166 |
8285 |
233 |
0 |
0 |
T167 |
102092 |
367 |
0 |
0 |
T168 |
76866 |
495 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
4339 |
0 |
0 |
T94 |
14521 |
72 |
0 |
0 |
T100 |
3024 |
4 |
0 |
0 |
T124 |
10382 |
22 |
0 |
0 |
T127 |
68361 |
500 |
0 |
0 |
T165 |
6603 |
8 |
0 |
0 |
T166 |
8285 |
106 |
0 |
0 |
T167 |
102092 |
422 |
0 |
0 |
T168 |
76866 |
415 |
0 |
0 |
T169 |
6897 |
49 |
0 |
0 |
T170 |
13746 |
35 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
4616 |
0 |
0 |
T94 |
14521 |
40 |
0 |
0 |
T100 |
3024 |
6 |
0 |
0 |
T124 |
10382 |
72 |
0 |
0 |
T127 |
68361 |
468 |
0 |
0 |
T130 |
5520 |
30 |
0 |
0 |
T166 |
8285 |
50 |
0 |
0 |
T167 |
102092 |
371 |
0 |
0 |
T168 |
76866 |
425 |
0 |
0 |
T169 |
6897 |
115 |
0 |
0 |
T171 |
4230 |
49 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
5021 |
0 |
0 |
T94 |
14521 |
73 |
0 |
0 |
T100 |
3024 |
3 |
0 |
0 |
T124 |
10382 |
36 |
0 |
0 |
T127 |
68361 |
551 |
0 |
0 |
T130 |
5520 |
32 |
0 |
0 |
T165 |
6603 |
24 |
0 |
0 |
T166 |
8285 |
108 |
0 |
0 |
T167 |
102092 |
393 |
0 |
0 |
T168 |
76866 |
497 |
0 |
0 |
T169 |
6897 |
70 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
4712 |
0 |
0 |
T94 |
14521 |
44 |
0 |
0 |
T99 |
2088 |
4 |
0 |
0 |
T100 |
3024 |
10 |
0 |
0 |
T121 |
14937 |
3 |
0 |
0 |
T124 |
10382 |
51 |
0 |
0 |
T127 |
68361 |
539 |
0 |
0 |
T130 |
5520 |
37 |
0 |
0 |
T165 |
6603 |
30 |
0 |
0 |
T166 |
8285 |
123 |
0 |
0 |
T167 |
102092 |
428 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
4625 |
0 |
0 |
T94 |
14521 |
17 |
0 |
0 |
T99 |
2088 |
1 |
0 |
0 |
T100 |
3024 |
1 |
0 |
0 |
T124 |
10382 |
15 |
0 |
0 |
T125 |
6915 |
4 |
0 |
0 |
T127 |
68361 |
605 |
0 |
0 |
T165 |
6603 |
7 |
0 |
0 |
T166 |
8285 |
72 |
0 |
0 |
T167 |
102092 |
373 |
0 |
0 |
T168 |
76866 |
459 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
4990 |
0 |
0 |
T94 |
14521 |
41 |
0 |
0 |
T100 |
3024 |
3 |
0 |
0 |
T124 |
10382 |
102 |
0 |
0 |
T127 |
68361 |
714 |
0 |
0 |
T165 |
6603 |
23 |
0 |
0 |
T166 |
8285 |
9 |
0 |
0 |
T167 |
102092 |
449 |
0 |
0 |
T168 |
76866 |
513 |
0 |
0 |
T169 |
6897 |
7 |
0 |
0 |
T171 |
4230 |
30 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
3718 |
0 |
0 |
T94 |
14521 |
107 |
0 |
0 |
T100 |
3024 |
5 |
0 |
0 |
T124 |
10382 |
55 |
0 |
0 |
T127 |
68361 |
374 |
0 |
0 |
T130 |
5520 |
10 |
0 |
0 |
T165 |
6603 |
9 |
0 |
0 |
T166 |
8285 |
13 |
0 |
0 |
T167 |
102092 |
355 |
0 |
0 |
T168 |
76866 |
499 |
0 |
0 |
T169 |
6897 |
17 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
4498 |
0 |
0 |
T94 |
14521 |
32 |
0 |
0 |
T100 |
3024 |
1 |
0 |
0 |
T124 |
10382 |
62 |
0 |
0 |
T127 |
68361 |
682 |
0 |
0 |
T130 |
5520 |
6 |
0 |
0 |
T165 |
6603 |
20 |
0 |
0 |
T166 |
8285 |
102 |
0 |
0 |
T167 |
102092 |
406 |
0 |
0 |
T168 |
76866 |
513 |
0 |
0 |
T171 |
4230 |
21 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
4053 |
0 |
0 |
T94 |
14521 |
24 |
0 |
0 |
T100 |
3024 |
1 |
0 |
0 |
T124 |
10382 |
17 |
0 |
0 |
T127 |
68361 |
489 |
0 |
0 |
T130 |
5520 |
12 |
0 |
0 |
T165 |
6603 |
33 |
0 |
0 |
T166 |
8285 |
121 |
0 |
0 |
T167 |
102092 |
387 |
0 |
0 |
T168 |
76866 |
470 |
0 |
0 |
T169 |
6897 |
60 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
5186 |
0 |
0 |
T94 |
14521 |
109 |
0 |
0 |
T99 |
2088 |
2 |
0 |
0 |
T100 |
3024 |
7 |
0 |
0 |
T124 |
10382 |
71 |
0 |
0 |
T127 |
68361 |
530 |
0 |
0 |
T130 |
5520 |
17 |
0 |
0 |
T165 |
6603 |
2 |
0 |
0 |
T166 |
8285 |
10 |
0 |
0 |
T167 |
102092 |
438 |
0 |
0 |
T168 |
76866 |
518 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
4407 |
0 |
0 |
T94 |
14521 |
21 |
0 |
0 |
T99 |
2088 |
1 |
0 |
0 |
T100 |
3024 |
7 |
0 |
0 |
T124 |
10382 |
71 |
0 |
0 |
T127 |
68361 |
467 |
0 |
0 |
T165 |
6603 |
8 |
0 |
0 |
T166 |
8285 |
60 |
0 |
0 |
T167 |
102092 |
347 |
0 |
0 |
T168 |
76866 |
465 |
0 |
0 |
T171 |
4230 |
45 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
4520 |
0 |
0 |
T94 |
14521 |
60 |
0 |
0 |
T99 |
2088 |
3 |
0 |
0 |
T100 |
3024 |
8 |
0 |
0 |
T124 |
10382 |
16 |
0 |
0 |
T127 |
68361 |
574 |
0 |
0 |
T130 |
5520 |
8 |
0 |
0 |
T165 |
6603 |
5 |
0 |
0 |
T166 |
8285 |
9 |
0 |
0 |
T167 |
102092 |
425 |
0 |
0 |
T168 |
76866 |
453 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
3850 |
0 |
0 |
T94 |
14521 |
26 |
0 |
0 |
T99 |
2088 |
4 |
0 |
0 |
T100 |
3024 |
17 |
0 |
0 |
T124 |
10382 |
11 |
0 |
0 |
T127 |
68361 |
471 |
0 |
0 |
T130 |
5520 |
6 |
0 |
0 |
T165 |
6603 |
8 |
0 |
0 |
T166 |
8285 |
100 |
0 |
0 |
T167 |
102092 |
349 |
0 |
0 |
T168 |
76866 |
490 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
4230 |
0 |
0 |
T94 |
14521 |
22 |
0 |
0 |
T100 |
3024 |
1 |
0 |
0 |
T124 |
10382 |
64 |
0 |
0 |
T127 |
68361 |
445 |
0 |
0 |
T130 |
5520 |
1 |
0 |
0 |
T165 |
6603 |
10 |
0 |
0 |
T166 |
8285 |
39 |
0 |
0 |
T167 |
102092 |
483 |
0 |
0 |
T168 |
76866 |
506 |
0 |
0 |
T171 |
4230 |
5 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
3959 |
0 |
0 |
T94 |
14521 |
34 |
0 |
0 |
T124 |
10382 |
48 |
0 |
0 |
T127 |
68361 |
392 |
0 |
0 |
T166 |
8285 |
48 |
0 |
0 |
T167 |
102092 |
331 |
0 |
0 |
T168 |
76866 |
475 |
0 |
0 |
T169 |
6897 |
102 |
0 |
0 |
T170 |
13746 |
56 |
0 |
0 |
T171 |
4230 |
35 |
0 |
0 |
T172 |
9404 |
31 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
4774 |
0 |
0 |
T94 |
14521 |
73 |
0 |
0 |
T100 |
3024 |
1 |
0 |
0 |
T121 |
14937 |
7 |
0 |
0 |
T124 |
10382 |
11 |
0 |
0 |
T127 |
68361 |
496 |
0 |
0 |
T130 |
5520 |
41 |
0 |
0 |
T165 |
6603 |
17 |
0 |
0 |
T166 |
8285 |
50 |
0 |
0 |
T167 |
102092 |
490 |
0 |
0 |
T168 |
76866 |
568 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
4682 |
0 |
0 |
T94 |
14521 |
1 |
0 |
0 |
T124 |
10382 |
54 |
0 |
0 |
T127 |
68361 |
671 |
0 |
0 |
T130 |
5520 |
37 |
0 |
0 |
T165 |
6603 |
8 |
0 |
0 |
T166 |
8285 |
63 |
0 |
0 |
T167 |
102092 |
421 |
0 |
0 |
T168 |
76866 |
499 |
0 |
0 |
T170 |
13746 |
22 |
0 |
0 |
T172 |
9404 |
28 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
4394 |
0 |
0 |
T94 |
14521 |
28 |
0 |
0 |
T99 |
2088 |
4 |
0 |
0 |
T100 |
3024 |
8 |
0 |
0 |
T124 |
10382 |
14 |
0 |
0 |
T127 |
68361 |
550 |
0 |
0 |
T130 |
5520 |
24 |
0 |
0 |
T165 |
6603 |
5 |
0 |
0 |
T166 |
8285 |
58 |
0 |
0 |
T167 |
102092 |
417 |
0 |
0 |
T168 |
76866 |
427 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
4559 |
0 |
0 |
T94 |
14521 |
65 |
0 |
0 |
T99 |
2088 |
8 |
0 |
0 |
T100 |
3024 |
1 |
0 |
0 |
T124 |
10382 |
65 |
0 |
0 |
T127 |
68361 |
763 |
0 |
0 |
T165 |
6603 |
6 |
0 |
0 |
T166 |
8285 |
55 |
0 |
0 |
T167 |
102092 |
414 |
0 |
0 |
T168 |
76866 |
501 |
0 |
0 |
T171 |
4230 |
38 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
4711 |
0 |
0 |
T94 |
14521 |
52 |
0 |
0 |
T99 |
2088 |
8 |
0 |
0 |
T100 |
3024 |
8 |
0 |
0 |
T124 |
10382 |
56 |
0 |
0 |
T127 |
68361 |
530 |
0 |
0 |
T165 |
6603 |
6 |
0 |
0 |
T166 |
8285 |
40 |
0 |
0 |
T167 |
102092 |
463 |
0 |
0 |
T168 |
76866 |
487 |
0 |
0 |
T171 |
4230 |
39 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
4626 |
0 |
0 |
T94 |
14521 |
66 |
0 |
0 |
T124 |
10382 |
61 |
0 |
0 |
T127 |
68361 |
439 |
0 |
0 |
T130 |
5520 |
37 |
0 |
0 |
T165 |
6603 |
4 |
0 |
0 |
T166 |
8285 |
117 |
0 |
0 |
T167 |
102092 |
408 |
0 |
0 |
T168 |
76866 |
497 |
0 |
0 |
T169 |
6897 |
11 |
0 |
0 |
T171 |
4230 |
39 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
4329 |
0 |
0 |
T94 |
14521 |
32 |
0 |
0 |
T100 |
3024 |
2 |
0 |
0 |
T124 |
10382 |
42 |
0 |
0 |
T127 |
68361 |
529 |
0 |
0 |
T130 |
5520 |
30 |
0 |
0 |
T165 |
6603 |
8 |
0 |
0 |
T166 |
8285 |
3 |
0 |
0 |
T167 |
102092 |
431 |
0 |
0 |
T168 |
76866 |
477 |
0 |
0 |
T171 |
4230 |
8 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
4258 |
0 |
0 |
T94 |
14521 |
47 |
0 |
0 |
T99 |
2088 |
7 |
0 |
0 |
T100 |
3024 |
6 |
0 |
0 |
T124 |
10382 |
82 |
0 |
0 |
T127 |
68361 |
401 |
0 |
0 |
T130 |
5520 |
45 |
0 |
0 |
T165 |
6603 |
7 |
0 |
0 |
T166 |
8285 |
8 |
0 |
0 |
T167 |
102092 |
387 |
0 |
0 |
T168 |
76866 |
479 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
4471 |
0 |
0 |
T94 |
14521 |
51 |
0 |
0 |
T99 |
2088 |
5 |
0 |
0 |
T100 |
3024 |
4 |
0 |
0 |
T124 |
10382 |
83 |
0 |
0 |
T127 |
68361 |
594 |
0 |
0 |
T130 |
5520 |
27 |
0 |
0 |
T165 |
6603 |
12 |
0 |
0 |
T166 |
8285 |
6 |
0 |
0 |
T167 |
102092 |
382 |
0 |
0 |
T168 |
76866 |
503 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
1892 |
0 |
0 |
T94 |
14521 |
8 |
0 |
0 |
T100 |
3024 |
7 |
0 |
0 |
T124 |
10382 |
17 |
0 |
0 |
T127 |
68361 |
86 |
0 |
0 |
T130 |
5520 |
9 |
0 |
0 |
T165 |
6603 |
7 |
0 |
0 |
T166 |
8285 |
14 |
0 |
0 |
T167 |
102092 |
451 |
0 |
0 |
T168 |
76866 |
476 |
0 |
0 |
T171 |
4230 |
1 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
1776 |
0 |
0 |
T94 |
14521 |
6 |
0 |
0 |
T124 |
10382 |
12 |
0 |
0 |
T127 |
68361 |
103 |
0 |
0 |
T130 |
5520 |
6 |
0 |
0 |
T166 |
8285 |
1 |
0 |
0 |
T167 |
102092 |
411 |
0 |
0 |
T168 |
76866 |
481 |
0 |
0 |
T169 |
6897 |
14 |
0 |
0 |
T170 |
13746 |
18 |
0 |
0 |
T171 |
4230 |
2 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
2022 |
0 |
0 |
T94 |
14521 |
10 |
0 |
0 |
T100 |
3024 |
3 |
0 |
0 |
T124 |
10382 |
29 |
0 |
0 |
T127 |
68361 |
120 |
0 |
0 |
T130 |
5520 |
5 |
0 |
0 |
T165 |
6603 |
10 |
0 |
0 |
T166 |
8285 |
8 |
0 |
0 |
T167 |
102092 |
391 |
0 |
0 |
T168 |
76866 |
510 |
0 |
0 |
T171 |
4230 |
1 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
1945 |
0 |
0 |
T94 |
14521 |
10 |
0 |
0 |
T100 |
3024 |
13 |
0 |
0 |
T124 |
10382 |
23 |
0 |
0 |
T127 |
68361 |
101 |
0 |
0 |
T130 |
5520 |
3 |
0 |
0 |
T165 |
6603 |
12 |
0 |
0 |
T166 |
8285 |
17 |
0 |
0 |
T167 |
102092 |
402 |
0 |
0 |
T168 |
76866 |
441 |
0 |
0 |
T171 |
4230 |
8 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
2605 |
0 |
0 |
T94 |
14521 |
22 |
0 |
0 |
T99 |
2088 |
5 |
0 |
0 |
T124 |
10382 |
44 |
0 |
0 |
T127 |
68361 |
216 |
0 |
0 |
T130 |
5520 |
17 |
0 |
0 |
T165 |
6603 |
8 |
0 |
0 |
T166 |
8285 |
43 |
0 |
0 |
T167 |
102092 |
419 |
0 |
0 |
T168 |
76866 |
478 |
0 |
0 |
T169 |
6897 |
17 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
4316 |
0 |
0 |
T34 |
281272 |
45 |
0 |
0 |
T96 |
0 |
10 |
0 |
0 |
T173 |
0 |
25 |
0 |
0 |
T174 |
0 |
25 |
0 |
0 |
T175 |
0 |
30 |
0 |
0 |
T176 |
0 |
6 |
0 |
0 |
T177 |
0 |
12 |
0 |
0 |
T178 |
0 |
82 |
0 |
0 |
T179 |
0 |
40 |
0 |
0 |
T180 |
0 |
31 |
0 |
0 |
T181 |
1139 |
0 |
0 |
0 |
T182 |
1969 |
0 |
0 |
0 |
T183 |
4213 |
0 |
0 |
0 |
T184 |
7290 |
0 |
0 |
0 |
T185 |
35118 |
0 |
0 |
0 |
T186 |
2635 |
0 |
0 |
0 |
T187 |
7417 |
0 |
0 |
0 |
T188 |
5520 |
0 |
0 |
0 |
T189 |
8615 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
1984 |
0 |
0 |
T94 |
14521 |
16 |
0 |
0 |
T99 |
2088 |
5 |
0 |
0 |
T124 |
10382 |
17 |
0 |
0 |
T127 |
68361 |
125 |
0 |
0 |
T165 |
6603 |
1 |
0 |
0 |
T166 |
8285 |
11 |
0 |
0 |
T167 |
102092 |
412 |
0 |
0 |
T168 |
76866 |
504 |
0 |
0 |
T169 |
6897 |
23 |
0 |
0 |
T171 |
4230 |
8 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
1963 |
0 |
0 |
T94 |
14521 |
27 |
0 |
0 |
T99 |
2088 |
3 |
0 |
0 |
T100 |
3024 |
4 |
0 |
0 |
T121 |
14937 |
3 |
0 |
0 |
T124 |
10382 |
14 |
0 |
0 |
T127 |
68361 |
96 |
0 |
0 |
T130 |
5520 |
3 |
0 |
0 |
T166 |
8285 |
3 |
0 |
0 |
T167 |
102092 |
400 |
0 |
0 |
T168 |
76866 |
542 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
1686 |
0 |
0 |
T94 |
14521 |
7 |
0 |
0 |
T124 |
10382 |
18 |
0 |
0 |
T127 |
68361 |
51 |
0 |
0 |
T130 |
5520 |
5 |
0 |
0 |
T165 |
6603 |
13 |
0 |
0 |
T166 |
8285 |
1 |
0 |
0 |
T167 |
102092 |
427 |
0 |
0 |
T168 |
76866 |
502 |
0 |
0 |
T169 |
6897 |
12 |
0 |
0 |
T171 |
4230 |
5 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
1790 |
0 |
0 |
T94 |
14521 |
26 |
0 |
0 |
T99 |
2088 |
1 |
0 |
0 |
T100 |
3024 |
6 |
0 |
0 |
T124 |
10382 |
12 |
0 |
0 |
T127 |
68361 |
54 |
0 |
0 |
T130 |
5520 |
5 |
0 |
0 |
T166 |
8285 |
10 |
0 |
0 |
T167 |
102092 |
488 |
0 |
0 |
T168 |
76866 |
501 |
0 |
0 |
T171 |
4230 |
4 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
1595 |
0 |
0 |
T94 |
14521 |
13 |
0 |
0 |
T99 |
2088 |
1 |
0 |
0 |
T100 |
3024 |
2 |
0 |
0 |
T124 |
10382 |
16 |
0 |
0 |
T127 |
68361 |
63 |
0 |
0 |
T165 |
6603 |
1 |
0 |
0 |
T166 |
8285 |
7 |
0 |
0 |
T167 |
102092 |
410 |
0 |
0 |
T168 |
76866 |
472 |
0 |
0 |
T169 |
6897 |
9 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
1672 |
0 |
0 |
T94 |
14521 |
19 |
0 |
0 |
T99 |
2088 |
7 |
0 |
0 |
T100 |
3024 |
14 |
0 |
0 |
T124 |
10382 |
18 |
0 |
0 |
T127 |
68361 |
64 |
0 |
0 |
T130 |
5520 |
12 |
0 |
0 |
T165 |
6603 |
27 |
0 |
0 |
T166 |
8285 |
16 |
0 |
0 |
T167 |
102092 |
456 |
0 |
0 |
T168 |
76866 |
412 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
2286 |
0 |
0 |
T94 |
14521 |
9 |
0 |
0 |
T124 |
10382 |
25 |
0 |
0 |
T127 |
68361 |
142 |
0 |
0 |
T130 |
5520 |
7 |
0 |
0 |
T165 |
6603 |
9 |
0 |
0 |
T166 |
8285 |
35 |
0 |
0 |
T167 |
102092 |
412 |
0 |
0 |
T168 |
76866 |
436 |
0 |
0 |
T169 |
6897 |
30 |
0 |
0 |
T170 |
13746 |
71 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
1718 |
0 |
0 |
T94 |
14521 |
11 |
0 |
0 |
T99 |
2088 |
9 |
0 |
0 |
T100 |
3024 |
1 |
0 |
0 |
T124 |
10382 |
20 |
0 |
0 |
T127 |
68361 |
59 |
0 |
0 |
T130 |
5520 |
3 |
0 |
0 |
T165 |
6603 |
20 |
0 |
0 |
T166 |
8285 |
11 |
0 |
0 |
T167 |
102092 |
391 |
0 |
0 |
T168 |
76866 |
465 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
2642 |
0 |
0 |
T94 |
14521 |
21 |
0 |
0 |
T99 |
2088 |
5 |
0 |
0 |
T100 |
3024 |
16 |
0 |
0 |
T124 |
10382 |
54 |
0 |
0 |
T127 |
68361 |
207 |
0 |
0 |
T130 |
5520 |
20 |
0 |
0 |
T165 |
6603 |
11 |
0 |
0 |
T166 |
8285 |
21 |
0 |
0 |
T167 |
102092 |
415 |
0 |
0 |
T168 |
76866 |
488 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
2001 |
0 |
0 |
T94 |
14521 |
24 |
0 |
0 |
T99 |
2088 |
6 |
0 |
0 |
T100 |
3024 |
14 |
0 |
0 |
T124 |
10382 |
18 |
0 |
0 |
T127 |
68361 |
103 |
0 |
0 |
T130 |
5520 |
11 |
0 |
0 |
T165 |
6603 |
20 |
0 |
0 |
T166 |
8285 |
4 |
0 |
0 |
T167 |
102092 |
445 |
0 |
0 |
T168 |
76866 |
484 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
1625 |
0 |
0 |
T94 |
14521 |
5 |
0 |
0 |
T99 |
2088 |
1 |
0 |
0 |
T100 |
3024 |
11 |
0 |
0 |
T124 |
10382 |
18 |
0 |
0 |
T127 |
68361 |
90 |
0 |
0 |
T130 |
5520 |
4 |
0 |
0 |
T165 |
6603 |
21 |
0 |
0 |
T166 |
8285 |
8 |
0 |
0 |
T167 |
102092 |
489 |
0 |
0 |
T168 |
76866 |
410 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
1673 |
0 |
0 |
T94 |
14521 |
9 |
0 |
0 |
T100 |
3024 |
10 |
0 |
0 |
T124 |
10382 |
16 |
0 |
0 |
T127 |
68361 |
61 |
0 |
0 |
T130 |
5520 |
9 |
0 |
0 |
T165 |
6603 |
23 |
0 |
0 |
T166 |
8285 |
1 |
0 |
0 |
T167 |
102092 |
470 |
0 |
0 |
T168 |
76866 |
450 |
0 |
0 |
T169 |
6897 |
3 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
1666 |
0 |
0 |
T94 |
14521 |
7 |
0 |
0 |
T100 |
3024 |
2 |
0 |
0 |
T124 |
10382 |
5 |
0 |
0 |
T127 |
68361 |
90 |
0 |
0 |
T166 |
8285 |
7 |
0 |
0 |
T167 |
102092 |
398 |
0 |
0 |
T168 |
76866 |
539 |
0 |
0 |
T169 |
6897 |
16 |
0 |
0 |
T170 |
13746 |
41 |
0 |
0 |
T172 |
9404 |
13 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
1707 |
0 |
0 |
T94 |
14521 |
25 |
0 |
0 |
T99 |
2088 |
2 |
0 |
0 |
T124 |
10382 |
20 |
0 |
0 |
T127 |
68361 |
86 |
0 |
0 |
T130 |
5520 |
4 |
0 |
0 |
T165 |
6603 |
16 |
0 |
0 |
T166 |
8285 |
12 |
0 |
0 |
T167 |
102092 |
441 |
0 |
0 |
T168 |
76866 |
490 |
0 |
0 |
T171 |
4230 |
6 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
1716 |
0 |
0 |
T94 |
14521 |
16 |
0 |
0 |
T124 |
10382 |
14 |
0 |
0 |
T127 |
68361 |
44 |
0 |
0 |
T130 |
5520 |
3 |
0 |
0 |
T165 |
6603 |
12 |
0 |
0 |
T166 |
8285 |
7 |
0 |
0 |
T167 |
102092 |
443 |
0 |
0 |
T168 |
76866 |
483 |
0 |
0 |
T169 |
6897 |
8 |
0 |
0 |
T171 |
4230 |
4 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526040200 |
1646 |
0 |
0 |
T94 |
14521 |
24 |
0 |
0 |
T100 |
3024 |
1 |
0 |
0 |
T124 |
10382 |
20 |
0 |
0 |
T127 |
68361 |
61 |
0 |
0 |
T130 |
5520 |
6 |
0 |
0 |
T166 |
8285 |
7 |
0 |
0 |
T167 |
102092 |
399 |
0 |
0 |
T168 |
76866 |
508 |
0 |
0 |
T169 |
6897 |
6 |
0 |
0 |
T171 |
4230 |
6 |
0 |
0 |