Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4182956	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4616290

1

T2

1

T3

15

T4

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4912449	1			T1	59		T2	1		T3	53
values[0x0]	1943758	1			T3	8		T4	1		T5	444
values[0x1]	1943039	1			T3	7		T4	12		T5	435

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2955575	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5843671

1

T1

23

T2

1

T3

34

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	37284	1			T8	1		T10	3		T13	10
valid_sources[0x01]	38206	1			T3	4		T10	1		T12	1
valid_sources[0x02]	38642	1			T8	1		T10	2		T13	8
valid_sources[0x03]	32292	1			T7	29		T10	3		T13	5
valid_sources[0x04]	40090	1			T10	2		T13	7		T24	7
valid_sources[0x05]	34537	1			T8	2		T10	13		T13	6
valid_sources[0x06]	32561	1			T1	2		T10	2		T13	8
valid_sources[0x07]	32324	1			T10	2		T13	8		T14	2
valid_sources[0x08]	33998	1			T1	1		T10	3		T13	7
valid_sources[0x09]	31027	1			T10	2		T12	3		T13	10
valid_sources[0x0a]	31278	1			T8	1		T10	1		T12	2
valid_sources[0x0b]	33129	1			T10	5		T13	10		T24	28
valid_sources[0x0c]	38472	1			T3	3		T13	11		T15	7
valid_sources[0x0d]	32340	1			T10	6		T13	9		T24	2
valid_sources[0x0e]	33799	1			T12	1		T13	7		T24	4
valid_sources[0x0f]	31663	1			T7	56		T10	4		T13	9
valid_sources[0x10]	34484	1			T3	4		T9	23		T13	5
valid_sources[0x11]	31903	1			T7	9		T12	1		T13	10
valid_sources[0x12]	32867	1			T10	2		T12	1		T13	7
valid_sources[0x13]	32865	1			T10	6		T13	12		T14	2
valid_sources[0x14]	31638	1			T3	1		T10	3		T12	1
valid_sources[0x15]	34574	1			T8	1		T12	1		T13	8
valid_sources[0x16]	33959	1			T1	1		T10	9		T12	1
valid_sources[0x17]	33552	1			T8	1		T10	7		T13	8
valid_sources[0x18]	32843	1			T10	1		T13	9		T24	6
valid_sources[0x19]	33652	1			T1	1		T10	4		T13	7
valid_sources[0x1a]	36301	1			T7	41		T10	2		T13	6
valid_sources[0x1b]	32276	1			T10	12		T13	5		T14	1
valid_sources[0x1c]	31795	1			T10	5		T13	13		T14	4
valid_sources[0x1d]	65385	1			T8	1		T10	4		T13	10
valid_sources[0x1e]	32427	1			T8	2		T10	2		T13	4
valid_sources[0x1f]	34353	1			T10	8		T11	1		T12	1
valid_sources[0x20]	31063	1			T10	4		T13	10		T14	5
valid_sources[0x21]	36445	1			T10	11		T12	1		T13	8
valid_sources[0x22]	33277	1			T7	27		T10	2		T11	1
valid_sources[0x23]	32488	1			T13	17		T24	1		T14	2
valid_sources[0x24]	32324	1			T10	1		T13	6		T24	5
valid_sources[0x25]	31582	1			T7	14		T13	10		T14	1
valid_sources[0x26]	36127	1			T1	1		T10	2		T12	2
valid_sources[0x27]	33961	1			T10	2		T13	12		T14	2
valid_sources[0x28]	33061	1			T1	3		T7	24		T12	1
valid_sources[0x29]	33832	1			T10	1		T13	6		T24	8
valid_sources[0x2a]	34540	1			T10	4		T13	3		T24	3
valid_sources[0x2b]	34586	1			T7	98		T13	16		T14	5
valid_sources[0x2c]	31816	1			T10	15		T12	1		T13	12
valid_sources[0x2d]	35254	1			T7	40		T8	1		T12	1
valid_sources[0x2e]	34744	1			T10	4		T13	14		T24	3
valid_sources[0x2f]	35048	1			T1	2		T10	2		T13	8
valid_sources[0x30]	32510	1			T1	2		T10	1		T12	2
valid_sources[0x31]	32662	1			T8	1		T10	3		T13	8
valid_sources[0x32]	33757	1			T8	1		T10	7		T13	5
valid_sources[0x33]	33558	1			T7	14		T10	3		T12	1
valid_sources[0x34]	30544	1			T10	5		T12	1		T13	8
valid_sources[0x35]	38055	1			T3	1		T7	45		T10	4
valid_sources[0x36]	33282	1			T13	7		T24	4		T14	3
valid_sources[0x37]	35587	1			T8	1		T10	2		T13	10
valid_sources[0x38]	31623	1			T10	8		T13	9		T24	1
valid_sources[0x39]	33736	1			T13	9		T24	2		T14	5
valid_sources[0x3a]	30143	1			T10	1		T13	6		T24	3
valid_sources[0x3b]	33664	1			T10	3		T12	1		T13	6
valid_sources[0x3c]	36106	1			T8	1		T10	4		T12	6
valid_sources[0x3d]	32394	1			T3	1		T8	1		T10	6
valid_sources[0x3e]	29999	1			T3	2		T12	1		T13	8
valid_sources[0x3f]	30300	1			T10	5		T13	9		T24	22
valid_sources[0x40]	33314	1			T7	39		T8	2		T10	4
valid_sources[0x41]	30843	1			T10	2		T13	12		T24	7
valid_sources[0x42]	32570	1			T1	2		T10	16		T12	1
valid_sources[0x43]	43477	1			T10	1		T13	5		T24	10
valid_sources[0x44]	35985	1			T10	7		T13	8		T24	2
valid_sources[0x45]	31945	1			T8	1		T13	5		T24	8
valid_sources[0x46]	34992	1			T8	1		T13	4		T24	6
valid_sources[0x47]	32058	1			T10	1		T13	8		T24	12
valid_sources[0x48]	42069	1			T8	1		T10	7		T13	5
valid_sources[0x49]	33750	1			T10	3		T12	1		T13	5
valid_sources[0x4a]	30476	1			T10	7		T13	11		T24	1
valid_sources[0x4b]	32227	1			T10	7		T12	2		T13	6
valid_sources[0x4c]	32575	1			T8	1		T10	7		T12	1
valid_sources[0x4d]	31590	1			T13	7		T24	7		T14	3
valid_sources[0x4e]	33348	1			T3	4		T10	3		T13	7
valid_sources[0x4f]	33078	1			T10	4		T13	7		T14	3
valid_sources[0x50]	47081	1			T3	2		T10	1		T13	7
valid_sources[0x51]	36034	1			T12	1		T13	4		T24	5
valid_sources[0x52]	34084	1			T10	1		T13	10		T14	5
valid_sources[0x53]	31879	1			T13	5		T14	3		T15	1
valid_sources[0x54]	30763	1			T10	3		T13	5		T24	2
valid_sources[0x55]	33275	1			T10	3		T13	6		T14	4
valid_sources[0x56]	34996	1			T10	10		T12	1		T13	7
valid_sources[0x57]	33126	1			T10	3		T12	1		T13	11
valid_sources[0x58]	32617	1			T8	1		T10	5		T12	1
valid_sources[0x59]	31292	1			T3	3		T7	2		T10	5
valid_sources[0x5a]	35055	1			T12	1		T13	3		T24	10
valid_sources[0x5b]	29974	1			T8	1		T10	1		T13	10
valid_sources[0x5c]	33438	1			T10	7		T13	7		T24	2
valid_sources[0x5d]	31604	1			T8	1		T13	12		T24	1
valid_sources[0x5e]	32259	1			T10	3		T13	6		T24	1
valid_sources[0x5f]	32307	1			T7	5		T10	4		T13	9
valid_sources[0x60]	34729	1			T8	1		T10	9		T13	10
valid_sources[0x61]	32318	1			T10	2		T13	9		T14	4
valid_sources[0x62]	36296	1			T1	3		T8	1		T10	1
valid_sources[0x63]	32516	1			T10	5		T12	1		T13	6
valid_sources[0x64]	30900	1			T3	1		T10	5		T13	8
valid_sources[0x65]	32123	1			T10	3		T12	1		T13	5
valid_sources[0x66]	33779	1			T7	1		T8	1		T10	4
valid_sources[0x67]	37217	1			T13	11		T14	3		T16	22
valid_sources[0x68]	86326	1			T10	1		T13	9		T24	4
valid_sources[0x69]	33115	1			T8	1		T10	2		T12	1
valid_sources[0x6a]	36304	1			T3	7		T10	9		T13	8
valid_sources[0x6b]	35169	1			T8	1		T10	1		T12	2
valid_sources[0x6c]	31971	1			T8	1		T13	9		T14	11
valid_sources[0x6d]	31281	1			T1	3		T10	1		T12	1
valid_sources[0x6e]	32261	1			T8	1		T10	2		T13	7
valid_sources[0x6f]	30622	1			T1	3		T12	2		T13	8
valid_sources[0x70]	33591	1			T1	2		T3	1		T10	9
valid_sources[0x71]	35590	1			T7	53		T8	1		T10	1
valid_sources[0x72]	33485	1			T10	2		T13	7		T24	5
valid_sources[0x73]	30105	1			T3	1		T10	3		T13	6
valid_sources[0x74]	35014	1			T1	1		T10	9		T13	12
valid_sources[0x75]	34648	1			T10	7		T13	3		T24	8
valid_sources[0x76]	35665	1			T10	2		T13	9		T14	10
valid_sources[0x77]	33571	1			T10	3		T12	1		T13	12
valid_sources[0x78]	30951	1			T1	1		T13	8		T24	2
valid_sources[0x79]	36163	1			T2	1		T3	1		T12	4
valid_sources[0x7a]	33385	1			T7	129		T10	2		T12	1
valid_sources[0x7b]	32908	1			T10	2		T13	10		T24	1
valid_sources[0x7c]	33412	1			T10	5		T13	11		T14	1
valid_sources[0x7d]	33700	1			T1	2		T10	5		T12	1
valid_sources[0x7e]	31153	1			T1	5		T13	11		T24	1
valid_sources[0x7f]	33592	1			T3	3		T10	5		T13	8
valid_sources[0x80]	32174	1			T10	3		T13	7		T14	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1120142

1

T2

1

T3

1

T5

2

values[0x0]

all_enables

biggest_size

1762624

1

T3

8

T5

443

T7

567

values[0x1]

all_enables

biggest_size

1733524

1

T3

6

T4

8

T5

435