Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

4208020

1

T1

59

T3

53

T4

6

full_word

4617824

1

T2

1

T3

15

T4

8

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8825484	1			T1	59		T2	1		T3	68
auto[TlIntgErrCmd]	123	1			T102	2		T116	4		T118	12
auto[TlIntgErrData]	116	1			T102	5		T116	4		T118	11
auto[TlIntgErrBoth]	121	1			T102	3		T116	2		T118	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4917412

1

T1

59

T2

1

T3

53

auto[1]

3908432

1

T3

15

T4

13

T5

879

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3796731	1			T1	59		T3	52		T4	1
auto[TlIntgErrNone]	partial	auto[1]	410951	1			T3	1		T4	5		T5	1
auto[TlIntgErrNone]	full_word	auto[0]	1120521	1			T2	1		T3	1		T5	2
auto[TlIntgErrNone]	full_word	auto[1]	3497281	1			T3	14		T4	8		T5	878
auto[TlIntgErrCmd]	partial	auto[0]	52	1			T116	2		T118	4		T209	5
auto[TlIntgErrCmd]	partial	auto[1]	65	1			T102	2		T116	1		T118	8
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T212	1		T213	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T116	1		T209	2		T214	1
auto[TlIntgErrData]	partial	auto[0]	54	1			T102	1		T118	7		T209	4
auto[TlIntgErrData]	partial	auto[1]	51	1			T102	3		T116	3		T118	4
auto[TlIntgErrData]	full_word	auto[0]	6	1			T116	1		T172	1		T213	2
auto[TlIntgErrData]	full_word	auto[1]	5	1			T102	1		T172	1		T215	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T102	1		T116	2		T118	3
auto[TlIntgErrBoth]	partial	auto[1]	72	1			T102	2		T118	4		T209	7
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T172	1		T212	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T209	1		T210	1		T211	1