Line Coverage for Module :
spid_csb_sync
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 11 | 11 | 100.00 |
| ALWAYS | 32 | 4 | 4 | 100.00 |
| ALWAYS | 44 | 3 | 3 | 100.00 |
| ALWAYS | 63 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 70 | 1 | 1 | 100.00 |
31 always_ff @(posedge sck_i or negedge rst_ni) begin
32 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
33 1/1 sck_toggle <= 1'b0;
Tests: T1 T2 T3
34 end else begin
35 1/1 if (sck_pulse_en_i) begin
Tests: T3 T4 T5
36 1/1 sck_toggle <= ~csb_toggle;
Tests: T3 T4 T5
37 end
MISSING_ELSE
38 end
39 end
40
41 // Signal CSB de-assertion with a change in count, but only do it if the
42 // change originated from the SCK domain.
43 always_ff @(posedge csb_i or negedge rst_ni) begin
44 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
45 1/1 csb_toggle <= 1'b0;
Tests: T1 T2 T3
46 end else begin
47 1/1 csb_toggle <= sck_toggle;
Tests: T1 T5 T7
48 end
49 end
50
51 // clk_i is asynchronous to CSB/SCK, so use a synchronizer.
52 prim_flop_2sync #(
53 .Width (1)
54 ) u_count_sync (
55 .clk_i,
56 .rst_ni,
57 .d_i (csb_toggle),
58 .q_o (sys_toggle)
59 );
60
61 // sys_toggle_last is used to generate the pulse on differences.
62 always_ff @(posedge clk_i or negedge rst_ni) begin
63 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
64 1/1 sys_toggle_last <= 1'b0;
Tests: T1 T2 T3
65 end else begin
66 1/1 sys_toggle_last <= sys_toggle;
Tests: T1 T2 T3
67 end
68 end
69
70 1/1 assign csb_deasserted_pulse_o = (sys_toggle != sys_toggle_last);
Tests: T1 T2 T3
Cond Coverage for Module :
spid_csb_sync
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 70
EXPRESSION (sys_toggle != sys_toggle_last)
---------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T5,T7,T10 |
Branch Coverage for Module :
spid_csb_sync
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| IF |
32 |
3 |
3 |
100.00 |
| IF |
44 |
2 |
2 |
100.00 |
| IF |
63 |
2 |
2 |
100.00 |
32 if (!rst_ni) begin
-1-
33 sck_toggle <= 1'b0;
==>
34 end else begin
35 if (sck_pulse_en_i) begin
-2-
36 sck_toggle <= ~csb_toggle;
==>
37 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T3,T4,T5 |
| 0 |
0 |
Covered |
T3,T4,T5 |
44 if (!rst_ni) begin
-1-
45 csb_toggle <= 1'b0;
==>
46 end else begin
47 csb_toggle <= sck_toggle;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T5,T7 |
63 if (!rst_ni) begin
-1-
64 sys_toggle_last <= 1'b0;
==>
65 end else begin
66 sys_toggle_last <= sys_toggle;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_spid_csb_sync
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 11 | 11 | 100.00 |
| ALWAYS | 32 | 4 | 4 | 100.00 |
| ALWAYS | 44 | 3 | 3 | 100.00 |
| ALWAYS | 63 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 70 | 1 | 1 | 100.00 |
31 always_ff @(posedge sck_i or negedge rst_ni) begin
32 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
33 1/1 sck_toggle <= 1'b0;
Tests: T1 T2 T3
34 end else begin
35 1/1 if (sck_pulse_en_i) begin
Tests: T3 T4 T5
36 1/1 sck_toggle <= ~csb_toggle;
Tests: T3 T4 T5
37 end
==> MISSING_ELSE
38 end
39 end
40
41 // Signal CSB de-assertion with a change in count, but only do it if the
42 // change originated from the SCK domain.
43 always_ff @(posedge csb_i or negedge rst_ni) begin
44 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
45 1/1 csb_toggle <= 1'b0;
Tests: T1 T2 T3
46 end else begin
47 1/1 csb_toggle <= sck_toggle;
Tests: T1 T5 T7
48 end
49 end
50
51 // clk_i is asynchronous to CSB/SCK, so use a synchronizer.
52 prim_flop_2sync #(
53 .Width (1)
54 ) u_count_sync (
55 .clk_i,
56 .rst_ni,
57 .d_i (csb_toggle),
58 .q_o (sys_toggle)
59 );
60
61 // sys_toggle_last is used to generate the pulse on differences.
62 always_ff @(posedge clk_i or negedge rst_ni) begin
63 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
64 1/1 sys_toggle_last <= 1'b0;
Tests: T1 T2 T3
65 end else begin
66 1/1 sys_toggle_last <= sys_toggle;
Tests: T1 T2 T3
67 end
68 end
69
70 1/1 assign csb_deasserted_pulse_o = (sys_toggle != sys_toggle_last);
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_spid_csb_sync
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 70
EXPRESSION (sys_toggle != sys_toggle_last)
---------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T5,T7,T10 |
Branch Coverage for Instance : tb.dut.u_spid_csb_sync
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
6 |
85.71 |
| IF |
32 |
3 |
2 |
66.67 |
| IF |
44 |
2 |
2 |
100.00 |
| IF |
63 |
2 |
2 |
100.00 |
32 if (!rst_ni) begin
-1-
33 sck_toggle <= 1'b0;
==>
34 end else begin
35 if (sck_pulse_en_i) begin
-2-
36 sck_toggle <= ~csb_toggle;
==>
37 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T3,T4,T5 |
| 0 |
0 |
Not Covered |
|
44 if (!rst_ni) begin
-1-
45 csb_toggle <= 1'b0;
==>
46 end else begin
47 csb_toggle <= sck_toggle;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T5,T7 |
63 if (!rst_ni) begin
-1-
64 sys_toggle_last <= 1'b0;
==>
65 end else begin
66 sys_toggle_last <= sys_toggle;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_upload.u_sys_cmdfifo_set
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 11 | 11 | 100.00 |
| ALWAYS | 32 | 4 | 4 | 100.00 |
| ALWAYS | 44 | 3 | 3 | 100.00 |
| ALWAYS | 63 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 70 | 1 | 1 | 100.00 |
31 always_ff @(posedge sck_i or negedge rst_ni) begin
32 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
33 1/1 sck_toggle <= 1'b0;
Tests: T1 T2 T3
34 end else begin
35 1/1 if (sck_pulse_en_i) begin
Tests: T3 T4 T5
36 1/1 sck_toggle <= ~csb_toggle;
Tests: T44 T49 T51
37 end
MISSING_ELSE
38 end
39 end
40
41 // Signal CSB de-assertion with a change in count, but only do it if the
42 // change originated from the SCK domain.
43 always_ff @(posedge csb_i or negedge rst_ni) begin
44 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
45 1/1 csb_toggle <= 1'b0;
Tests: T1 T2 T3
46 end else begin
47 1/1 csb_toggle <= sck_toggle;
Tests: T1 T5 T7
48 end
49 end
50
51 // clk_i is asynchronous to CSB/SCK, so use a synchronizer.
52 prim_flop_2sync #(
53 .Width (1)
54 ) u_count_sync (
55 .clk_i,
56 .rst_ni,
57 .d_i (csb_toggle),
58 .q_o (sys_toggle)
59 );
60
61 // sys_toggle_last is used to generate the pulse on differences.
62 always_ff @(posedge clk_i or negedge rst_ni) begin
63 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
64 1/1 sys_toggle_last <= 1'b0;
Tests: T1 T2 T3
65 end else begin
66 1/1 sys_toggle_last <= sys_toggle;
Tests: T1 T2 T3
67 end
68 end
69
70 1/1 assign csb_deasserted_pulse_o = (sys_toggle != sys_toggle_last);
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_upload.u_sys_cmdfifo_set
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 70
EXPRESSION (sys_toggle != sys_toggle_last)
---------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T44,T49,T51 |
Branch Coverage for Instance : tb.dut.u_upload.u_sys_cmdfifo_set
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| IF |
32 |
3 |
3 |
100.00 |
| IF |
44 |
2 |
2 |
100.00 |
| IF |
63 |
2 |
2 |
100.00 |
32 if (!rst_ni) begin
-1-
33 sck_toggle <= 1'b0;
==>
34 end else begin
35 if (sck_pulse_en_i) begin
-2-
36 sck_toggle <= ~csb_toggle;
==>
37 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T44,T49,T51 |
| 0 |
0 |
Covered |
T3,T4,T5 |
44 if (!rst_ni) begin
-1-
45 csb_toggle <= 1'b0;
==>
46 end else begin
47 csb_toggle <= sck_toggle;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T5,T7 |
63 if (!rst_ni) begin
-1-
64 sys_toggle_last <= 1'b0;
==>
65 end else begin
66 sys_toggle_last <= sys_toggle;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |