Line Coverage for Module :
spid_addr_4b
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 28 | 28 | 100.00 |
| ALWAYS | 53 | 6 | 6 | 100.00 |
| ALWAYS | 63 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| ALWAYS | 112 | 3 | 3 | 100.00 |
| ALWAYS | 124 | 7 | 7 | 100.00 |
| ALWAYS | 139 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 147 | 1 | 1 | 100.00 |
52 always_ff @(posedge sys_clk_i or negedge sys_rst_ni) begin
53 1/1 if (!sys_rst_ni) begin
Tests: T1 T2 T3
54 1/1 sys_fw_new_addr_mode_req <= 1'b0;
Tests: T1 T2 T3
55 1/1 end else if (reg2hw_addr_mode_addr_4b_en_qe_i) begin
Tests: T1 T2 T3
56 1/1 sys_fw_new_addr_mode_req <= 1'b1;
Tests: T5 T7 T10
57 1/1 end else if (sys_fw_new_addr_mode_ack) begin
Tests: T1 T2 T3
58 1/1 sys_fw_new_addr_mode_req <= 1'b0;
Tests: T5 T7 T10
59 end
MISSING_ELSE
60 end
61
62 always_ff @(posedge sys_clk_i or negedge sys_rst_ni) begin
63 1/1 if (!sys_rst_ni) begin
Tests: T1 T2 T3
64 1/1 sys_fw_new_addr_mode_data <= 1'b0;
Tests: T1 T2 T3
65 1/1 end else if (reg2hw_addr_mode_addr_4b_en_qe_i) begin
Tests: T1 T2 T3
66 1/1 sys_fw_new_addr_mode_data <= reg2hw_addr_mode_addr_4b_en_q_i;
Tests: T5 T7 T10
67 end
MISSING_ELSE
68 end
69
70 // SYS-originated address mode changes must only occur while SPI is inactive.
71 // The SPI flash protocol and hardware view would be violated otherwise.
72 // Thus, the data will always be stable by the time the SPI domain picks it up.
73 prim_sync_reqack_data #(
74 .Width (1)
75 ) u_sys2spi_sync (
76 .clk_src_i (sys_clk_i),
77 .rst_src_ni (sys_rst_ni),
78 .clk_dst_i (spi_clk_i),
79 .rst_dst_ni (sys_rst_ni),
80
81 .req_chk_i (1'b1),
82
83 .src_req_i (sys_fw_new_addr_mode_req),
84 .src_ack_o (sys_fw_new_addr_mode_ack),
85 .dst_req_o (spi_fw_new_addr_mode_req),
86 .dst_ack_i (spi_fw_new_addr_mode_ack),
87
88 .data_i (sys_fw_new_addr_mode_data),
89 .data_o (spi_fw_new_addr_mode_data)
90 );
91
92 1/1 assign spi_fw_new_addr_mode_ack = spi_fw_new_addr_mode_req & cmd_sync_pulse_i;
Tests: T1 T2 T3
93 1/1 assign hw2reg_addr_mode_pending_d_o = sys_fw_new_addr_mode_req;
Tests: T1 T2 T3
94
95 ////////////////
96 // SPI -> SYS //
97 ////////////////
98 // The SPI domain is the source of truth, so keep the SYS domain updated
99 // when a firmware change isn't pending.
100 logic sys_cfg_addr_4b_en;
101
102 prim_flop_2sync #(
103 .Width (1)
104 ) u_spi2sys_sync (
105 .clk_i (sys_clk_i),
106 .rst_ni (sys_rst_ni),
107 .d_i (spi_cfg_addr_4b_en_o),
108 .q_o (sys_cfg_addr_4b_en)
109 );
110
111 always_comb begin
112 1/1 if (sys_fw_new_addr_mode_req) begin
Tests: T1 T2 T3
113 1/1 hw2reg_addr_mode_addr_4b_en_d_o = sys_fw_new_addr_mode_data;
Tests: T5 T7 T10
114 end else begin
115 1/1 hw2reg_addr_mode_addr_4b_en_d_o = sys_cfg_addr_4b_en;
Tests: T1 T2 T3
116 end
117 end
118
119 ////////////////
120 // SPI domain //
121 ////////////////
122 logic spi_cfg_addr_4b_en_d, spi_cfg_addr_4b_en_q;
123 always_comb begin
124 1/1 spi_cfg_addr_4b_en_d = spi_cfg_addr_4b_en_q;
Tests: T1 T2 T3
125
126 1/1 if (spi_addr_4b_set_i) begin
Tests: T1 T2 T3
127 // This event occurs when EN4B command is received
128 1/1 spi_cfg_addr_4b_en_d = 1'b 1;
Tests: T64 T44 T48
129 1/1 end else if (spi_addr_4b_clr_i) begin
Tests: T1 T2 T3
130 // EX4B command raises the clear event
131 1/1 spi_cfg_addr_4b_en_d = 1'b 0;
Tests: T17 T44 T95
132 1/1 end else if (spi_fw_new_addr_mode_req) begin
Tests: T1 T2 T3
133 // Update
134 1/1 spi_cfg_addr_4b_en_d = spi_fw_new_addr_mode_data;
Tests: T5 T7 T10
135 end
MISSING_ELSE
136 end
137
138 always_ff @(posedge spi_clk_i or negedge sys_rst_ni) begin
139 1/1 if (!sys_rst_ni) begin
Tests: T1 T2 T3
140 1/1 spi_cfg_addr_4b_en_q <= 1'b 0;
Tests: T1 T2 T3
141 1/1 end else if (cmd_sync_pulse_i) begin
Tests: T3 T4 T5
142 1/1 spi_cfg_addr_4b_en_q <= spi_cfg_addr_4b_en_d;
Tests: T5 T7 T10
143 end
MISSING_ELSE
144 end
145
146 1/1 assign spi_cfg_addr_4b_en_o = spi_cfg_addr_4b_en_q;
Tests: T1 T2 T3
147 1/1 assign cmd_sync_cfg_addr_4b_en_o = spi_cfg_addr_4b_en_d;
Tests: T1 T2 T3
Cond Coverage for Module :
spid_addr_4b
| Total | Covered | Percent |
|---|
| Conditions | 3 | 3 | 100.00 |
| Logical | 3 | 3 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 92
EXPRESSION (spi_fw_new_addr_mode_req & cmd_sync_pulse_i)
------------1----------- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T5,T7,T10 |
| 1 | 0 | Covered | T5,T7,T10 |
| 1 | 1 | Covered | T5,T7,T10 |
Branch Coverage for Module :
spid_addr_4b
| Line No. | Total | Covered | Percent |
| Branches |
|
16 |
16 |
100.00 |
| IF |
53 |
4 |
4 |
100.00 |
| IF |
63 |
3 |
3 |
100.00 |
| IF |
112 |
2 |
2 |
100.00 |
| IF |
126 |
4 |
4 |
100.00 |
| IF |
139 |
3 |
3 |
100.00 |
53 if (!sys_rst_ni) begin
-1-
54 sys_fw_new_addr_mode_req <= 1'b0;
==>
55 end else if (reg2hw_addr_mode_addr_4b_en_qe_i) begin
-2-
56 sys_fw_new_addr_mode_req <= 1'b1;
==>
57 end else if (sys_fw_new_addr_mode_ack) begin
-3-
58 sys_fw_new_addr_mode_req <= 1'b0;
==>
59 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T5,T7,T10 |
| 0 |
0 |
1 |
Covered |
T5,T7,T10 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
63 if (!sys_rst_ni) begin
-1-
64 sys_fw_new_addr_mode_data <= 1'b0;
==>
65 end else if (reg2hw_addr_mode_addr_4b_en_qe_i) begin
-2-
66 sys_fw_new_addr_mode_data <= reg2hw_addr_mode_addr_4b_en_q_i;
==>
67 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T5,T7,T10 |
| 0 |
0 |
Covered |
T1,T2,T3 |
112 if (sys_fw_new_addr_mode_req) begin
-1-
113 hw2reg_addr_mode_addr_4b_en_d_o = sys_fw_new_addr_mode_data;
==>
114 end else begin
115 hw2reg_addr_mode_addr_4b_en_d_o = sys_cfg_addr_4b_en;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T7,T10 |
| 0 |
Covered |
T1,T2,T3 |
126 if (spi_addr_4b_set_i) begin
-1-
127 // This event occurs when EN4B command is received
128 spi_cfg_addr_4b_en_d = 1'b 1;
==>
129 end else if (spi_addr_4b_clr_i) begin
-2-
130 // EX4B command raises the clear event
131 spi_cfg_addr_4b_en_d = 1'b 0;
==>
132 end else if (spi_fw_new_addr_mode_req) begin
-3-
133 // Update
134 spi_cfg_addr_4b_en_d = spi_fw_new_addr_mode_data;
==>
135 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T64,T44,T48 |
| 0 |
1 |
- |
Covered |
T17,T44,T95 |
| 0 |
0 |
1 |
Covered |
T5,T7,T10 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
139 if (!sys_rst_ni) begin
-1-
140 spi_cfg_addr_4b_en_q <= 1'b 0;
==>
141 end else if (cmd_sync_pulse_i) begin
-2-
142 spi_cfg_addr_4b_en_q <= spi_cfg_addr_4b_en_d;
==>
143 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T5,T7,T10 |
| 0 |
0 |
Covered |
T3,T4,T5 |