Assert Coverage for Module :
prim_mubi4_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
956 |
956 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
497019669 |
496931308 |
0 |
0 |
| T1 |
1521 |
1460 |
0 |
0 |
| T2 |
1086 |
1019 |
0 |
0 |
| T3 |
1881 |
1831 |
0 |
0 |
| T4 |
2746 |
2693 |
0 |
0 |
| T5 |
11728 |
11662 |
0 |
0 |
| T6 |
10995 |
8581 |
0 |
0 |
| T7 |
22288 |
22210 |
0 |
0 |
| T8 |
1513 |
1434 |
0 |
0 |
| T9 |
1530 |
1434 |
0 |
0 |
| T10 |
25303 |
25203 |
0 |
0 |
gen_no_flops.OutputDelay_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
497019669 |
496931308 |
0 |
0 |
| T1 |
1521 |
1460 |
0 |
0 |
| T2 |
1086 |
1019 |
0 |
0 |
| T3 |
1881 |
1831 |
0 |
0 |
| T4 |
2746 |
2693 |
0 |
0 |
| T5 |
11728 |
11662 |
0 |
0 |
| T6 |
10995 |
8581 |
0 |
0 |
| T7 |
22288 |
22210 |
0 |
0 |
| T8 |
1513 |
1434 |
0 |
0 |
| T9 |
1530 |
1434 |
0 |
0 |
| T10 |
25303 |
25203 |
0 |
0 |