SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_scanmode_sync | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
92.52 | 95.20 | 84.31 | 97.00 | 90.62 | 95.45 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 956 | 956 | 0 | 0 |
OutputsKnown_A | 497019669 | 496931308 | 0 | 0 |
gen_no_flops.OutputDelay_A | 497019669 | 496931308 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 956 | 956 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 497019669 | 496931308 | 0 | 0 |
T1 | 1521 | 1460 | 0 | 0 |
T2 | 1086 | 1019 | 0 | 0 |
T3 | 1881 | 1831 | 0 | 0 |
T4 | 2746 | 2693 | 0 | 0 |
T5 | 11728 | 11662 | 0 | 0 |
T6 | 10995 | 8581 | 0 | 0 |
T7 | 22288 | 22210 | 0 | 0 |
T8 | 1513 | 1434 | 0 | 0 |
T9 | 1530 | 1434 | 0 | 0 |
T10 | 25303 | 25203 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 497019669 | 496931308 | 0 | 0 |
T1 | 1521 | 1460 | 0 | 0 |
T2 | 1086 | 1019 | 0 | 0 |
T3 | 1881 | 1831 | 0 | 0 |
T4 | 2746 | 2693 | 0 | 0 |
T5 | 11728 | 11662 | 0 | 0 |
T6 | 10995 | 8581 | 0 | 0 |
T7 | 22288 | 22210 | 0 | 0 |
T8 | 1513 | 1434 | 0 | 0 |
T9 | 1530 | 1434 | 0 | 0 |
T10 | 25303 | 25203 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |