Unified Coverage Report :: Module :: prim_generic_ram_1r1w

Module : prim_generic_ram_1r1w

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

44                        logic unused_cfg;
45         1/1            assign unused_cfg = ^cfg_i;
           Tests:       T2 
46                      
47                        // Width of internal write mask. Note *_wmask_i input into the module is always assumed
48                        // to be the full bit mask.
49                        localparam int MaskWidth = Width / DataBitsPerMask;
50                      
51                        logic [Width-1:0]     mem [Depth];
52                        logic [MaskWidth-1:0] a_wmask;
53                        for (genvar k = 0; k < MaskWidth; k++) begin : gen_wmask
54         4/4              assign a_wmask[k] = &a_wmask_i[k*DataBitsPerMask +: DataBitsPerMask];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
55                      
56                          // Ensure that all mask bits within a group have the same value for a write
57                          `ASSERT(MaskCheckPortA_A, a_req_i |->
58                              a_wmask_i[k*DataBitsPerMask +: DataBitsPerMask] inside {{DataBitsPerMask{1'b1}}, '0},
59                              clk_a_i, '0)
60                        end
61                      
62                        // Xilinx FPGA specific Two-port RAM coding style
63                        // using always instead of always_ff to avoid 'ICPD  - illegal combination of drivers' error
64                        // thrown due to 'mem' being driven by two always processes below
65                        always @(posedge clk_a_i) begin
66         1/1              if (a_req_i) begin
           Tests:       T1 T2 T3 
67         1/1                for (int i=0; i < MaskWidth; i = i + 1) begin
           Tests:       T3 T5 T7 
68         1/1                  if (a_wmask[i]) begin
           Tests:       T3 T5 T7 
69         1/1                    mem[a_addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
           Tests:       T3 T5 T7 
70                                  a_wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
71                              end
                        MISSING_ELSE
72                            end
73                          end
                        MISSING_ELSE
74                        end
75                      
76                        always @(posedge clk_b_i) begin
77         1/1              if (b_req_i) begin
           Tests:       T1 T2 T3 
78         1/1                b_rdata_o <= mem[b_addr_i];
           Tests:       T3 T5 T7 
79                          end
                        MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

66             if (a_req_i) begin
               -1-  
67               for (int i=0; i < MaskWidth; i = i + 1) begin
                 ==>
68                 if (a_wmask[i]) begin
69                   mem[a_addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
70                     a_wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
71                 end
72               end
73             end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T7
0	Covered	T1,T2,T3

77             if (b_req_i) begin
               -1-  
78               b_rdata_o <= mem[b_addr_i];
                 ==>
79             end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1r1w

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	652630940	3569276	0	0
gen_wmask[1].MaskCheckPortA_A	652630940	3569276	0	0
gen_wmask[2].MaskCheckPortA_A	652630940	3569276	0	0
gen_wmask[3].MaskCheckPortA_A	652630940	3569276	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652630940	3569276	0	0
T3	1881	12	0	0
T4	2746	0	0	0
T5	11728	832	0	0
T6	10995	0	0	0
T7	22288	1088	0	0
T8	1513	0	0	0
T9	1530	0	0	0
T10	25303	832	0	0
T11	1267	0	0	0
T12	3109	60	0	0
T13	113426	1613	0	0
T14	8224	832	0	0
T15	25075	832	0	0
T16	13747	832	0	0
T17	17605	0	0	0
T18	10729	0	0	0
T19	101809	0	0	0
T24	0	832	0	0
T25	75090	0	0	0
T26	95091	0	0	0
T29	0	45	0	0
T32	0	51	0	0
T43	0	2948	0	0
T44	0	2181	0	0
T45	0	70	0	0
T47	0	3089	0	0
T48	0	1752	0	0
T49	0	7219	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652630940	3569276	0	0
T3	1881	12	0	0
T4	2746	0	0	0
T5	11728	832	0	0
T6	10995	0	0	0
T7	22288	1088	0	0
T8	1513	0	0	0
T9	1530	0	0	0
T10	25303	832	0	0
T11	1267	0	0	0
T12	3109	60	0	0
T13	113426	1613	0	0
T14	8224	832	0	0
T15	25075	832	0	0
T16	13747	832	0	0
T17	17605	0	0	0
T18	10729	0	0	0
T19	101809	0	0	0
T24	0	832	0	0
T25	75090	0	0	0
T26	95091	0	0	0
T29	0	45	0	0
T32	0	51	0	0
T43	0	2948	0	0
T44	0	2181	0	0
T45	0	70	0	0
T47	0	3089	0	0
T48	0	1752	0	0
T49	0	7219	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652630940	3569276	0	0
T3	1881	12	0	0
T4	2746	0	0	0
T5	11728	832	0	0
T6	10995	0	0	0
T7	22288	1088	0	0
T8	1513	0	0	0
T9	1530	0	0	0
T10	25303	832	0	0
T11	1267	0	0	0
T12	3109	60	0	0
T13	113426	1613	0	0
T14	8224	832	0	0
T15	25075	832	0	0
T16	13747	832	0	0
T17	17605	0	0	0
T18	10729	0	0	0
T19	101809	0	0	0
T24	0	832	0	0
T25	75090	0	0	0
T26	95091	0	0	0
T29	0	45	0	0
T32	0	51	0	0
T43	0	2948	0	0
T44	0	2181	0	0
T45	0	70	0	0
T47	0	3089	0	0
T48	0	1752	0	0
T49	0	7219	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652630940	3569276	0	0
T3	1881	12	0	0
T4	2746	0	0	0
T5	11728	832	0	0
T6	10995	0	0	0
T7	22288	1088	0	0
T8	1513	0	0	0
T9	1530	0	0	0
T10	25303	832	0	0
T11	1267	0	0	0
T12	3109	60	0	0
T13	113426	1613	0	0
T14	8224	832	0	0
T15	25075	832	0	0
T16	13747	832	0	0
T17	17605	0	0	0
T18	10729	0	0	0
T19	101809	0	0	0
T24	0	832	0	0
T25	75090	0	0	0
T26	95091	0	0	0
T29	0	45	0	0
T32	0	51	0	0
T43	0	2948	0	0
T44	0	2181	0	0
T45	0	70	0	0
T47	0	3089	0	0
T48	0	1752	0	0
T49	0	7219	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

44                        logic unused_cfg;
45         1/1            assign unused_cfg = ^cfg_i;
           Tests:       T2 
46                      
47                        // Width of internal write mask. Note *_wmask_i input into the module is always assumed
48                        // to be the full bit mask.
49                        localparam int MaskWidth = Width / DataBitsPerMask;
50                      
51                        logic [Width-1:0]     mem [Depth];
52                        logic [MaskWidth-1:0] a_wmask;
53                        for (genvar k = 0; k < MaskWidth; k++) begin : gen_wmask
54         4/4              assign a_wmask[k] = &a_wmask_i[k*DataBitsPerMask +: DataBitsPerMask];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
55                      
56                          // Ensure that all mask bits within a group have the same value for a write
57                          `ASSERT(MaskCheckPortA_A, a_req_i |->
58                              a_wmask_i[k*DataBitsPerMask +: DataBitsPerMask] inside {{DataBitsPerMask{1'b1}}, '0},
59                              clk_a_i, '0)
60                        end
61                      
62                        // Xilinx FPGA specific Two-port RAM coding style
63                        // using always instead of always_ff to avoid 'ICPD  - illegal combination of drivers' error
64                        // thrown due to 'mem' being driven by two always processes below
65                        always @(posedge clk_a_i) begin
66         1/1              if (a_req_i) begin
           Tests:       T1 T2 T3 
67         1/1                for (int i=0; i < MaskWidth; i = i + 1) begin
           Tests:       T3 T5 T7 
68         1/1                  if (a_wmask[i]) begin
           Tests:       T3 T5 T7 
69         1/1                    mem[a_addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
           Tests:       T3 T5 T7 
70                                  a_wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
71                              end
                   ==>  MISSING_ELSE
72                            end
73                          end
                        MISSING_ELSE
74                        end
75                      
76                        always @(posedge clk_b_i) begin
77         1/1              if (b_req_i) begin
           Tests:       T3 T4 T5 
78         1/1                b_rdata_o <= mem[b_addr_i];
           Tests:       T3 T5 T7 
79                          end
                        MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

66             if (a_req_i) begin
               -1-  
67               for (int i=0; i < MaskWidth; i = i + 1) begin
                 ==>
68                 if (a_wmask[i]) begin
69                   mem[a_addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
70                     a_wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
71                 end
72               end
73             end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T7
0	Covered	T1,T2,T3

77             if (b_req_i) begin
               -1-  
78               b_rdata_o <= mem[b_addr_i];
                 ==>
79             end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T7
0	Covered	T3,T4,T5

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	497019669	2191166	0	0
gen_wmask[1].MaskCheckPortA_A	497019669	2191166	0	0
gen_wmask[2].MaskCheckPortA_A	497019669	2191166	0	0
gen_wmask[3].MaskCheckPortA_A	497019669	2191166	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497019669	2191166	0	0
T3	1881	12	0	0
T4	2746	0	0	0
T5	11728	832	0	0
T6	10995	0	0	0
T7	22288	1088	0	0
T8	1513	0	0	0
T9	1530	0	0	0
T10	25303	832	0	0
T11	1267	0	0	0
T12	2243	1	0	0
T13	0	573	0	0
T14	0	832	0	0
T15	0	832	0	0
T16	0	832	0	0
T24	0	832	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497019669	2191166	0	0
T3	1881	12	0	0
T4	2746	0	0	0
T5	11728	832	0	0
T6	10995	0	0	0
T7	22288	1088	0	0
T8	1513	0	0	0
T9	1530	0	0	0
T10	25303	832	0	0
T11	1267	0	0	0
T12	2243	1	0	0
T13	0	573	0	0
T14	0	832	0	0
T15	0	832	0	0
T16	0	832	0	0
T24	0	832	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497019669	2191166	0	0
T3	1881	12	0	0
T4	2746	0	0	0
T5	11728	832	0	0
T6	10995	0	0	0
T7	22288	1088	0	0
T8	1513	0	0	0
T9	1530	0	0	0
T10	25303	832	0	0
T11	1267	0	0	0
T12	2243	1	0	0
T13	0	573	0	0
T14	0	832	0	0
T15	0	832	0	0
T16	0	832	0	0
T24	0	832	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497019669	2191166	0	0
T3	1881	12	0	0
T4	2746	0	0	0
T5	11728	832	0	0
T6	10995	0	0	0
T7	22288	1088	0	0
T8	1513	0	0	0
T9	1530	0	0	0
T10	25303	832	0	0
T11	1267	0	0	0
T12	2243	1	0	0
T13	0	573	0	0
T14	0	832	0	0
T15	0	832	0	0
T16	0	832	0	0
T24	0	832	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

44                        logic unused_cfg;
45         1/1            assign unused_cfg = ^cfg_i;
           Tests:       T2 
46                      
47                        // Width of internal write mask. Note *_wmask_i input into the module is always assumed
48                        // to be the full bit mask.
49                        localparam int MaskWidth = Width / DataBitsPerMask;
50                      
51                        logic [Width-1:0]     mem [Depth];
52                        logic [MaskWidth-1:0] a_wmask;
53                        for (genvar k = 0; k < MaskWidth; k++) begin : gen_wmask
54         4/4              assign a_wmask[k] = &a_wmask_i[k*DataBitsPerMask +: DataBitsPerMask];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
55                      
56                          // Ensure that all mask bits within a group have the same value for a write
57                          `ASSERT(MaskCheckPortA_A, a_req_i |->
58                              a_wmask_i[k*DataBitsPerMask +: DataBitsPerMask] inside {{DataBitsPerMask{1'b1}}, '0},
59                              clk_a_i, '0)
60                        end
61                      
62                        // Xilinx FPGA specific Two-port RAM coding style
63                        // using always instead of always_ff to avoid 'ICPD  - illegal combination of drivers' error
64                        // thrown due to 'mem' being driven by two always processes below
65                        always @(posedge clk_a_i) begin
66         1/1              if (a_req_i) begin
           Tests:       T3 T4 T5 
67         1/1                for (int i=0; i < MaskWidth; i = i + 1) begin
           Tests:       T12 T13 T29 
68         1/1                  if (a_wmask[i]) begin
           Tests:       T12 T13 T29 
69         1/1                    mem[a_addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
           Tests:       T12 T13 T29 
70                                  a_wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
71                              end
                        MISSING_ELSE
72                            end
73                          end
                        MISSING_ELSE
74                        end
75                      
76                        always @(posedge clk_b_i) begin
77         1/1              if (b_req_i) begin
           Tests:       T1 T2 T3 
78         1/1                b_rdata_o <= mem[b_addr_i];
           Tests:       T12 T13 T29 
79                          end
                        MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

66             if (a_req_i) begin
               -1-  
67               for (int i=0; i < MaskWidth; i = i + 1) begin
                 ==>
68                 if (a_wmask[i]) begin
69                   mem[a_addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
70                     a_wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
71                 end
72               end
73             end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T29
0	Covered	T3,T4,T5

77             if (b_req_i) begin
               -1-  
78               b_rdata_o <= mem[b_addr_i];
                 ==>
79             end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T29
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	155611271	1378110	0	0
gen_wmask[1].MaskCheckPortA_A	155611271	1378110	0	0
gen_wmask[2].MaskCheckPortA_A	155611271	1378110	0	0
gen_wmask[3].MaskCheckPortA_A	155611271	1378110	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155611271	1378110	0	0
T12	866	59	0	0
T13	113426	1040	0	0
T14	8224	0	0	0
T15	25075	0	0	0
T16	13747	0	0	0
T17	17605	0	0	0
T18	10729	0	0	0
T19	101809	0	0	0
T25	75090	0	0	0
T26	95091	0	0	0
T29	0	45	0	0
T32	0	51	0	0
T43	0	2948	0	0
T44	0	2181	0	0
T45	0	70	0	0
T47	0	3089	0	0
T48	0	1752	0	0
T49	0	7219	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155611271	1378110	0	0
T12	866	59	0	0
T13	113426	1040	0	0
T14	8224	0	0	0
T15	25075	0	0	0
T16	13747	0	0	0
T17	17605	0	0	0
T18	10729	0	0	0
T19	101809	0	0	0
T25	75090	0	0	0
T26	95091	0	0	0
T29	0	45	0	0
T32	0	51	0	0
T43	0	2948	0	0
T44	0	2181	0	0
T45	0	70	0	0
T47	0	3089	0	0
T48	0	1752	0	0
T49	0	7219	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155611271	1378110	0	0
T12	866	59	0	0
T13	113426	1040	0	0
T14	8224	0	0	0
T15	25075	0	0	0
T16	13747	0	0	0
T17	17605	0	0	0
T18	10729	0	0	0
T19	101809	0	0	0
T25	75090	0	0	0
T26	95091	0	0	0
T29	0	45	0	0
T32	0	51	0	0
T43	0	2948	0	0
T44	0	2181	0	0
T45	0	70	0	0
T47	0	3089	0	0
T48	0	1752	0	0
T49	0	7219	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155611271	1378110	0	0
T12	866	59	0	0
T13	113426	1040	0	0
T14	8224	0	0	0
T15	25075	0	0	0
T16	13747	0	0	0
T17	17605	0	0	0
T18	10729	0	0	0
T19	101809	0	0	0
T25	75090	0	0	0
T26	95091	0	0	0
T29	0	45	0	0
T32	0	51	0	0
T43	0	2948	0	0
T44	0	2181	0	0
T45	0	70	0	0
T47	0	3089	0	0
T48	0	1752	0	0
T49	0	7219	0	0