Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	499330282	3020946	0	0
DepthKnown_A	499330282	499200393	0	0
RvalidKnown_A	499330282	499200393	0	0
WreadyKnown_A	499330282	499200393	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499330282	3020946	0	0
T5	11728	832	0	0
T6	10995	0	0	0
T7	22288	1345	0	0
T8	1513	0	0	0
T9	1530	0	0	0
T10	25303	832	0	0
T11	1267	0	0	0
T12	2243	0	0	0
T13	64768	0	0	0
T14	0	832	0	0
T15	0	832	0	0
T16	0	1663	0	0
T17	0	832	0	0
T18	0	1663	0	0
T19	0	832	0	0
T24	10095	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499330282	499200393	0	0
T1	1521	1460	0	0
T2	1086	1019	0	0
T3	1881	1831	0	0
T4	2746	2693	0	0
T5	11728	11662	0	0
T6	10995	8581	0	0
T7	22288	22210	0	0
T8	1513	1434	0	0
T9	1530	1434	0	0
T10	25303	25203	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499330282	499200393	0	0
T1	1521	1460	0	0
T2	1086	1019	0	0
T3	1881	1831	0	0
T4	2746	2693	0	0
T5	11728	11662	0	0
T6	10995	8581	0	0
T7	22288	22210	0	0
T8	1513	1434	0	0
T9	1530	1434	0	0
T10	25303	25203	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499330282	499200393	0	0
T1	1521	1460	0	0
T2	1086	1019	0	0
T3	1881	1831	0	0
T4	2746	2693	0	0
T5	11728	11662	0	0
T6	10995	8581	0	0
T7	22288	22210	0	0
T8	1513	1434	0	0
T9	1530	1434	0	0
T10	25303	25203	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	499330282	3221246	0	0
DepthKnown_A	499330282	499200393	0	0
RvalidKnown_A	499330282	499200393	0	0
WreadyKnown_A	499330282	499200393	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499330282	3221246	0	0
T5	11728	3760	0	0
T6	10995	0	0	0
T7	22288	2861	0	0
T8	1513	0	0	0
T9	1530	0	0	0
T10	25303	2519	0	0
T11	1267	0	0	0
T12	2243	0	0	0
T13	64768	0	0	0
T14	0	832	0	0
T15	0	832	0	0
T16	0	832	0	0
T17	0	832	0	0
T18	0	832	0	0
T19	0	832	0	0
T24	10095	3657	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499330282	499200393	0	0
T1	1521	1460	0	0
T2	1086	1019	0	0
T3	1881	1831	0	0
T4	2746	2693	0	0
T5	11728	11662	0	0
T6	10995	8581	0	0
T7	22288	22210	0	0
T8	1513	1434	0	0
T9	1530	1434	0	0
T10	25303	25203	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499330282	499200393	0	0
T1	1521	1460	0	0
T2	1086	1019	0	0
T3	1881	1831	0	0
T4	2746	2693	0	0
T5	11728	11662	0	0
T6	10995	8581	0	0
T7	22288	22210	0	0
T8	1513	1434	0	0
T9	1530	1434	0	0
T10	25303	25203	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499330282	499200393	0	0
T1	1521	1460	0	0
T2	1086	1019	0	0
T3	1881	1831	0	0
T4	2746	2693	0	0
T5	11728	11662	0	0
T6	10995	8581	0	0
T7	22288	22210	0	0
T8	1513	1434	0	0
T9	1530	1434	0	0
T10	25303	25203	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	499330282	212620	0	0
DepthKnown_A	499330282	499200393	0	0
RvalidKnown_A	499330282	499200393	0	0
WreadyKnown_A	499330282	499200393	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499330282	212620	0	0
T12	2243	15	0	0
T13	64768	271	0	0
T14	60295	0	0	0
T15	29380	0	0	0
T16	85943	0	0	0
T17	71809	0	0	0
T18	88685	0	0	0
T24	10095	0	0	0
T25	180063	0	0	0
T26	124855	0	0	0
T29	0	12	0	0
T32	0	13	0	0
T43	0	766	0	0
T44	0	416	0	0
T45	0	18	0	0
T47	0	810	0	0
T48	0	454	0	0
T49	0	1407	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499330282	499200393	0	0
T1	1521	1460	0	0
T2	1086	1019	0	0
T3	1881	1831	0	0
T4	2746	2693	0	0
T5	11728	11662	0	0
T6	10995	8581	0	0
T7	22288	22210	0	0
T8	1513	1434	0	0
T9	1530	1434	0	0
T10	25303	25203	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499330282	499200393	0	0
T1	1521	1460	0	0
T2	1086	1019	0	0
T3	1881	1831	0	0
T4	2746	2693	0	0
T5	11728	11662	0	0
T6	10995	8581	0	0
T7	22288	22210	0	0
T8	1513	1434	0	0
T9	1530	1434	0	0
T10	25303	25203	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499330282	499200393	0	0
T1	1521	1460	0	0
T2	1086	1019	0	0
T3	1881	1831	0	0
T4	2746	2693	0	0
T5	11728	11662	0	0
T6	10995	8581	0	0
T7	22288	22210	0	0
T8	1513	1434	0	0
T9	1530	1434	0	0
T10	25303	25203	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	499330282	481781	0	0
DepthKnown_A	499330282	499200393	0	0
RvalidKnown_A	499330282	499200393	0	0
WreadyKnown_A	499330282	499200393	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499330282	481781	0	0
T12	2243	15	0	0
T13	64768	1221	0	0
T14	60295	0	0	0
T15	29380	0	0	0
T16	85943	0	0	0
T17	71809	0	0	0
T18	88685	0	0	0
T24	10095	0	0	0
T25	180063	0	0	0
T26	124855	0	0	0
T29	0	12	0	0
T32	0	13	0	0
T43	0	766	0	0
T44	0	416	0	0
T45	0	81	0	0
T47	0	810	0	0
T48	0	454	0	0
T49	0	1407	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499330282	499200393	0	0
T1	1521	1460	0	0
T2	1086	1019	0	0
T3	1881	1831	0	0
T4	2746	2693	0	0
T5	11728	11662	0	0
T6	10995	8581	0	0
T7	22288	22210	0	0
T8	1513	1434	0	0
T9	1530	1434	0	0
T10	25303	25203	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499330282	499200393	0	0
T1	1521	1460	0	0
T2	1086	1019	0	0
T3	1881	1831	0	0
T4	2746	2693	0	0
T5	11728	11662	0	0
T6	10995	8581	0	0
T7	22288	22210	0	0
T8	1513	1434	0	0
T9	1530	1434	0	0
T10	25303	25203	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499330282	499200393	0	0
T1	1521	1460	0	0
T2	1086	1019	0	0
T3	1881	1831	0	0
T4	2746	2693	0	0
T5	11728	11662	0	0
T6	10995	8581	0	0
T7	22288	22210	0	0
T8	1513	1434	0	0
T9	1530	1434	0	0
T10	25303	25203	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	499330282	7075777	0	0
DepthKnown_A	499330282	499200393	0	0
RvalidKnown_A	499330282	499200393	0	0
WreadyKnown_A	499330282	499200393	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499330282	7075777	0	0
T1	1521	59	0	0
T2	1086	1	0	0
T3	1881	68	0	0
T4	2746	14	0	0
T5	11728	50	0	0
T6	10995	1	0	0
T7	22288	511	0	0
T8	1513	61	0	0
T9	1530	23	0	0
T10	25303	92	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499330282	499200393	0	0
T1	1521	1460	0	0
T2	1086	1019	0	0
T3	1881	1831	0	0
T4	2746	2693	0	0
T5	11728	11662	0	0
T6	10995	8581	0	0
T7	22288	22210	0	0
T8	1513	1434	0	0
T9	1530	1434	0	0
T10	25303	25203	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499330282	499200393	0	0
T1	1521	1460	0	0
T2	1086	1019	0	0
T3	1881	1831	0	0
T4	2746	2693	0	0
T5	11728	11662	0	0
T6	10995	8581	0	0
T7	22288	22210	0	0
T8	1513	1434	0	0
T9	1530	1434	0	0
T10	25303	25203	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499330282	499200393	0	0
T1	1521	1460	0	0
T2	1086	1019	0	0
T3	1881	1831	0	0
T4	2746	2693	0	0
T5	11728	11662	0	0
T6	10995	8581	0	0
T7	22288	22210	0	0
T8	1513	1434	0	0
T9	1530	1434	0	0
T10	25303	25203	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	499330282	16114647	0	0
DepthKnown_A	499330282	499200393	0	0
RvalidKnown_A	499330282	499200393	0	0
WreadyKnown_A	499330282	499200393	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499330282	16114647	0	0
T1	1521	59	0	0
T2	1086	1	0	0
T3	1881	68	0	0
T4	2746	76	0	0
T5	11728	247	0	0
T6	10995	7	0	0
T7	22288	1537	0	0
T8	1513	61	0	0
T9	1530	23	0	0
T10	25303	259	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499330282	499200393	0	0
T1	1521	1460	0	0
T2	1086	1019	0	0
T3	1881	1831	0	0
T4	2746	2693	0	0
T5	11728	11662	0	0
T6	10995	8581	0	0
T7	22288	22210	0	0
T8	1513	1434	0	0
T9	1530	1434	0	0
T10	25303	25203	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499330282	499200393	0	0
T1	1521	1460	0	0
T2	1086	1019	0	0
T3	1881	1831	0	0
T4	2746	2693	0	0
T5	11728	11662	0	0
T6	10995	8581	0	0
T7	22288	22210	0	0
T8	1513	1434	0	0
T9	1530	1434	0	0
T10	25303	25203	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499330282	499200393	0	0
T1	1521	1460	0	0
T2	1086	1019	0	0
T3	1881	1831	0	0
T4	2746	2693	0	0
T5	11728	11662	0	0
T6	10995	8581	0	0
T7	22288	22210	0	0
T8	1513	1434	0	0
T9	1530	1434	0	0
T10	25303	25203	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0