Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T3 T5 T7 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        unreachable          mask <= ppc_out;
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T3 T5 T7 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T3 T5 T7 
128                             end
                        MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T3 T4 T11 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T3 T12 T13 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T3 T4 T11 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        unreachable          mask <= ppc_out;
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T3 T12 T13 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T3 T12 T13 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T29
1	0	Covered	T3,T12,T13

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T11
1	0	Unreachable
1	1	Covered	T3,T12,T13

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T44,T49,T51

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T44,T49,T51
1	0	Covered	T44,T49,T51

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T10
1	0	Unreachable
1	1	Covered	T44,T49,T51

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T13,T29

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T12,T13
1	0	Covered	T5,T7,T10

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T3,T5,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T29
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==> (Unreachable)  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==> (Unreachable)
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T5,T7
0	0	1	Unreachable
0	0	0	Covered	T1,T3,T4

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T7
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	808242211	651044130	0	0
CheckNGreaterZero_A	2868	2868	0	0
GntImpliesReady_A	808242211	4004101	0	0
GntImpliesValid_A	808242211	4004101	0	0
GrantKnown_A	808242211	651044130	0	0
IdxKnown_A	808242211	651044130	0	0
IndexIsCorrect_A	808242211	4004101	0	0
LockArbDecision_A	808242211	0	0	0
NoReadyValidNoGrant_A	808242211	0	0	0
ReadyAndValidImplyGrant_A	808242211	4004101	0	0
ReqAndReadyImplyGrant_A	808242211	4004101	0	0
ReqImpliesValid_A	808242211	4004101	0	0
ReqStaysHighUntilGranted0_M	808242211	0	0	0
RoundRobin_A	808242211	5	0	956
ValidKnown_A	808242211	651044130	0	0
gen_data_port_assertion.DataFlow_A	808242211	4004101	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	808242211	651044130	0	0
T1	1521	1460	0	0
T2	1086	1019	0	0
T3	2305	2255	0	0
T4	3034	2981	0	0
T5	13200	12398	0	0
T6	10995	8581	0	0
T7	47970	35051	0	0
T8	1513	1434	0	0
T9	1530	1434	0	0
T10	35927	30515	0	0
T11	144	72	0	0
T12	1732	632	0	0
T13	226852	111408	0	0
T14	16448	8224	0	0
T15	50150	24648	0	0
T16	13747	13747	0	0
T25	75090	72192	0	0
T26	0	89832	0	0
T28	0	144	0	0
T29	0	3592	0	0
T30	0	58216	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2868	2868	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	808242211	4004101	0	0
T3	2305	24	0	0
T4	3034	0	0	0
T5	12464	832	0	0
T6	10995	0	0	0
T7	35129	1088	0	0
T8	1513	0	0	0
T9	1530	0	0	0
T10	30615	832	0	0
T11	1339	0	0	0
T12	3109	77	0	0
T13	113426	2505	0	0
T14	8224	832	0	0
T15	25075	832	0	0
T16	0	832	0	0
T24	0	832	0	0
T29	0	102	0	0
T32	0	102	0	0
T34	0	6213	0	0
T43	0	3781	0	0
T44	360253	2181	0	0
T45	0	95	0	0
T47	126953	4654	0	0
T48	0	2822	0	0
T49	0	8730	0	0
T51	0	3271	0	0
T55	84808	0	0	0
T57	43240	0	0	0
T63	0	2841	0	0
T75	89578	0	0	0
T76	61114	0	0	0
T77	15487	0	0	0
T78	24156	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	808242211	4004101	0	0
T3	2305	24	0	0
T4	3034	0	0	0
T5	12464	832	0	0
T6	10995	0	0	0
T7	35129	1088	0	0
T8	1513	0	0	0
T9	1530	0	0	0
T10	30615	832	0	0
T11	1339	0	0	0
T12	3109	77	0	0
T13	113426	2505	0	0
T14	8224	832	0	0
T15	25075	832	0	0
T16	0	832	0	0
T24	0	832	0	0
T29	0	102	0	0
T32	0	102	0	0
T34	0	6213	0	0
T43	0	3781	0	0
T44	360253	2181	0	0
T45	0	95	0	0
T47	126953	4654	0	0
T48	0	2822	0	0
T49	0	8730	0	0
T51	0	3271	0	0
T55	84808	0	0	0
T57	43240	0	0	0
T63	0	2841	0	0
T75	89578	0	0	0
T76	61114	0	0	0
T77	15487	0	0	0
T78	24156	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	808242211	651044130	0	0
T1	1521	1460	0	0
T2	1086	1019	0	0
T3	2305	2255	0	0
T4	3034	2981	0	0
T5	13200	12398	0	0
T6	10995	8581	0	0
T7	47970	35051	0	0
T8	1513	1434	0	0
T9	1530	1434	0	0
T10	35927	30515	0	0
T11	144	72	0	0
T12	1732	632	0	0
T13	226852	111408	0	0
T14	16448	8224	0	0
T15	50150	24648	0	0
T16	13747	13747	0	0
T25	75090	72192	0	0
T26	0	89832	0	0
T28	0	144	0	0
T29	0	3592	0	0
T30	0	58216	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	808242211	651044130	0	0
T1	1521	1460	0	0
T2	1086	1019	0	0
T3	2305	2255	0	0
T4	3034	2981	0	0
T5	13200	12398	0	0
T6	10995	8581	0	0
T7	47970	35051	0	0
T8	1513	1434	0	0
T9	1530	1434	0	0
T10	35927	30515	0	0
T11	144	72	0	0
T12	1732	632	0	0
T13	226852	111408	0	0
T14	16448	8224	0	0
T15	50150	24648	0	0
T16	13747	13747	0	0
T25	75090	72192	0	0
T26	0	89832	0	0
T28	0	144	0	0
T29	0	3592	0	0
T30	0	58216	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	808242211	4004101	0	0
T3	2305	24	0	0
T4	3034	0	0	0
T5	12464	832	0	0
T6	10995	0	0	0
T7	35129	1088	0	0
T8	1513	0	0	0
T9	1530	0	0	0
T10	30615	832	0	0
T11	1339	0	0	0
T12	3109	77	0	0
T13	113426	2505	0	0
T14	8224	832	0	0
T15	25075	832	0	0
T16	0	832	0	0
T24	0	832	0	0
T29	0	102	0	0
T32	0	102	0	0
T34	0	6213	0	0
T43	0	3781	0	0
T44	360253	2181	0	0
T45	0	95	0	0
T47	126953	4654	0	0
T48	0	2822	0	0
T49	0	8730	0	0
T51	0	3271	0	0
T55	84808	0	0	0
T57	43240	0	0	0
T63	0	2841	0	0
T75	89578	0	0	0
T76	61114	0	0	0
T77	15487	0	0	0
T78	24156	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	808242211	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	808242211	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	808242211	4004101	0	0
T3	2305	24	0	0
T4	3034	0	0	0
T5	12464	832	0	0
T6	10995	0	0	0
T7	35129	1088	0	0
T8	1513	0	0	0
T9	1530	0	0	0
T10	30615	832	0	0
T11	1339	0	0	0
T12	3109	77	0	0
T13	113426	2505	0	0
T14	8224	832	0	0
T15	25075	832	0	0
T16	0	832	0	0
T24	0	832	0	0
T29	0	102	0	0
T32	0	102	0	0
T34	0	6213	0	0
T43	0	3781	0	0
T44	360253	2181	0	0
T45	0	95	0	0
T47	126953	4654	0	0
T48	0	2822	0	0
T49	0	8730	0	0
T51	0	3271	0	0
T55	84808	0	0	0
T57	43240	0	0	0
T63	0	2841	0	0
T75	89578	0	0	0
T76	61114	0	0	0
T77	15487	0	0	0
T78	24156	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	808242211	4004101	0	0
T3	2305	24	0	0
T4	3034	0	0	0
T5	12464	832	0	0
T6	10995	0	0	0
T7	35129	1088	0	0
T8	1513	0	0	0
T9	1530	0	0	0
T10	30615	832	0	0
T11	1339	0	0	0
T12	3109	77	0	0
T13	113426	2505	0	0
T14	8224	832	0	0
T15	25075	832	0	0
T16	0	832	0	0
T24	0	832	0	0
T29	0	102	0	0
T32	0	102	0	0
T34	0	6213	0	0
T43	0	3781	0	0
T44	360253	2181	0	0
T45	0	95	0	0
T47	126953	4654	0	0
T48	0	2822	0	0
T49	0	8730	0	0
T51	0	3271	0	0
T55	84808	0	0	0
T57	43240	0	0	0
T63	0	2841	0	0
T75	89578	0	0	0
T76	61114	0	0	0
T77	15487	0	0	0
T78	24156	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	808242211	4004101	0	0
T3	2305	24	0	0
T4	3034	0	0	0
T5	12464	832	0	0
T6	10995	0	0	0
T7	35129	1088	0	0
T8	1513	0	0	0
T9	1530	0	0	0
T10	30615	832	0	0
T11	1339	0	0	0
T12	3109	77	0	0
T13	113426	2505	0	0
T14	8224	832	0	0
T15	25075	832	0	0
T16	0	832	0	0
T24	0	832	0	0
T29	0	102	0	0
T32	0	102	0	0
T34	0	6213	0	0
T43	0	3781	0	0
T44	360253	2181	0	0
T45	0	95	0	0
T47	126953	4654	0	0
T48	0	2822	0	0
T49	0	8730	0	0
T51	0	3271	0	0
T55	84808	0	0	0
T57	43240	0	0	0
T63	0	2841	0	0
T75	89578	0	0	0
T76	61114	0	0	0
T77	15487	0	0	0
T78	24156	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	808242211	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	808242211	5	0	956
T40	696721	1	0	1
T79	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	1358	0	0	1
T84	126075	0	0	1
T85	102673	0	0	1
T86	2423	0	0	1
T87	10563	0	0	1
T88	658623	0	0	1
T89	40359	0	0	1
T90	273306	0	0	1
T91	484195	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	808242211	651044130	0	0
T1	1521	1460	0	0
T2	1086	1019	0	0
T3	2305	2255	0	0
T4	3034	2981	0	0
T5	13200	12398	0	0
T6	10995	8581	0	0
T7	47970	35051	0	0
T8	1513	1434	0	0
T9	1530	1434	0	0
T10	35927	30515	0	0
T11	144	72	0	0
T12	1732	632	0	0
T13	226852	111408	0	0
T14	16448	8224	0	0
T15	50150	24648	0	0
T16	13747	13747	0	0
T25	75090	72192	0	0
T26	0	89832	0	0
T28	0	144	0	0
T29	0	3592	0	0
T30	0	58216	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	808242211	4004101	0	0
T3	2305	24	0	0
T4	3034	0	0	0
T5	12464	832	0	0
T6	10995	0	0	0
T7	35129	1088	0	0
T8	1513	0	0	0
T9	1530	0	0	0
T10	30615	832	0	0
T11	1339	0	0	0
T12	3109	77	0	0
T13	113426	2505	0	0
T14	8224	832	0	0
T15	25075	832	0	0
T16	0	832	0	0
T24	0	832	0	0
T29	0	102	0	0
T32	0	102	0	0
T34	0	6213	0	0
T43	0	3781	0	0
T44	360253	2181	0	0
T45	0	95	0	0
T47	126953	4654	0	0
T48	0	2822	0	0
T49	0	8730	0	0
T51	0	3271	0	0
T55	84808	0	0	0
T57	43240	0	0	0
T63	0	2841	0	0
T75	89578	0	0	0
T76	61114	0	0	0
T77	15487	0	0	0
T78	24156	0	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T3 T4 T11 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T3 T12 T13 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T3 T4 T11 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        unreachable          mask <= ppc_out;
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T3 T12 T13 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T3 T12 T13 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T29
1	0	Covered	T3,T12,T13

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T11
1	0	Unreachable
1	1	Covered	T3,T12,T13

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==> (Unreachable)  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==> (Unreachable)
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T12,T13
0	0	1	Unreachable
0	0	0	Covered	T3,T4,T11

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T3,T12,T13
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T3,T12,T13
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	155611271	30288372	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	155611271	719671	0	0
GntImpliesValid_A	155611271	719671	0	0
GrantKnown_A	155611271	30288372	0	0
IdxKnown_A	155611271	30288372	0	0
IndexIsCorrect_A	155611271	719671	0	0
LockArbDecision_A	155611271	0	0	0
NoReadyValidNoGrant_A	155611271	0	0	0
ReadyAndValidImplyGrant_A	155611271	719671	0	0
ReqAndReadyImplyGrant_A	155611271	719671	0	0
ReqImpliesValid_A	155611271	719671	0	0
ReqStaysHighUntilGranted0_M	155611271	0	0	0
RoundRobin_A	155611271	0	0	0
ValidKnown_A	155611271	30288372	0	0
gen_data_port_assertion.DataFlow_A	155611271	719671	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155611271	30288372	0	0
T3	424	424	0	0
T4	288	288	0	0
T5	736	0	0	0
T7	12841	0	0	0
T10	5312	0	0	0
T11	72	72	0	0
T12	866	632	0	0
T13	113426	111408	0	0
T14	8224	0	0	0
T15	25075	0	0	0
T25	0	72192	0	0
T26	0	89832	0	0
T28	0	144	0	0
T29	0	3592	0	0
T30	0	58216	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155611271	719671	0	0
T3	424	12	0	0
T4	288	0	0	0
T5	736	0	0	0
T7	12841	0	0	0
T10	5312	0	0	0
T11	72	0	0	0
T12	866	61	0	0
T13	113426	1661	0	0
T14	8224	0	0	0
T15	25075	0	0	0
T29	0	102	0	0
T32	0	102	0	0
T43	0	3781	0	0
T45	0	95	0	0
T47	0	4654	0	0
T48	0	2822	0	0
T49	0	5475	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155611271	719671	0	0
T3	424	12	0	0
T4	288	0	0	0
T5	736	0	0	0
T7	12841	0	0	0
T10	5312	0	0	0
T11	72	0	0	0
T12	866	61	0	0
T13	113426	1661	0	0
T14	8224	0	0	0
T15	25075	0	0	0
T29	0	102	0	0
T32	0	102	0	0
T43	0	3781	0	0
T45	0	95	0	0
T47	0	4654	0	0
T48	0	2822	0	0
T49	0	5475	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155611271	30288372	0	0
T3	424	424	0	0
T4	288	288	0	0
T5	736	0	0	0
T7	12841	0	0	0
T10	5312	0	0	0
T11	72	72	0	0
T12	866	632	0	0
T13	113426	111408	0	0
T14	8224	0	0	0
T15	25075	0	0	0
T25	0	72192	0	0
T26	0	89832	0	0
T28	0	144	0	0
T29	0	3592	0	0
T30	0	58216	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155611271	30288372	0	0
T3	424	424	0	0
T4	288	288	0	0
T5	736	0	0	0
T7	12841	0	0	0
T10	5312	0	0	0
T11	72	72	0	0
T12	866	632	0	0
T13	113426	111408	0	0
T14	8224	0	0	0
T15	25075	0	0	0
T25	0	72192	0	0
T26	0	89832	0	0
T28	0	144	0	0
T29	0	3592	0	0
T30	0	58216	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155611271	719671	0	0
T3	424	12	0	0
T4	288	0	0	0
T5	736	0	0	0
T7	12841	0	0	0
T10	5312	0	0	0
T11	72	0	0	0
T12	866	61	0	0
T13	113426	1661	0	0
T14	8224	0	0	0
T15	25075	0	0	0
T29	0	102	0	0
T32	0	102	0	0
T43	0	3781	0	0
T45	0	95	0	0
T47	0	4654	0	0
T48	0	2822	0	0
T49	0	5475	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155611271	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155611271	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155611271	719671	0	0
T3	424	12	0	0
T4	288	0	0	0
T5	736	0	0	0
T7	12841	0	0	0
T10	5312	0	0	0
T11	72	0	0	0
T12	866	61	0	0
T13	113426	1661	0	0
T14	8224	0	0	0
T15	25075	0	0	0
T29	0	102	0	0
T32	0	102	0	0
T43	0	3781	0	0
T45	0	95	0	0
T47	0	4654	0	0
T48	0	2822	0	0
T49	0	5475	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155611271	719671	0	0
T3	424	12	0	0
T4	288	0	0	0
T5	736	0	0	0
T7	12841	0	0	0
T10	5312	0	0	0
T11	72	0	0	0
T12	866	61	0	0
T13	113426	1661	0	0
T14	8224	0	0	0
T15	25075	0	0	0
T29	0	102	0	0
T32	0	102	0	0
T43	0	3781	0	0
T45	0	95	0	0
T47	0	4654	0	0
T48	0	2822	0	0
T49	0	5475	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155611271	719671	0	0
T3	424	12	0	0
T4	288	0	0	0
T5	736	0	0	0
T7	12841	0	0	0
T10	5312	0	0	0
T11	72	0	0	0
T12	866	61	0	0
T13	113426	1661	0	0
T14	8224	0	0	0
T15	25075	0	0	0
T29	0	102	0	0
T32	0	102	0	0
T43	0	3781	0	0
T45	0	95	0	0
T47	0	4654	0	0
T48	0	2822	0	0
T49	0	5475	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	155611271	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155611271	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155611271	30288372	0	0
T3	424	424	0	0
T4	288	288	0	0
T5	736	0	0	0
T7	12841	0	0	0
T10	5312	0	0	0
T11	72	72	0	0
T12	866	632	0	0
T13	113426	111408	0	0
T14	8224	0	0	0
T15	25075	0	0	0
T25	0	72192	0	0
T26	0	89832	0	0
T28	0	144	0	0
T29	0	3592	0	0
T30	0	58216	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155611271	719671	0	0
T3	424	12	0	0
T4	288	0	0	0
T5	736	0	0	0
T7	12841	0	0	0
T10	5312	0	0	0
T11	72	0	0	0
T12	866	61	0	0
T13	113426	1661	0	0
T14	8224	0	0	0
T15	25075	0	0	0
T29	0	102	0	0
T32	0	102	0	0
T43	0	3781	0	0
T45	0	95	0	0
T47	0	4654	0	0
T48	0	2822	0	0
T49	0	5475	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T5 T7 T10 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T44 T49 T51 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T5 T7 T10 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        unreachable          mask <= ppc_out;
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T44 T49 T51 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T44 T49 T51 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T44,T49,T51

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T44,T49,T51
1	0	Covered	T44,T49,T51

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T10
1	0	Unreachable
1	1	Covered	T44,T49,T51

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T44,T49,T51
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==> (Unreachable)  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==> (Unreachable)
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T44,T49,T51
0	0	1	Unreachable
0	0	0	Covered	T5,T7,T10

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T44,T49,T51
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T44,T49,T51
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	155611271	123824450	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	155611271	892523	0	0
GntImpliesValid_A	155611271	892523	0	0
GrantKnown_A	155611271	123824450	0	0
IdxKnown_A	155611271	123824450	0	0
IndexIsCorrect_A	155611271	892523	0	0
LockArbDecision_A	155611271	0	0	0
NoReadyValidNoGrant_A	155611271	0	0	0
ReadyAndValidImplyGrant_A	155611271	892523	0	0
ReqAndReadyImplyGrant_A	155611271	892523	0	0
ReqImpliesValid_A	155611271	892523	0	0
ReqStaysHighUntilGranted0_M	155611271	0	0	0
RoundRobin_A	155611271	0	0	0
ValidKnown_A	155611271	123824450	0	0
gen_data_port_assertion.DataFlow_A	155611271	892523	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155611271	123824450	0	0
T5	736	736	0	0
T7	12841	12841	0	0
T10	5312	5312	0	0
T11	72	0	0	0
T12	866	0	0	0
T13	113426	0	0	0
T14	8224	8224	0	0
T15	25075	24648	0	0
T16	13747	13747	0	0
T17	0	16592	0	0
T18	0	10704	0	0
T19	0	101638	0	0
T20	0	26682	0	0
T25	75090	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155611271	892523	0	0
T34	0	6213	0	0
T44	360253	2181	0	0
T46	0	514	0	0
T47	126953	0	0	0
T49	0	3255	0	0
T51	0	3271	0	0
T55	84808	0	0	0
T57	43240	0	0	0
T63	0	2841	0	0
T65	0	1036	0	0
T66	0	4	0	0
T75	89578	0	0	0
T76	61114	0	0	0
T77	15487	0	0	0
T78	24156	0	0	0
T92	0	1322	0	0
T93	0	7277	0	0
T94	211388	0	0	0
T95	25728	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155611271	892523	0	0
T34	0	6213	0	0
T44	360253	2181	0	0
T46	0	514	0	0
T47	126953	0	0	0
T49	0	3255	0	0
T51	0	3271	0	0
T55	84808	0	0	0
T57	43240	0	0	0
T63	0	2841	0	0
T65	0	1036	0	0
T66	0	4	0	0
T75	89578	0	0	0
T76	61114	0	0	0
T77	15487	0	0	0
T78	24156	0	0	0
T92	0	1322	0	0
T93	0	7277	0	0
T94	211388	0	0	0
T95	25728	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155611271	123824450	0	0
T5	736	736	0	0
T7	12841	12841	0	0
T10	5312	5312	0	0
T11	72	0	0	0
T12	866	0	0	0
T13	113426	0	0	0
T14	8224	8224	0	0
T15	25075	24648	0	0
T16	13747	13747	0	0
T17	0	16592	0	0
T18	0	10704	0	0
T19	0	101638	0	0
T20	0	26682	0	0
T25	75090	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155611271	123824450	0	0
T5	736	736	0	0
T7	12841	12841	0	0
T10	5312	5312	0	0
T11	72	0	0	0
T12	866	0	0	0
T13	113426	0	0	0
T14	8224	8224	0	0
T15	25075	24648	0	0
T16	13747	13747	0	0
T17	0	16592	0	0
T18	0	10704	0	0
T19	0	101638	0	0
T20	0	26682	0	0
T25	75090	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155611271	892523	0	0
T34	0	6213	0	0
T44	360253	2181	0	0
T46	0	514	0	0
T47	126953	0	0	0
T49	0	3255	0	0
T51	0	3271	0	0
T55	84808	0	0	0
T57	43240	0	0	0
T63	0	2841	0	0
T65	0	1036	0	0
T66	0	4	0	0
T75	89578	0	0	0
T76	61114	0	0	0
T77	15487	0	0	0
T78	24156	0	0	0
T92	0	1322	0	0
T93	0	7277	0	0
T94	211388	0	0	0
T95	25728	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155611271	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155611271	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155611271	892523	0	0
T34	0	6213	0	0
T44	360253	2181	0	0
T46	0	514	0	0
T47	126953	0	0	0
T49	0	3255	0	0
T51	0	3271	0	0
T55	84808	0	0	0
T57	43240	0	0	0
T63	0	2841	0	0
T65	0	1036	0	0
T66	0	4	0	0
T75	89578	0	0	0
T76	61114	0	0	0
T77	15487	0	0	0
T78	24156	0	0	0
T92	0	1322	0	0
T93	0	7277	0	0
T94	211388	0	0	0
T95	25728	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155611271	892523	0	0
T34	0	6213	0	0
T44	360253	2181	0	0
T46	0	514	0	0
T47	126953	0	0	0
T49	0	3255	0	0
T51	0	3271	0	0
T55	84808	0	0	0
T57	43240	0	0	0
T63	0	2841	0	0
T65	0	1036	0	0
T66	0	4	0	0
T75	89578	0	0	0
T76	61114	0	0	0
T77	15487	0	0	0
T78	24156	0	0	0
T92	0	1322	0	0
T93	0	7277	0	0
T94	211388	0	0	0
T95	25728	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155611271	892523	0	0
T34	0	6213	0	0
T44	360253	2181	0	0
T46	0	514	0	0
T47	126953	0	0	0
T49	0	3255	0	0
T51	0	3271	0	0
T55	84808	0	0	0
T57	43240	0	0	0
T63	0	2841	0	0
T65	0	1036	0	0
T66	0	4	0	0
T75	89578	0	0	0
T76	61114	0	0	0
T77	15487	0	0	0
T78	24156	0	0	0
T92	0	1322	0	0
T93	0	7277	0	0
T94	211388	0	0	0
T95	25728	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	155611271	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155611271	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155611271	123824450	0	0
T5	736	736	0	0
T7	12841	12841	0	0
T10	5312	5312	0	0
T11	72	0	0	0
T12	866	0	0	0
T13	113426	0	0	0
T14	8224	8224	0	0
T15	25075	24648	0	0
T16	13747	13747	0	0
T17	0	16592	0	0
T18	0	10704	0	0
T19	0	101638	0	0
T20	0	26682	0	0
T25	75090	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	155611271	892523	0	0
T34	0	6213	0	0
T44	360253	2181	0	0
T46	0	514	0	0
T47	126953	0	0	0
T49	0	3255	0	0
T51	0	3271	0	0
T55	84808	0	0	0
T57	43240	0	0	0
T63	0	2841	0	0
T65	0	1036	0	0
T66	0	4	0	0
T75	89578	0	0	0
T76	61114	0	0	0
T77	15487	0	0	0
T78	24156	0	0	0
T92	0	1322	0	0
T93	0	7277	0	0
T94	211388	0	0	0
T95	25728	0	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

54                        logic unused_req_chk;
55         unreachable    assign unused_req_chk = req_chk_i;
56                      
57                        `ASSERT_INIT(CheckNGreaterZero_A, N > 0)
58                      
59                        // this case is basically just a bypass
60                        if (N == 1) begin : gen_degenerate_case
61                      
62                          assign valid_o  = req_i[0];
63                          assign data_o   = data_i[0];
64                          assign gnt_o[0] = valid_o & ready_i;
65                          assign idx_o    = '0;
66                      
67                        end else begin : gen_normal_case
68                      
69                          logic [N-1:0] masked_req;
70                          logic [N-1:0] ppc_out;
71                          logic [N-1:0] arb_req;
72                          logic [N-1:0] mask, mask_next;
73                          logic [N-1:0] winner;
74                      
75         1/1              assign masked_req = mask & req_i;
           Tests:       T1 T2 T3 
76         1/1              assign arb_req = (|masked_req) ? masked_req : req_i;
           Tests:       T1 T2 T3 
77                      
78                          // PPC
79                          //   Even below code looks O(n) but DC optimizes it to O(log(N))
80                          //   Using Parallel Prefix Computation
81                          always_comb begin
82         1/1                ppc_out[0] = arb_req[0];
           Tests:       T1 T2 T3 
83         1/1                for (int i = 1 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
84         1/1                  ppc_out[i] = ppc_out[i-1] | arb_req[i];
           Tests:       T1 T2 T3 
85                            end
86                          end
87                      
88                          // Grant Generation: Leading-One detector
89         1/1              assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
90         1/1              assign gnt_o    = (ready_i) ? winner : '0;
           Tests:       T1 T2 T3 
91                      
92         1/1              assign valid_o = |req_i;
           Tests:       T1 T2 T3 
93                          // Mask Generation
94         1/1              assign mask_next = {ppc_out[N-2:0], 1'b0};
           Tests:       T1 T2 T3 
95                          always_ff @(posedge clk_i or negedge rst_ni) begin
96         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
97         1/1                  mask <= '0;
           Tests:       T1 T2 T3 
98         1/1                end else if (valid_o && ready_i) begin
           Tests:       T1 T2 T3 
99                              // Latch only when requests accepted
100        1/1                  mask <= mask_next;
           Tests:       T3 T5 T7 
101        1/1                end else if (valid_o && !ready_i) begin
           Tests:       T1 T2 T3 
102                             // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103        unreachable          mask <= ppc_out;
104                           end
                        MISSING_ELSE
105                         end
106                     
107                         if (EnDataPort == 1) begin: gen_datapath
108                           always_comb begin
109        1/1                  data_o = '0;
           Tests:       T1 T2 T3 
110        1/1                  for (int i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
111        1/1                    if (winner[i]) begin
           Tests:       T1 T2 T3 
112        1/1                      data_o = data_i[i];
           Tests:       T3 T5 T7 
113                               end
                        MISSING_ELSE
114                             end
115                           end
116                         end else begin: gen_nodatapath
117                           assign data_o = '1;
118                           // The following signal is used to avoid possible lint errors.
119                           logic [DW-1:0] unused_data [N];
120                           assign unused_data = data_i;
121                         end
122                     
123                         always_comb begin
124        1/1                idx_o = '0;
           Tests:       T1 T2 T3 
125        1/1                for (int unsigned i = 0 ; i < N ; i++) begin
           Tests:       T1 T2 T3 
126        1/1                  if (winner[i]) begin
           Tests:       T1 T2 T3 
127        1/1                    idx_o = i[IdxW-1:0];
           Tests:       T3 T5 T7 
128                             end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T13,T29

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T12,T13
1	0	Covered	T5,T7,T10

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T3,T5,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

76             assign arb_req = (|masked_req) ? masked_req : req_i;
                                              -1-  
                                              ==>  
                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T29
0	Covered	T1,T2,T3

90             assign gnt_o    = (ready_i) ? winner : '0;
                                           -1-  
                                           ==>  
                                           ==> (Unreachable)  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

96               if (!rst_ni) begin
                 -1-  
97                 mask <= '0;
                   ==>
98               end else if (valid_o && ready_i) begin
                          -2-  
99                 // Latch only when requests accepted
100                mask <= mask_next;
                   ==>
101              end else if (valid_o && !ready_i) begin
                          -3-  
102                // Downstream isn't yet ready so, keep current request alive. (First come first serve)
103                mask <= ppc_out;
                   ==> (Unreachable)
104              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T5,T7
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

126                if (winner[i]) begin
                   -1-  
127                  idx_o = i[IdxW-1:0];
                     ==>
128                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T7
0	Covered	T1,T2,T3

111                  if (winner[i]) begin
                     -1-  
112                    data_o = data_i[i];
                       ==>
113                  end
                     MISSING_ELSE
                     ==>

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	497019669	496931308	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	497019669	2391907	0	0
GntImpliesValid_A	497019669	2391907	0	0
GrantKnown_A	497019669	496931308	0	0
IdxKnown_A	497019669	496931308	0	0
IndexIsCorrect_A	497019669	2391907	0	0
LockArbDecision_A	497019669	0	0	0
NoReadyValidNoGrant_A	497019669	0	0	0
ReadyAndValidImplyGrant_A	497019669	2391907	0	0
ReqAndReadyImplyGrant_A	497019669	2391907	0	0
ReqImpliesValid_A	497019669	2391907	0	0
ReqStaysHighUntilGranted0_M	497019669	0	0	0
RoundRobin_A	497019669	5	0	956
ValidKnown_A	497019669	496931308	0	0
gen_data_port_assertion.DataFlow_A	497019669	2391907	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497019669	496931308	0	0
T1	1521	1460	0	0
T2	1086	1019	0	0
T3	1881	1831	0	0
T4	2746	2693	0	0
T5	11728	11662	0	0
T6	10995	8581	0	0
T7	22288	22210	0	0
T8	1513	1434	0	0
T9	1530	1434	0	0
T10	25303	25203	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497019669	2391907	0	0
T3	1881	12	0	0
T4	2746	0	0	0
T5	11728	832	0	0
T6	10995	0	0	0
T7	22288	1088	0	0
T8	1513	0	0	0
T9	1530	0	0	0
T10	25303	832	0	0
T11	1267	0	0	0
T12	2243	16	0	0
T13	0	844	0	0
T14	0	832	0	0
T15	0	832	0	0
T16	0	832	0	0
T24	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497019669	2391907	0	0
T3	1881	12	0	0
T4	2746	0	0	0
T5	11728	832	0	0
T6	10995	0	0	0
T7	22288	1088	0	0
T8	1513	0	0	0
T9	1530	0	0	0
T10	25303	832	0	0
T11	1267	0	0	0
T12	2243	16	0	0
T13	0	844	0	0
T14	0	832	0	0
T15	0	832	0	0
T16	0	832	0	0
T24	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497019669	496931308	0	0
T1	1521	1460	0	0
T2	1086	1019	0	0
T3	1881	1831	0	0
T4	2746	2693	0	0
T5	11728	11662	0	0
T6	10995	8581	0	0
T7	22288	22210	0	0
T8	1513	1434	0	0
T9	1530	1434	0	0
T10	25303	25203	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497019669	496931308	0	0
T1	1521	1460	0	0
T2	1086	1019	0	0
T3	1881	1831	0	0
T4	2746	2693	0	0
T5	11728	11662	0	0
T6	10995	8581	0	0
T7	22288	22210	0	0
T8	1513	1434	0	0
T9	1530	1434	0	0
T10	25303	25203	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497019669	2391907	0	0
T3	1881	12	0	0
T4	2746	0	0	0
T5	11728	832	0	0
T6	10995	0	0	0
T7	22288	1088	0	0
T8	1513	0	0	0
T9	1530	0	0	0
T10	25303	832	0	0
T11	1267	0	0	0
T12	2243	16	0	0
T13	0	844	0	0
T14	0	832	0	0
T15	0	832	0	0
T16	0	832	0	0
T24	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497019669	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497019669	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497019669	2391907	0	0
T3	1881	12	0	0
T4	2746	0	0	0
T5	11728	832	0	0
T6	10995	0	0	0
T7	22288	1088	0	0
T8	1513	0	0	0
T9	1530	0	0	0
T10	25303	832	0	0
T11	1267	0	0	0
T12	2243	16	0	0
T13	0	844	0	0
T14	0	832	0	0
T15	0	832	0	0
T16	0	832	0	0
T24	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497019669	2391907	0	0
T3	1881	12	0	0
T4	2746	0	0	0
T5	11728	832	0	0
T6	10995	0	0	0
T7	22288	1088	0	0
T8	1513	0	0	0
T9	1530	0	0	0
T10	25303	832	0	0
T11	1267	0	0	0
T12	2243	16	0	0
T13	0	844	0	0
T14	0	832	0	0
T15	0	832	0	0
T16	0	832	0	0
T24	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497019669	2391907	0	0
T3	1881	12	0	0
T4	2746	0	0	0
T5	11728	832	0	0
T6	10995	0	0	0
T7	22288	1088	0	0
T8	1513	0	0	0
T9	1530	0	0	0
T10	25303	832	0	0
T11	1267	0	0	0
T12	2243	16	0	0
T13	0	844	0	0
T14	0	832	0	0
T15	0	832	0	0
T16	0	832	0	0
T24	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	497019669	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497019669	5	0	956
T40	696721	1	0	1
T79	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	1358	0	0	1
T84	126075	0	0	1
T85	102673	0	0	1
T86	2423	0	0	1
T87	10563	0	0	1
T88	658623	0	0	1
T89	40359	0	0	1
T90	273306	0	0	1
T91	484195	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497019669	496931308	0	0
T1	1521	1460	0	0
T2	1086	1019	0	0
T3	1881	1831	0	0
T4	2746	2693	0	0
T5	11728	11662	0	0
T6	10995	8581	0	0
T7	22288	22210	0	0
T8	1513	1434	0	0
T9	1530	1434	0	0
T10	25303	25203	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497019669	2391907	0	0
T3	1881	12	0	0
T4	2746	0	0	0
T5	11728	832	0	0
T6	10995	0	0	0
T7	22288	1088	0	0
T8	1513	0	0	0
T9	1530	0	0	0
T10	25303	832	0	0
T11	1267	0	0	0
T12	2243	16	0	0
T13	0	844	0	0
T14	0	832	0	0
T15	0	832	0	0
T16	0	832	0	0
T24	0	832	0	0