Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
4172 |
0 |
0 |
T100 |
3833 |
89 |
0 |
0 |
T101 |
3698 |
3 |
0 |
0 |
T116 |
10156 |
3 |
0 |
0 |
T117 |
19507 |
302 |
0 |
0 |
T118 |
30282 |
9 |
0 |
0 |
T119 |
6505 |
81 |
0 |
0 |
T129 |
19648 |
323 |
0 |
0 |
T130 |
8532 |
7 |
0 |
0 |
T135 |
5233 |
15 |
0 |
0 |
T136 |
8686 |
2 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
1607 |
0 |
0 |
T106 |
2896 |
2 |
0 |
0 |
T124 |
15544 |
8 |
0 |
0 |
T146 |
90951 |
212 |
0 |
0 |
T148 |
7535 |
5 |
0 |
0 |
T170 |
8735 |
13 |
0 |
0 |
T171 |
7869 |
33 |
0 |
0 |
T172 |
88390 |
62 |
0 |
0 |
T173 |
37305 |
36 |
0 |
0 |
T174 |
18368 |
48 |
0 |
0 |
T175 |
34598 |
43 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
1604 |
0 |
0 |
T106 |
2896 |
17 |
0 |
0 |
T146 |
90951 |
213 |
0 |
0 |
T148 |
7535 |
10 |
0 |
0 |
T170 |
8735 |
10 |
0 |
0 |
T171 |
7869 |
20 |
0 |
0 |
T172 |
88390 |
45 |
0 |
0 |
T173 |
37305 |
44 |
0 |
0 |
T174 |
18368 |
17 |
0 |
0 |
T175 |
34598 |
32 |
0 |
0 |
T176 |
106423 |
450 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
2018 |
0 |
0 |
T106 |
2896 |
9 |
0 |
0 |
T124 |
15544 |
8 |
0 |
0 |
T129 |
19648 |
1 |
0 |
0 |
T146 |
90951 |
199 |
0 |
0 |
T148 |
7535 |
30 |
0 |
0 |
T170 |
8735 |
24 |
0 |
0 |
T172 |
88390 |
153 |
0 |
0 |
T173 |
37305 |
69 |
0 |
0 |
T174 |
18368 |
65 |
0 |
0 |
T175 |
34598 |
67 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
7323 |
0 |
0 |
T106 |
2896 |
3 |
0 |
0 |
T146 |
90951 |
250 |
0 |
0 |
T148 |
7535 |
11 |
0 |
0 |
T170 |
8735 |
109 |
0 |
0 |
T171 |
7869 |
35 |
0 |
0 |
T172 |
88390 |
946 |
0 |
0 |
T173 |
37305 |
455 |
0 |
0 |
T174 |
18368 |
72 |
0 |
0 |
T175 |
34598 |
522 |
0 |
0 |
T176 |
106423 |
410 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
8837 |
0 |
0 |
T106 |
2896 |
8 |
0 |
0 |
T146 |
90951 |
230 |
0 |
0 |
T148 |
7535 |
127 |
0 |
0 |
T170 |
8735 |
226 |
0 |
0 |
T171 |
7869 |
25 |
0 |
0 |
T172 |
88390 |
1352 |
0 |
0 |
T173 |
37305 |
872 |
0 |
0 |
T174 |
18368 |
41 |
0 |
0 |
T175 |
34598 |
706 |
0 |
0 |
T176 |
106423 |
411 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
8030 |
0 |
0 |
T106 |
2896 |
3 |
0 |
0 |
T146 |
90951 |
220 |
0 |
0 |
T148 |
7535 |
131 |
0 |
0 |
T170 |
8735 |
129 |
0 |
0 |
T171 |
7869 |
29 |
0 |
0 |
T172 |
88390 |
959 |
0 |
0 |
T173 |
37305 |
616 |
0 |
0 |
T174 |
18368 |
13 |
0 |
0 |
T175 |
34598 |
893 |
0 |
0 |
T177 |
5796 |
9 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
7377 |
0 |
0 |
T106 |
2896 |
3 |
0 |
0 |
T146 |
90951 |
209 |
0 |
0 |
T148 |
7535 |
244 |
0 |
0 |
T170 |
8735 |
144 |
0 |
0 |
T171 |
7869 |
62 |
0 |
0 |
T172 |
88390 |
910 |
0 |
0 |
T173 |
37305 |
743 |
0 |
0 |
T174 |
18368 |
19 |
0 |
0 |
T175 |
34598 |
414 |
0 |
0 |
T176 |
106423 |
316 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
6716 |
0 |
0 |
T106 |
2896 |
8 |
0 |
0 |
T146 |
90951 |
207 |
0 |
0 |
T148 |
7535 |
99 |
0 |
0 |
T170 |
8735 |
91 |
0 |
0 |
T172 |
88390 |
1003 |
0 |
0 |
T173 |
37305 |
575 |
0 |
0 |
T174 |
18368 |
26 |
0 |
0 |
T175 |
34598 |
787 |
0 |
0 |
T176 |
106423 |
382 |
0 |
0 |
T178 |
10452 |
131 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
7153 |
0 |
0 |
T106 |
2896 |
5 |
0 |
0 |
T146 |
90951 |
226 |
0 |
0 |
T148 |
7535 |
250 |
0 |
0 |
T170 |
8735 |
278 |
0 |
0 |
T171 |
7869 |
41 |
0 |
0 |
T172 |
88390 |
693 |
0 |
0 |
T173 |
37305 |
489 |
0 |
0 |
T174 |
18368 |
15 |
0 |
0 |
T175 |
34598 |
384 |
0 |
0 |
T176 |
106423 |
381 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
7104 |
0 |
0 |
T106 |
2896 |
11 |
0 |
0 |
T146 |
90951 |
222 |
0 |
0 |
T148 |
7535 |
87 |
0 |
0 |
T170 |
8735 |
241 |
0 |
0 |
T171 |
7869 |
17 |
0 |
0 |
T172 |
88390 |
956 |
0 |
0 |
T173 |
37305 |
606 |
0 |
0 |
T174 |
18368 |
31 |
0 |
0 |
T175 |
34598 |
345 |
0 |
0 |
T176 |
106423 |
366 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
7876 |
0 |
0 |
T106 |
2896 |
6 |
0 |
0 |
T146 |
90951 |
228 |
0 |
0 |
T148 |
7535 |
227 |
0 |
0 |
T170 |
8735 |
100 |
0 |
0 |
T171 |
7869 |
5 |
0 |
0 |
T172 |
88390 |
1181 |
0 |
0 |
T173 |
37305 |
374 |
0 |
0 |
T174 |
18368 |
24 |
0 |
0 |
T175 |
34598 |
945 |
0 |
0 |
T176 |
106423 |
401 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
4152 |
0 |
0 |
T106 |
2896 |
4 |
0 |
0 |
T146 |
90951 |
250 |
0 |
0 |
T170 |
8735 |
108 |
0 |
0 |
T171 |
7869 |
24 |
0 |
0 |
T172 |
88390 |
331 |
0 |
0 |
T173 |
37305 |
310 |
0 |
0 |
T174 |
18368 |
37 |
0 |
0 |
T175 |
34598 |
375 |
0 |
0 |
T176 |
106423 |
423 |
0 |
0 |
T178 |
10452 |
61 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
3857 |
0 |
0 |
T106 |
2896 |
8 |
0 |
0 |
T146 |
90951 |
266 |
0 |
0 |
T148 |
7535 |
9 |
0 |
0 |
T170 |
8735 |
49 |
0 |
0 |
T171 |
7869 |
12 |
0 |
0 |
T172 |
88390 |
341 |
0 |
0 |
T173 |
37305 |
398 |
0 |
0 |
T174 |
18368 |
58 |
0 |
0 |
T175 |
34598 |
233 |
0 |
0 |
T176 |
106423 |
396 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
4156 |
0 |
0 |
T106 |
2896 |
3 |
0 |
0 |
T146 |
90951 |
266 |
0 |
0 |
T148 |
7535 |
2 |
0 |
0 |
T170 |
8735 |
58 |
0 |
0 |
T171 |
7869 |
16 |
0 |
0 |
T172 |
88390 |
558 |
0 |
0 |
T173 |
37305 |
233 |
0 |
0 |
T174 |
18368 |
67 |
0 |
0 |
T175 |
34598 |
210 |
0 |
0 |
T176 |
106423 |
408 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
4097 |
0 |
0 |
T106 |
2896 |
4 |
0 |
0 |
T124 |
15544 |
9 |
0 |
0 |
T146 |
90951 |
178 |
0 |
0 |
T148 |
7535 |
106 |
0 |
0 |
T170 |
8735 |
57 |
0 |
0 |
T171 |
7869 |
3 |
0 |
0 |
T172 |
88390 |
459 |
0 |
0 |
T173 |
37305 |
285 |
0 |
0 |
T174 |
18368 |
38 |
0 |
0 |
T175 |
34598 |
381 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
3726 |
0 |
0 |
T106 |
2896 |
5 |
0 |
0 |
T146 |
90951 |
259 |
0 |
0 |
T148 |
7535 |
95 |
0 |
0 |
T170 |
8735 |
9 |
0 |
0 |
T171 |
7869 |
19 |
0 |
0 |
T172 |
88390 |
465 |
0 |
0 |
T173 |
37305 |
141 |
0 |
0 |
T174 |
18368 |
42 |
0 |
0 |
T175 |
34598 |
299 |
0 |
0 |
T176 |
106423 |
411 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
3502 |
0 |
0 |
T106 |
2896 |
7 |
0 |
0 |
T146 |
90951 |
217 |
0 |
0 |
T148 |
7535 |
109 |
0 |
0 |
T170 |
8735 |
111 |
0 |
0 |
T171 |
7869 |
42 |
0 |
0 |
T172 |
88390 |
407 |
0 |
0 |
T173 |
37305 |
120 |
0 |
0 |
T174 |
18368 |
8 |
0 |
0 |
T175 |
34598 |
343 |
0 |
0 |
T176 |
106423 |
356 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
4189 |
0 |
0 |
T106 |
2896 |
14 |
0 |
0 |
T146 |
90951 |
228 |
0 |
0 |
T148 |
7535 |
63 |
0 |
0 |
T170 |
8735 |
49 |
0 |
0 |
T171 |
7869 |
24 |
0 |
0 |
T172 |
88390 |
411 |
0 |
0 |
T173 |
37305 |
409 |
0 |
0 |
T174 |
18368 |
20 |
0 |
0 |
T175 |
34598 |
406 |
0 |
0 |
T176 |
106423 |
397 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
4215 |
0 |
0 |
T106 |
2896 |
2 |
0 |
0 |
T146 |
90951 |
254 |
0 |
0 |
T148 |
7535 |
108 |
0 |
0 |
T170 |
8735 |
53 |
0 |
0 |
T171 |
7869 |
3 |
0 |
0 |
T172 |
88390 |
394 |
0 |
0 |
T173 |
37305 |
270 |
0 |
0 |
T174 |
18368 |
17 |
0 |
0 |
T175 |
34598 |
287 |
0 |
0 |
T176 |
106423 |
365 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
3705 |
0 |
0 |
T106 |
2896 |
9 |
0 |
0 |
T129 |
19648 |
8 |
0 |
0 |
T146 |
90951 |
210 |
0 |
0 |
T148 |
7535 |
9 |
0 |
0 |
T170 |
8735 |
57 |
0 |
0 |
T171 |
7869 |
14 |
0 |
0 |
T172 |
88390 |
342 |
0 |
0 |
T173 |
37305 |
227 |
0 |
0 |
T174 |
18368 |
21 |
0 |
0 |
T175 |
34598 |
259 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
3553 |
0 |
0 |
T106 |
2896 |
5 |
0 |
0 |
T146 |
90951 |
229 |
0 |
0 |
T170 |
8735 |
11 |
0 |
0 |
T171 |
7869 |
8 |
0 |
0 |
T172 |
88390 |
378 |
0 |
0 |
T173 |
37305 |
310 |
0 |
0 |
T174 |
18368 |
48 |
0 |
0 |
T175 |
34598 |
164 |
0 |
0 |
T176 |
106423 |
410 |
0 |
0 |
T178 |
10452 |
10 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
3752 |
0 |
0 |
T106 |
2896 |
13 |
0 |
0 |
T146 |
90951 |
235 |
0 |
0 |
T148 |
7535 |
43 |
0 |
0 |
T170 |
8735 |
5 |
0 |
0 |
T171 |
7869 |
24 |
0 |
0 |
T172 |
88390 |
483 |
0 |
0 |
T173 |
37305 |
279 |
0 |
0 |
T174 |
18368 |
23 |
0 |
0 |
T175 |
34598 |
325 |
0 |
0 |
T176 |
106423 |
401 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
4004 |
0 |
0 |
T106 |
2896 |
4 |
0 |
0 |
T146 |
90951 |
213 |
0 |
0 |
T148 |
7535 |
96 |
0 |
0 |
T170 |
8735 |
71 |
0 |
0 |
T171 |
7869 |
23 |
0 |
0 |
T172 |
88390 |
604 |
0 |
0 |
T173 |
37305 |
202 |
0 |
0 |
T174 |
18368 |
19 |
0 |
0 |
T175 |
34598 |
353 |
0 |
0 |
T176 |
106423 |
398 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
3799 |
0 |
0 |
T106 |
2896 |
12 |
0 |
0 |
T146 |
90951 |
226 |
0 |
0 |
T148 |
7535 |
76 |
0 |
0 |
T170 |
8735 |
103 |
0 |
0 |
T171 |
7869 |
8 |
0 |
0 |
T172 |
88390 |
416 |
0 |
0 |
T173 |
37305 |
323 |
0 |
0 |
T174 |
18368 |
38 |
0 |
0 |
T175 |
34598 |
308 |
0 |
0 |
T176 |
106423 |
410 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
3920 |
0 |
0 |
T106 |
2896 |
12 |
0 |
0 |
T129 |
19648 |
3 |
0 |
0 |
T146 |
90951 |
228 |
0 |
0 |
T148 |
7535 |
42 |
0 |
0 |
T170 |
8735 |
7 |
0 |
0 |
T171 |
7869 |
18 |
0 |
0 |
T172 |
88390 |
407 |
0 |
0 |
T173 |
37305 |
493 |
0 |
0 |
T174 |
18368 |
31 |
0 |
0 |
T175 |
34598 |
195 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
3690 |
0 |
0 |
T106 |
2896 |
3 |
0 |
0 |
T146 |
90951 |
229 |
0 |
0 |
T148 |
7535 |
89 |
0 |
0 |
T170 |
8735 |
45 |
0 |
0 |
T171 |
7869 |
58 |
0 |
0 |
T172 |
88390 |
482 |
0 |
0 |
T173 |
37305 |
205 |
0 |
0 |
T174 |
18368 |
42 |
0 |
0 |
T175 |
34598 |
180 |
0 |
0 |
T176 |
106423 |
434 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
3614 |
0 |
0 |
T106 |
2896 |
1 |
0 |
0 |
T146 |
90951 |
201 |
0 |
0 |
T148 |
7535 |
41 |
0 |
0 |
T170 |
8735 |
8 |
0 |
0 |
T171 |
7869 |
18 |
0 |
0 |
T172 |
88390 |
332 |
0 |
0 |
T173 |
37305 |
147 |
0 |
0 |
T174 |
18368 |
27 |
0 |
0 |
T175 |
34598 |
332 |
0 |
0 |
T176 |
106423 |
439 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
3986 |
0 |
0 |
T106 |
2896 |
8 |
0 |
0 |
T146 |
90951 |
250 |
0 |
0 |
T148 |
7535 |
52 |
0 |
0 |
T170 |
8735 |
74 |
0 |
0 |
T171 |
7869 |
35 |
0 |
0 |
T172 |
88390 |
427 |
0 |
0 |
T173 |
37305 |
281 |
0 |
0 |
T174 |
18368 |
55 |
0 |
0 |
T175 |
34598 |
267 |
0 |
0 |
T176 |
106423 |
449 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
3683 |
0 |
0 |
T106 |
2896 |
10 |
0 |
0 |
T146 |
90951 |
207 |
0 |
0 |
T148 |
7535 |
59 |
0 |
0 |
T170 |
8735 |
5 |
0 |
0 |
T171 |
7869 |
26 |
0 |
0 |
T172 |
88390 |
344 |
0 |
0 |
T173 |
37305 |
364 |
0 |
0 |
T174 |
18368 |
42 |
0 |
0 |
T175 |
34598 |
320 |
0 |
0 |
T176 |
106423 |
378 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
3766 |
0 |
0 |
T106 |
2896 |
2 |
0 |
0 |
T146 |
90951 |
229 |
0 |
0 |
T148 |
7535 |
10 |
0 |
0 |
T170 |
8735 |
73 |
0 |
0 |
T171 |
7869 |
7 |
0 |
0 |
T172 |
88390 |
427 |
0 |
0 |
T173 |
37305 |
329 |
0 |
0 |
T174 |
18368 |
54 |
0 |
0 |
T175 |
34598 |
241 |
0 |
0 |
T176 |
106423 |
430 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
4134 |
0 |
0 |
T106 |
2896 |
1 |
0 |
0 |
T129 |
19648 |
6 |
0 |
0 |
T146 |
90951 |
261 |
0 |
0 |
T148 |
7535 |
66 |
0 |
0 |
T170 |
8735 |
15 |
0 |
0 |
T171 |
7869 |
25 |
0 |
0 |
T172 |
88390 |
563 |
0 |
0 |
T173 |
37305 |
273 |
0 |
0 |
T174 |
18368 |
42 |
0 |
0 |
T175 |
34598 |
142 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
3627 |
0 |
0 |
T124 |
15544 |
4 |
0 |
0 |
T146 |
90951 |
228 |
0 |
0 |
T148 |
7535 |
2 |
0 |
0 |
T170 |
8735 |
54 |
0 |
0 |
T171 |
7869 |
57 |
0 |
0 |
T172 |
88390 |
274 |
0 |
0 |
T173 |
37305 |
387 |
0 |
0 |
T174 |
18368 |
9 |
0 |
0 |
T175 |
34598 |
215 |
0 |
0 |
T176 |
106423 |
390 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
3583 |
0 |
0 |
T106 |
2896 |
9 |
0 |
0 |
T146 |
90951 |
194 |
0 |
0 |
T148 |
7535 |
5 |
0 |
0 |
T170 |
8735 |
52 |
0 |
0 |
T171 |
7869 |
26 |
0 |
0 |
T172 |
88390 |
301 |
0 |
0 |
T173 |
37305 |
277 |
0 |
0 |
T174 |
18368 |
15 |
0 |
0 |
T175 |
34598 |
170 |
0 |
0 |
T176 |
106423 |
423 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
3431 |
0 |
0 |
T106 |
2896 |
5 |
0 |
0 |
T129 |
19648 |
3 |
0 |
0 |
T146 |
90951 |
218 |
0 |
0 |
T148 |
7535 |
43 |
0 |
0 |
T170 |
8735 |
63 |
0 |
0 |
T171 |
7869 |
23 |
0 |
0 |
T172 |
88390 |
367 |
0 |
0 |
T173 |
37305 |
301 |
0 |
0 |
T174 |
18368 |
47 |
0 |
0 |
T175 |
34598 |
284 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
3854 |
0 |
0 |
T106 |
2896 |
8 |
0 |
0 |
T126 |
20869 |
5 |
0 |
0 |
T146 |
90951 |
203 |
0 |
0 |
T148 |
7535 |
50 |
0 |
0 |
T170 |
8735 |
114 |
0 |
0 |
T172 |
88390 |
400 |
0 |
0 |
T173 |
37305 |
306 |
0 |
0 |
T174 |
18368 |
39 |
0 |
0 |
T175 |
34598 |
292 |
0 |
0 |
T176 |
106423 |
411 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
1687 |
0 |
0 |
T106 |
2896 |
6 |
0 |
0 |
T146 |
90951 |
218 |
0 |
0 |
T148 |
7535 |
7 |
0 |
0 |
T170 |
8735 |
16 |
0 |
0 |
T171 |
7869 |
20 |
0 |
0 |
T172 |
88390 |
76 |
0 |
0 |
T173 |
37305 |
31 |
0 |
0 |
T174 |
18368 |
51 |
0 |
0 |
T175 |
34598 |
64 |
0 |
0 |
T176 |
106423 |
353 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
1603 |
0 |
0 |
T106 |
2896 |
5 |
0 |
0 |
T146 |
90951 |
211 |
0 |
0 |
T148 |
7535 |
11 |
0 |
0 |
T170 |
8735 |
4 |
0 |
0 |
T171 |
7869 |
9 |
0 |
0 |
T172 |
88390 |
107 |
0 |
0 |
T173 |
37305 |
55 |
0 |
0 |
T174 |
18368 |
42 |
0 |
0 |
T175 |
34598 |
42 |
0 |
0 |
T176 |
106423 |
365 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
1750 |
0 |
0 |
T106 |
2896 |
13 |
0 |
0 |
T146 |
90951 |
230 |
0 |
0 |
T148 |
7535 |
16 |
0 |
0 |
T170 |
8735 |
15 |
0 |
0 |
T171 |
7869 |
17 |
0 |
0 |
T172 |
88390 |
96 |
0 |
0 |
T173 |
37305 |
47 |
0 |
0 |
T174 |
18368 |
27 |
0 |
0 |
T175 |
34598 |
51 |
0 |
0 |
T176 |
106423 |
432 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
1811 |
0 |
0 |
T106 |
2896 |
6 |
0 |
0 |
T146 |
90951 |
223 |
0 |
0 |
T148 |
7535 |
11 |
0 |
0 |
T170 |
8735 |
17 |
0 |
0 |
T171 |
7869 |
35 |
0 |
0 |
T172 |
88390 |
101 |
0 |
0 |
T173 |
37305 |
72 |
0 |
0 |
T174 |
18368 |
36 |
0 |
0 |
T175 |
34598 |
54 |
0 |
0 |
T176 |
106423 |
406 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
2048 |
0 |
0 |
T106 |
2896 |
6 |
0 |
0 |
T146 |
90951 |
209 |
0 |
0 |
T148 |
7535 |
29 |
0 |
0 |
T170 |
8735 |
15 |
0 |
0 |
T171 |
7869 |
22 |
0 |
0 |
T172 |
88390 |
132 |
0 |
0 |
T173 |
37305 |
67 |
0 |
0 |
T174 |
18368 |
29 |
0 |
0 |
T175 |
34598 |
116 |
0 |
0 |
T176 |
106423 |
397 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
3637 |
0 |
0 |
T82 |
0 |
11 |
0 |
0 |
T162 |
0 |
6 |
0 |
0 |
T179 |
172389 |
23 |
0 |
0 |
T180 |
0 |
23 |
0 |
0 |
T181 |
0 |
37 |
0 |
0 |
T182 |
0 |
25 |
0 |
0 |
T183 |
0 |
13 |
0 |
0 |
T184 |
0 |
15 |
0 |
0 |
T185 |
0 |
44 |
0 |
0 |
T186 |
0 |
8 |
0 |
0 |
T187 |
330873 |
0 |
0 |
0 |
T188 |
375058 |
0 |
0 |
0 |
T189 |
1397 |
0 |
0 |
0 |
T190 |
179335 |
0 |
0 |
0 |
T191 |
1255 |
0 |
0 |
0 |
T192 |
83533 |
0 |
0 |
0 |
T193 |
625279 |
0 |
0 |
0 |
T194 |
547671 |
0 |
0 |
0 |
T195 |
389248 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
1845 |
0 |
0 |
T106 |
2896 |
19 |
0 |
0 |
T146 |
90951 |
246 |
0 |
0 |
T148 |
7535 |
8 |
0 |
0 |
T170 |
8735 |
16 |
0 |
0 |
T171 |
7869 |
34 |
0 |
0 |
T172 |
88390 |
102 |
0 |
0 |
T173 |
37305 |
44 |
0 |
0 |
T174 |
18368 |
29 |
0 |
0 |
T175 |
34598 |
60 |
0 |
0 |
T176 |
106423 |
469 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
1770 |
0 |
0 |
T106 |
2896 |
3 |
0 |
0 |
T146 |
90951 |
228 |
0 |
0 |
T148 |
7535 |
7 |
0 |
0 |
T170 |
8735 |
7 |
0 |
0 |
T171 |
7869 |
45 |
0 |
0 |
T172 |
88390 |
75 |
0 |
0 |
T173 |
37305 |
68 |
0 |
0 |
T174 |
18368 |
12 |
0 |
0 |
T175 |
34598 |
92 |
0 |
0 |
T176 |
106423 |
455 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
1567 |
0 |
0 |
T106 |
2896 |
2 |
0 |
0 |
T129 |
19648 |
6 |
0 |
0 |
T146 |
90951 |
223 |
0 |
0 |
T148 |
7535 |
8 |
0 |
0 |
T170 |
8735 |
8 |
0 |
0 |
T171 |
7869 |
23 |
0 |
0 |
T172 |
88390 |
78 |
0 |
0 |
T173 |
37305 |
26 |
0 |
0 |
T174 |
18368 |
23 |
0 |
0 |
T175 |
34598 |
45 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
1618 |
0 |
0 |
T106 |
2896 |
12 |
0 |
0 |
T146 |
90951 |
267 |
0 |
0 |
T148 |
7535 |
6 |
0 |
0 |
T170 |
8735 |
11 |
0 |
0 |
T171 |
7869 |
21 |
0 |
0 |
T172 |
88390 |
49 |
0 |
0 |
T173 |
37305 |
43 |
0 |
0 |
T174 |
18368 |
29 |
0 |
0 |
T175 |
34598 |
41 |
0 |
0 |
T176 |
106423 |
396 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
1440 |
0 |
0 |
T106 |
2896 |
2 |
0 |
0 |
T146 |
90951 |
191 |
0 |
0 |
T148 |
7535 |
2 |
0 |
0 |
T170 |
8735 |
10 |
0 |
0 |
T171 |
7869 |
22 |
0 |
0 |
T172 |
88390 |
67 |
0 |
0 |
T173 |
37305 |
45 |
0 |
0 |
T174 |
18368 |
53 |
0 |
0 |
T175 |
34598 |
26 |
0 |
0 |
T176 |
106423 |
394 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
1604 |
0 |
0 |
T106 |
2896 |
10 |
0 |
0 |
T146 |
90951 |
255 |
0 |
0 |
T148 |
7535 |
3 |
0 |
0 |
T170 |
8735 |
5 |
0 |
0 |
T171 |
7869 |
28 |
0 |
0 |
T172 |
88390 |
47 |
0 |
0 |
T173 |
37305 |
22 |
0 |
0 |
T174 |
18368 |
19 |
0 |
0 |
T175 |
34598 |
41 |
0 |
0 |
T176 |
106423 |
420 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
2122 |
0 |
0 |
T126 |
20869 |
6 |
0 |
0 |
T146 |
90951 |
251 |
0 |
0 |
T148 |
7535 |
16 |
0 |
0 |
T170 |
8735 |
30 |
0 |
0 |
T171 |
7869 |
7 |
0 |
0 |
T172 |
88390 |
131 |
0 |
0 |
T173 |
37305 |
73 |
0 |
0 |
T174 |
18368 |
64 |
0 |
0 |
T175 |
34598 |
57 |
0 |
0 |
T176 |
106423 |
462 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
1553 |
0 |
0 |
T106 |
2896 |
4 |
0 |
0 |
T146 |
90951 |
201 |
0 |
0 |
T148 |
7535 |
2 |
0 |
0 |
T170 |
8735 |
12 |
0 |
0 |
T171 |
7869 |
21 |
0 |
0 |
T172 |
88390 |
62 |
0 |
0 |
T173 |
37305 |
36 |
0 |
0 |
T174 |
18368 |
13 |
0 |
0 |
T175 |
34598 |
35 |
0 |
0 |
T176 |
106423 |
404 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
2341 |
0 |
0 |
T106 |
2896 |
4 |
0 |
0 |
T129 |
19648 |
5 |
0 |
0 |
T146 |
90951 |
211 |
0 |
0 |
T148 |
7535 |
35 |
0 |
0 |
T170 |
8735 |
27 |
0 |
0 |
T171 |
7869 |
19 |
0 |
0 |
T172 |
88390 |
204 |
0 |
0 |
T173 |
37305 |
124 |
0 |
0 |
T174 |
18368 |
28 |
0 |
0 |
T175 |
34598 |
130 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
1729 |
0 |
0 |
T106 |
2896 |
5 |
0 |
0 |
T146 |
90951 |
211 |
0 |
0 |
T148 |
7535 |
15 |
0 |
0 |
T170 |
8735 |
10 |
0 |
0 |
T171 |
7869 |
33 |
0 |
0 |
T172 |
88390 |
95 |
0 |
0 |
T173 |
37305 |
45 |
0 |
0 |
T174 |
18368 |
50 |
0 |
0 |
T175 |
34598 |
51 |
0 |
0 |
T176 |
106423 |
400 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
1638 |
0 |
0 |
T106 |
2896 |
7 |
0 |
0 |
T146 |
90951 |
275 |
0 |
0 |
T148 |
7535 |
4 |
0 |
0 |
T170 |
8735 |
2 |
0 |
0 |
T171 |
7869 |
28 |
0 |
0 |
T172 |
88390 |
70 |
0 |
0 |
T173 |
37305 |
43 |
0 |
0 |
T174 |
18368 |
53 |
0 |
0 |
T175 |
34598 |
38 |
0 |
0 |
T176 |
106423 |
426 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
1560 |
0 |
0 |
T106 |
2896 |
8 |
0 |
0 |
T146 |
90951 |
260 |
0 |
0 |
T148 |
7535 |
12 |
0 |
0 |
T170 |
8735 |
3 |
0 |
0 |
T171 |
7869 |
7 |
0 |
0 |
T172 |
88390 |
75 |
0 |
0 |
T173 |
37305 |
34 |
0 |
0 |
T174 |
18368 |
40 |
0 |
0 |
T175 |
34598 |
35 |
0 |
0 |
T176 |
106423 |
389 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
1658 |
0 |
0 |
T106 |
2896 |
6 |
0 |
0 |
T146 |
90951 |
212 |
0 |
0 |
T148 |
7535 |
8 |
0 |
0 |
T170 |
8735 |
5 |
0 |
0 |
T171 |
7869 |
4 |
0 |
0 |
T172 |
88390 |
78 |
0 |
0 |
T173 |
37305 |
47 |
0 |
0 |
T174 |
18368 |
40 |
0 |
0 |
T175 |
34598 |
42 |
0 |
0 |
T176 |
106423 |
444 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
1457 |
0 |
0 |
T106 |
2896 |
5 |
0 |
0 |
T126 |
20869 |
4 |
0 |
0 |
T146 |
90951 |
171 |
0 |
0 |
T148 |
7535 |
6 |
0 |
0 |
T170 |
8735 |
1 |
0 |
0 |
T171 |
7869 |
12 |
0 |
0 |
T172 |
88390 |
48 |
0 |
0 |
T173 |
37305 |
30 |
0 |
0 |
T174 |
18368 |
49 |
0 |
0 |
T175 |
34598 |
28 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
1442 |
0 |
0 |
T106 |
2896 |
8 |
0 |
0 |
T146 |
90951 |
225 |
0 |
0 |
T148 |
7535 |
9 |
0 |
0 |
T170 |
8735 |
12 |
0 |
0 |
T171 |
7869 |
43 |
0 |
0 |
T172 |
88390 |
65 |
0 |
0 |
T173 |
37305 |
41 |
0 |
0 |
T174 |
18368 |
32 |
0 |
0 |
T175 |
34598 |
34 |
0 |
0 |
T176 |
106423 |
305 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
499330282 |
1521 |
0 |
0 |
T106 |
2896 |
10 |
0 |
0 |
T146 |
90951 |
187 |
0 |
0 |
T148 |
7535 |
6 |
0 |
0 |
T170 |
8735 |
12 |
0 |
0 |
T171 |
7869 |
6 |
0 |
0 |
T172 |
88390 |
78 |
0 |
0 |
T173 |
37305 |
36 |
0 |
0 |
T174 |
18368 |
20 |
0 |
0 |
T175 |
34598 |
42 |
0 |
0 |
T176 |
106423 |
389 |
0 |
0 |