Line Coverage for Module :
prim_ram_1r1w_async_adv
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 28 | 28 | 100.00 |
| ALWAYS | 118 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 125 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 129 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
| ALWAYS | 180 | 8 | 8 | 100.00 |
| CONT_ASSIGN | 203 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 234 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 235 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 237 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 239 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 240 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 258 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 259 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 261 | 1 | 1 | 100.00 |
117 always_ff @(posedge clk_b_i or negedge rst_b_ni) begin
118 1/1 if (!rst_b_ni) begin
Tests: T1 T2 T3
119 1/1 b_rvalid_sram_q <= 1'b0;
Tests: T1 T2 T3
120 end else begin
121 1/1 b_rvalid_sram_q <= b_req_q;
Tests: T1 T2 T3
122 end
123 end
124
125 1/1 assign a_req_d = a_req_i;
Tests: T1 T2 T3
126 1/1 assign a_addr_d = a_addr_i;
Tests: T1 T2 T3
127
128 1/1 assign b_req_d = b_req_i;
Tests: T1 T2 T3
129 1/1 assign b_addr_d = b_addr_i;
Tests: T1 T2 T3
130 1/1 assign b_rvalid_o = b_rvalid_q;
Tests: T1 T2 T3
131 1/1 assign b_rdata_o = b_rdata_q;
Tests: T3 T5 T7
132 1/1 assign b_rerror_o = b_rerror_q;
Tests: T1 T2 T3
133
134 /////////////////////////////
135 // ECC / Parity Generation //
136 /////////////////////////////
137
138 if (EnableParity == 0 && EnableECC) begin : gen_secded
139
140 // check supported widths
141 `ASSERT_INIT(SecDecWidth_A, Width inside {32})
142
143 // the wmask is constantly set to 1 in this case
144 `ASSERT(OnlyWordWritePossibleWithEccPortA_A, a_req_i |->
145 a_wmask_i == {Width{1'b1}}, clk_a_i, rst_a_ni)
146
147 assign a_wmask_d = {TotalWidth{1'b1}};
148
149 if (Width == 32) begin : gen_secded_39_32
150 if (HammingECC) begin : gen_hamming
151 prim_secded_inv_hamming_39_32_enc u_enc_a (
152 .data_i(a_wdata_i),
153 .data_o(a_wdata_d)
154 );
155 prim_secded_inv_hamming_39_32_dec u_dec_b (
156 .data_i (b_rdata_sram),
157 .data_o (b_rdata_d[0+:Width]),
158 .syndrome_o ( ),
159 .err_o (b_rerror_d)
160 );
161 end else begin : gen_hsiao
162 prim_secded_inv_39_32_enc u_enc_a (
163 .data_i(a_wdata_i),
164 .data_o(a_wdata_d)
165 );
166 prim_secded_inv_39_32_dec u_dec_b (
167 .data_i (b_rdata_sram),
168 .data_o (b_rdata_d[0+:Width]),
169 .syndrome_o ( ),
170 .err_o (b_rerror_d)
171 );
172 end
173 end
174 end else if (EnableParity) begin : gen_byte_parity
175
176 `ASSERT_INIT(ParityNeedsByteWriteMask_A, DataBitsPerMask == 8)
177 `ASSERT_INIT(WidthNeedsToBeByteAligned_A, Width % 8 == 0)
178
179 always_comb begin : p_parity
180 1/1 b_rerror_d = '0;
Tests: T1 T2 T3
181 1/1 for (int i = 0; i < Width/8; i ++) begin
Tests: T1 T2 T3
182 // Data mapping. We have to make 8+1 = 9 bit groups
183 // that have the same write enable such that FPGA tools
184 // can map this correctly to BRAM resources.
185 1/1 a_wmask_d[i*9 +: 8] = a_wmask_i[i*8 +: 8];
Tests: T1 T2 T3
186 1/1 a_wdata_d[i*9 +: 8] = a_wdata_i[i*8 +: 8];
Tests: T1 T2 T3
187 1/1 b_rdata_d[i*8 +: 8] = b_rdata_sram[i*9 +: 8];
Tests: T1 T2 T3
188
189 // parity generation (odd parity)
190 1/1 a_wdata_d[i*9 + 8] = ~(^a_wdata_i[i*8 +: 8]);
Tests: T1 T2 T3
191 1/1 a_wmask_d[i*9 + 8] = &a_wmask_i[i*8 +: 8];
Tests: T1 T2 T3
192 // parity decoding (errors are always uncorrectable)
193 1/1 b_rerror_d[1] |= ~(^{b_rdata_sram[i*9 +: 8], b_rdata_sram[i*9 + 8]});
Tests: T1 T2 T3
194 end
195 end
196 end else begin : gen_nosecded_noparity
197 assign a_wmask_d = a_wmask_i;
198 assign a_wdata_d = a_wdata_i;
199 assign b_rdata_d = b_rdata_sram[0+:Width];
200 assign b_rerror_d = '0;
201 end
202
203 1/1 assign b_rvalid_d = b_rvalid_sram_q;
Tests: T1 T2 T3
204
205 /////////////////////////////////////
206 // Input/Output Pipeline Registers //
207 /////////////////////////////////////
208
209 if (EnableInputPipeline) begin : gen_regslice_input
210 // Put the register slices between ECC encoding to SRAM port
211 always_ff @(posedge clk_a_i or negedge rst_a_ni) begin
212 if (!rst_a_ni) begin
213 a_req_q <= '0;
214 a_addr_q <= '0;
215 a_wdata_q <= '0;
216 a_wmask_q <= '0;
217 end else begin
218 a_req_q <= a_req_d;
219 a_addr_q <= a_addr_d;
220 a_wdata_q <= a_wdata_d;
221 a_wmask_q <= a_wmask_d;
222 end
223 end
224 always_ff @(posedge clk_b_i or negedge rst_b_ni) begin
225 if (!rst_b_ni) begin
226 b_req_q <= '0;
227 b_addr_q <= '0;
228 end else begin
229 b_req_q <= b_req_d;
230 b_addr_q <= b_addr_d;
231 end
232 end
233 end else begin : gen_dirconnect_input
234 1/1 assign a_req_q = a_req_d;
Tests: T1 T2 T3
235 1/1 assign a_addr_q = a_addr_d;
Tests: T1 T2 T3
236 1/1 assign a_wdata_q = a_wdata_d;
Tests: T1 T2 T3
237 1/1 assign a_wmask_q = a_wmask_d;
Tests: T1 T2 T3
238
239 1/1 assign b_req_q = b_req_d;
Tests: T1 T2 T3
240 1/1 assign b_addr_q = b_addr_d;
Tests: T1 T2 T3
241 end
242
243 if (EnableOutputPipeline) begin : gen_regslice_output
244 // Put the register slices between ECC decoding to output
245 always_ff @(posedge clk_b_i or negedge rst_b_ni) begin
246 if (!rst_b_ni) begin
247 b_rvalid_q <= '0;
248 b_rdata_q <= '0;
249 b_rerror_q <= '0;
250 end else begin
251 b_rvalid_q <= b_rvalid_d;
252 b_rdata_q <= b_rdata_d;
253 // tie to zero if the read data is not valid
254 b_rerror_q <= b_rerror_d & {2{b_rvalid_d}};
255 end
256 end
257 end else begin : gen_dirconnect_output
258 1/1 assign b_rvalid_q = b_rvalid_d;
Tests: T1 T2 T3
259 1/1 assign b_rdata_q = b_rdata_d;
Tests: T3 T5 T7
260 // tie to zero if the read data is not valid
261 1/1 assign b_rerror_q = b_rerror_d & {2{b_rvalid_d}};
Tests: T1 T2 T3
Branch Coverage for Module :
prim_ram_1r1w_async_adv
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
118 |
2 |
2 |
100.00 |
118 if (!rst_b_ni) begin
-1-
119 b_rvalid_sram_q <= 1'b0;
==>
120 end else begin
121 b_rvalid_sram_q <= b_req_q;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_ram_1r1w_async_adv
Assertion Details
CannotHaveEccAndParity_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1912 |
1912 |
0 |
0 |
| T1 |
2 |
2 |
0 |
0 |
| T2 |
2 |
2 |
0 |
0 |
| T3 |
2 |
2 |
0 |
0 |
| T4 |
2 |
2 |
0 |
0 |
| T5 |
2 |
2 |
0 |
0 |
| T6 |
2 |
2 |
0 |
0 |
| T7 |
2 |
2 |
0 |
0 |
| T8 |
2 |
2 |
0 |
0 |
| T9 |
2 |
2 |
0 |
0 |
| T10 |
2 |
2 |
0 |
0 |
gen_byte_parity.ParityNeedsByteWriteMask_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1912 |
1912 |
0 |
0 |
| T1 |
2 |
2 |
0 |
0 |
| T2 |
2 |
2 |
0 |
0 |
| T3 |
2 |
2 |
0 |
0 |
| T4 |
2 |
2 |
0 |
0 |
| T5 |
2 |
2 |
0 |
0 |
| T6 |
2 |
2 |
0 |
0 |
| T7 |
2 |
2 |
0 |
0 |
| T8 |
2 |
2 |
0 |
0 |
| T9 |
2 |
2 |
0 |
0 |
| T10 |
2 |
2 |
0 |
0 |
gen_byte_parity.WidthNeedsToBeByteAligned_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1912 |
1912 |
0 |
0 |
| T1 |
2 |
2 |
0 |
0 |
| T2 |
2 |
2 |
0 |
0 |
| T3 |
2 |
2 |
0 |
0 |
| T4 |
2 |
2 |
0 |
0 |
| T5 |
2 |
2 |
0 |
0 |
| T6 |
2 |
2 |
0 |
0 |
| T7 |
2 |
2 |
0 |
0 |
| T8 |
2 |
2 |
0 |
0 |
| T9 |
2 |
2 |
0 |
0 |
| T10 |
2 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 28 | 28 | 100.00 |
| ALWAYS | 118 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 125 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 129 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
| ALWAYS | 180 | 8 | 8 | 100.00 |
| CONT_ASSIGN | 203 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 234 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 235 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 237 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 239 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 240 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 258 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 259 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 261 | 1 | 1 | 100.00 |
117 always_ff @(posedge clk_b_i or negedge rst_b_ni) begin
118 1/1 if (!rst_b_ni) begin
Tests: T1 T2 T3
119 1/1 b_rvalid_sram_q <= 1'b0;
Tests: T1 T2 T3
120 end else begin
121 1/1 b_rvalid_sram_q <= b_req_q;
Tests: T3 T4 T5
122 end
123 end
124
125 1/1 assign a_req_d = a_req_i;
Tests: T1 T2 T3
126 1/1 assign a_addr_d = a_addr_i;
Tests: T1 T2 T3
127
128 1/1 assign b_req_d = b_req_i;
Tests: T1 T2 T3
129 1/1 assign b_addr_d = b_addr_i;
Tests: T1 T2 T3
130 1/1 assign b_rvalid_o = b_rvalid_q;
Tests: T1 T2 T3
131 1/1 assign b_rdata_o = b_rdata_q;
Tests: T3 T5 T7
132 1/1 assign b_rerror_o = b_rerror_q;
Tests: T1 T2 T3
133
134 /////////////////////////////
135 // ECC / Parity Generation //
136 /////////////////////////////
137
138 if (EnableParity == 0 && EnableECC) begin : gen_secded
139
140 // check supported widths
141 `ASSERT_INIT(SecDecWidth_A, Width inside {32})
142
143 // the wmask is constantly set to 1 in this case
144 `ASSERT(OnlyWordWritePossibleWithEccPortA_A, a_req_i |->
145 a_wmask_i == {Width{1'b1}}, clk_a_i, rst_a_ni)
146
147 assign a_wmask_d = {TotalWidth{1'b1}};
148
149 if (Width == 32) begin : gen_secded_39_32
150 if (HammingECC) begin : gen_hamming
151 prim_secded_inv_hamming_39_32_enc u_enc_a (
152 .data_i(a_wdata_i),
153 .data_o(a_wdata_d)
154 );
155 prim_secded_inv_hamming_39_32_dec u_dec_b (
156 .data_i (b_rdata_sram),
157 .data_o (b_rdata_d[0+:Width]),
158 .syndrome_o ( ),
159 .err_o (b_rerror_d)
160 );
161 end else begin : gen_hsiao
162 prim_secded_inv_39_32_enc u_enc_a (
163 .data_i(a_wdata_i),
164 .data_o(a_wdata_d)
165 );
166 prim_secded_inv_39_32_dec u_dec_b (
167 .data_i (b_rdata_sram),
168 .data_o (b_rdata_d[0+:Width]),
169 .syndrome_o ( ),
170 .err_o (b_rerror_d)
171 );
172 end
173 end
174 end else if (EnableParity) begin : gen_byte_parity
175
176 `ASSERT_INIT(ParityNeedsByteWriteMask_A, DataBitsPerMask == 8)
177 `ASSERT_INIT(WidthNeedsToBeByteAligned_A, Width % 8 == 0)
178
179 always_comb begin : p_parity
180 1/1 b_rerror_d = '0;
Tests: T1 T2 T3
181 1/1 for (int i = 0; i < Width/8; i ++) begin
Tests: T1 T2 T3
182 // Data mapping. We have to make 8+1 = 9 bit groups
183 // that have the same write enable such that FPGA tools
184 // can map this correctly to BRAM resources.
185 1/1 a_wmask_d[i*9 +: 8] = a_wmask_i[i*8 +: 8];
Tests: T1 T2 T3
186 1/1 a_wdata_d[i*9 +: 8] = a_wdata_i[i*8 +: 8];
Tests: T1 T2 T3
187 1/1 b_rdata_d[i*8 +: 8] = b_rdata_sram[i*9 +: 8];
Tests: T1 T2 T3
188
189 // parity generation (odd parity)
190 1/1 a_wdata_d[i*9 + 8] = ~(^a_wdata_i[i*8 +: 8]);
Tests: T1 T2 T3
191 1/1 a_wmask_d[i*9 + 8] = &a_wmask_i[i*8 +: 8];
Tests: T1 T2 T3
192 // parity decoding (errors are always uncorrectable)
193 1/1 b_rerror_d[1] |= ~(^{b_rdata_sram[i*9 +: 8], b_rdata_sram[i*9 + 8]});
Tests: T1 T2 T3
194 end
195 end
196 end else begin : gen_nosecded_noparity
197 assign a_wmask_d = a_wmask_i;
198 assign a_wdata_d = a_wdata_i;
199 assign b_rdata_d = b_rdata_sram[0+:Width];
200 assign b_rerror_d = '0;
201 end
202
203 1/1 assign b_rvalid_d = b_rvalid_sram_q;
Tests: T1 T2 T3
204
205 /////////////////////////////////////
206 // Input/Output Pipeline Registers //
207 /////////////////////////////////////
208
209 if (EnableInputPipeline) begin : gen_regslice_input
210 // Put the register slices between ECC encoding to SRAM port
211 always_ff @(posedge clk_a_i or negedge rst_a_ni) begin
212 if (!rst_a_ni) begin
213 a_req_q <= '0;
214 a_addr_q <= '0;
215 a_wdata_q <= '0;
216 a_wmask_q <= '0;
217 end else begin
218 a_req_q <= a_req_d;
219 a_addr_q <= a_addr_d;
220 a_wdata_q <= a_wdata_d;
221 a_wmask_q <= a_wmask_d;
222 end
223 end
224 always_ff @(posedge clk_b_i or negedge rst_b_ni) begin
225 if (!rst_b_ni) begin
226 b_req_q <= '0;
227 b_addr_q <= '0;
228 end else begin
229 b_req_q <= b_req_d;
230 b_addr_q <= b_addr_d;
231 end
232 end
233 end else begin : gen_dirconnect_input
234 1/1 assign a_req_q = a_req_d;
Tests: T1 T2 T3
235 1/1 assign a_addr_q = a_addr_d;
Tests: T1 T2 T3
236 1/1 assign a_wdata_q = a_wdata_d;
Tests: T1 T2 T3
237 1/1 assign a_wmask_q = a_wmask_d;
Tests: T1 T2 T3
238
239 1/1 assign b_req_q = b_req_d;
Tests: T1 T2 T3
240 1/1 assign b_addr_q = b_addr_d;
Tests: T1 T2 T3
241 end
242
243 if (EnableOutputPipeline) begin : gen_regslice_output
244 // Put the register slices between ECC decoding to output
245 always_ff @(posedge clk_b_i or negedge rst_b_ni) begin
246 if (!rst_b_ni) begin
247 b_rvalid_q <= '0;
248 b_rdata_q <= '0;
249 b_rerror_q <= '0;
250 end else begin
251 b_rvalid_q <= b_rvalid_d;
252 b_rdata_q <= b_rdata_d;
253 // tie to zero if the read data is not valid
254 b_rerror_q <= b_rerror_d & {2{b_rvalid_d}};
255 end
256 end
257 end else begin : gen_dirconnect_output
258 1/1 assign b_rvalid_q = b_rvalid_d;
Tests: T1 T2 T3
259 1/1 assign b_rdata_q = b_rdata_d;
Tests: T3 T5 T7
260 // tie to zero if the read data is not valid
261 1/1 assign b_rerror_q = b_rerror_d & {2{b_rvalid_d}};
Tests: T1 T2 T3
Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
118 |
2 |
2 |
100.00 |
118 if (!rst_b_ni) begin
-1-
119 b_rvalid_sram_q <= 1'b0;
==>
120 end else begin
121 b_rvalid_sram_q <= b_req_q;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T3,T4,T5 |
Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem
Assertion Details
CannotHaveEccAndParity_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
956 |
956 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
gen_byte_parity.ParityNeedsByteWriteMask_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
956 |
956 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
gen_byte_parity.WidthNeedsToBeByteAligned_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
956 |
956 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 28 | 28 | 100.00 |
| ALWAYS | 118 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 125 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 129 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
| ALWAYS | 180 | 8 | 8 | 100.00 |
| CONT_ASSIGN | 203 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 234 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 235 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 237 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 239 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 240 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 258 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 259 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 261 | 1 | 1 | 100.00 |
117 always_ff @(posedge clk_b_i or negedge rst_b_ni) begin
118 1/1 if (!rst_b_ni) begin
Tests: T1 T2 T3
119 1/1 b_rvalid_sram_q <= 1'b0;
Tests: T1 T2 T3
120 end else begin
121 1/1 b_rvalid_sram_q <= b_req_q;
Tests: T1 T2 T3
122 end
123 end
124
125 1/1 assign a_req_d = a_req_i;
Tests: T1 T2 T3
126 1/1 assign a_addr_d = a_addr_i;
Tests: T1 T2 T3
127
128 1/1 assign b_req_d = b_req_i;
Tests: T1 T2 T3
129 1/1 assign b_addr_d = b_addr_i;
Tests: T1 T2 T3
130 1/1 assign b_rvalid_o = b_rvalid_q;
Tests: T1 T2 T3
131 1/1 assign b_rdata_o = b_rdata_q;
Tests: T12 T13 T29
132 1/1 assign b_rerror_o = b_rerror_q;
Tests: T1 T2 T3
133
134 /////////////////////////////
135 // ECC / Parity Generation //
136 /////////////////////////////
137
138 if (EnableParity == 0 && EnableECC) begin : gen_secded
139
140 // check supported widths
141 `ASSERT_INIT(SecDecWidth_A, Width inside {32})
142
143 // the wmask is constantly set to 1 in this case
144 `ASSERT(OnlyWordWritePossibleWithEccPortA_A, a_req_i |->
145 a_wmask_i == {Width{1'b1}}, clk_a_i, rst_a_ni)
146
147 assign a_wmask_d = {TotalWidth{1'b1}};
148
149 if (Width == 32) begin : gen_secded_39_32
150 if (HammingECC) begin : gen_hamming
151 prim_secded_inv_hamming_39_32_enc u_enc_a (
152 .data_i(a_wdata_i),
153 .data_o(a_wdata_d)
154 );
155 prim_secded_inv_hamming_39_32_dec u_dec_b (
156 .data_i (b_rdata_sram),
157 .data_o (b_rdata_d[0+:Width]),
158 .syndrome_o ( ),
159 .err_o (b_rerror_d)
160 );
161 end else begin : gen_hsiao
162 prim_secded_inv_39_32_enc u_enc_a (
163 .data_i(a_wdata_i),
164 .data_o(a_wdata_d)
165 );
166 prim_secded_inv_39_32_dec u_dec_b (
167 .data_i (b_rdata_sram),
168 .data_o (b_rdata_d[0+:Width]),
169 .syndrome_o ( ),
170 .err_o (b_rerror_d)
171 );
172 end
173 end
174 end else if (EnableParity) begin : gen_byte_parity
175
176 `ASSERT_INIT(ParityNeedsByteWriteMask_A, DataBitsPerMask == 8)
177 `ASSERT_INIT(WidthNeedsToBeByteAligned_A, Width % 8 == 0)
178
179 always_comb begin : p_parity
180 1/1 b_rerror_d = '0;
Tests: T1 T2 T3
181 1/1 for (int i = 0; i < Width/8; i ++) begin
Tests: T1 T2 T3
182 // Data mapping. We have to make 8+1 = 9 bit groups
183 // that have the same write enable such that FPGA tools
184 // can map this correctly to BRAM resources.
185 1/1 a_wmask_d[i*9 +: 8] = a_wmask_i[i*8 +: 8];
Tests: T1 T2 T3
186 1/1 a_wdata_d[i*9 +: 8] = a_wdata_i[i*8 +: 8];
Tests: T1 T2 T3
187 1/1 b_rdata_d[i*8 +: 8] = b_rdata_sram[i*9 +: 8];
Tests: T1 T2 T3
188
189 // parity generation (odd parity)
190 1/1 a_wdata_d[i*9 + 8] = ~(^a_wdata_i[i*8 +: 8]);
Tests: T1 T2 T3
191 1/1 a_wmask_d[i*9 + 8] = &a_wmask_i[i*8 +: 8];
Tests: T1 T2 T3
192 // parity decoding (errors are always uncorrectable)
193 1/1 b_rerror_d[1] |= ~(^{b_rdata_sram[i*9 +: 8], b_rdata_sram[i*9 + 8]});
Tests: T1 T2 T3
194 end
195 end
196 end else begin : gen_nosecded_noparity
197 assign a_wmask_d = a_wmask_i;
198 assign a_wdata_d = a_wdata_i;
199 assign b_rdata_d = b_rdata_sram[0+:Width];
200 assign b_rerror_d = '0;
201 end
202
203 1/1 assign b_rvalid_d = b_rvalid_sram_q;
Tests: T1 T2 T3
204
205 /////////////////////////////////////
206 // Input/Output Pipeline Registers //
207 /////////////////////////////////////
208
209 if (EnableInputPipeline) begin : gen_regslice_input
210 // Put the register slices between ECC encoding to SRAM port
211 always_ff @(posedge clk_a_i or negedge rst_a_ni) begin
212 if (!rst_a_ni) begin
213 a_req_q <= '0;
214 a_addr_q <= '0;
215 a_wdata_q <= '0;
216 a_wmask_q <= '0;
217 end else begin
218 a_req_q <= a_req_d;
219 a_addr_q <= a_addr_d;
220 a_wdata_q <= a_wdata_d;
221 a_wmask_q <= a_wmask_d;
222 end
223 end
224 always_ff @(posedge clk_b_i or negedge rst_b_ni) begin
225 if (!rst_b_ni) begin
226 b_req_q <= '0;
227 b_addr_q <= '0;
228 end else begin
229 b_req_q <= b_req_d;
230 b_addr_q <= b_addr_d;
231 end
232 end
233 end else begin : gen_dirconnect_input
234 1/1 assign a_req_q = a_req_d;
Tests: T1 T2 T3
235 1/1 assign a_addr_q = a_addr_d;
Tests: T1 T2 T3
236 1/1 assign a_wdata_q = a_wdata_d;
Tests: T1 T2 T3
237 1/1 assign a_wmask_q = a_wmask_d;
Tests: T1 T2 T3
238
239 1/1 assign b_req_q = b_req_d;
Tests: T1 T2 T3
240 1/1 assign b_addr_q = b_addr_d;
Tests: T1 T2 T3
241 end
242
243 if (EnableOutputPipeline) begin : gen_regslice_output
244 // Put the register slices between ECC decoding to output
245 always_ff @(posedge clk_b_i or negedge rst_b_ni) begin
246 if (!rst_b_ni) begin
247 b_rvalid_q <= '0;
248 b_rdata_q <= '0;
249 b_rerror_q <= '0;
250 end else begin
251 b_rvalid_q <= b_rvalid_d;
252 b_rdata_q <= b_rdata_d;
253 // tie to zero if the read data is not valid
254 b_rerror_q <= b_rerror_d & {2{b_rvalid_d}};
255 end
256 end
257 end else begin : gen_dirconnect_output
258 1/1 assign b_rvalid_q = b_rvalid_d;
Tests: T1 T2 T3
259 1/1 assign b_rdata_q = b_rdata_d;
Tests: T12 T13 T29
260 // tie to zero if the read data is not valid
261 1/1 assign b_rerror_q = b_rerror_d & {2{b_rvalid_d}};
Tests: T1 T2 T3
Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
118 |
2 |
2 |
100.00 |
118 if (!rst_b_ni) begin
-1-
119 b_rvalid_sram_q <= 1'b0;
==>
120 end else begin
121 b_rvalid_sram_q <= b_req_q;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem
Assertion Details
CannotHaveEccAndParity_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
956 |
956 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
gen_byte_parity.ParityNeedsByteWriteMask_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
956 |
956 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
gen_byte_parity.WidthNeedsToBeByteAligned_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
956 |
956 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |