T333 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_pass_addr_payload_swap.774881915 |
|
|
Sep 04 08:10:20 AM UTC 24 |
Sep 04 08:10:36 AM UTC 24 |
8910503266 ps |
T206 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.2652326676 |
|
|
Sep 04 08:08:51 AM UTC 24 |
Sep 04 08:10:37 AM UTC 24 |
7126337228 ps |
T276 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_upload.2358062139 |
|
|
Sep 04 08:10:25 AM UTC 24 |
Sep 04 08:10:38 AM UTC 24 |
3241131424 ps |
T175 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_stress_all.2431796269 |
|
|
Sep 04 08:09:42 AM UTC 24 |
Sep 04 08:10:38 AM UTC 24 |
51069512796 ps |
T469 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_alert_test.2628206456 |
|
|
Sep 04 08:10:37 AM UTC 24 |
Sep 04 08:10:39 AM UTC 24 |
13014255 ps |
T470 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_read_buffer_direct.3283631399 |
|
|
Sep 04 08:10:32 AM UTC 24 |
Sep 04 08:10:40 AM UTC 24 |
221490567 ps |
T471 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_csb_read.30849430 |
|
|
Sep 04 08:10:38 AM UTC 24 |
Sep 04 08:10:40 AM UTC 24 |
15564540 ps |
T241 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_upload.3636605600 |
|
|
Sep 04 08:10:59 AM UTC 24 |
Sep 04 08:11:28 AM UTC 24 |
9919366068 ps |
T400 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_all.214896299 |
|
|
Sep 04 08:09:23 AM UTC 24 |
Sep 04 08:10:42 AM UTC 24 |
36589210187 ps |
T472 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_sts_read.3907250934 |
|
|
Sep 04 08:10:40 AM UTC 24 |
Sep 04 08:10:43 AM UTC 24 |
268477470 ps |
T248 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.4128554 |
|
|
Sep 04 08:05:38 AM UTC 24 |
Sep 04 08:10:44 AM UTC 24 |
53965649637 ps |
T473 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_rw.49468029 |
|
|
Sep 04 08:10:41 AM UTC 24 |
Sep 04 08:10:44 AM UTC 24 |
20924220 ps |
T236 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_and_tpm_min_idle.515705991 |
|
|
Sep 04 08:09:15 AM UTC 24 |
Sep 04 08:10:46 AM UTC 24 |
14583340672 ps |
T474 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_upload.4249838205 |
|
|
Sep 04 08:10:45 AM UTC 24 |
Sep 04 08:10:48 AM UTC 24 |
82919109 ps |
T319 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_cfg_cmd.3910624582 |
|
|
Sep 04 08:10:46 AM UTC 24 |
Sep 04 08:10:50 AM UTC 24 |
331775693 ps |
T475 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_mode.3002994009 |
|
|
Sep 04 08:10:47 AM UTC 24 |
Sep 04 08:10:52 AM UTC 24 |
605964225 ps |
T337 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_pass_addr_payload_swap.2836366055 |
|
|
Sep 04 08:10:42 AM UTC 24 |
Sep 04 08:10:54 AM UTC 24 |
1878354215 ps |
T279 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_mode_ignore_cmds.1717390104 |
|
|
Sep 04 08:10:04 AM UTC 24 |
Sep 04 08:10:55 AM UTC 24 |
9342797319 ps |
T476 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_read_buffer_direct.1004485447 |
|
|
Sep 04 08:10:49 AM UTC 24 |
Sep 04 08:10:55 AM UTC 24 |
677994406 ps |
T345 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_pass_cmd_filtering.4227816731 |
|
|
Sep 04 08:10:42 AM UTC 24 |
Sep 04 08:10:55 AM UTC 24 |
669473498 ps |
T477 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_read_hw_reg.1332885973 |
|
|
Sep 04 08:10:39 AM UTC 24 |
Sep 04 08:10:56 AM UTC 24 |
22365665703 ps |
T40 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_stress_all.59775866 |
|
|
Sep 04 08:05:40 AM UTC 24 |
Sep 04 08:10:56 AM UTC 24 |
113359211658 ps |
T391 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_all.2754402587 |
|
|
Sep 04 08:10:40 AM UTC 24 |
Sep 04 08:10:57 AM UTC 24 |
1190201176 ps |
T478 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_alert_test.3119654844 |
|
|
Sep 04 08:10:55 AM UTC 24 |
Sep 04 08:10:57 AM UTC 24 |
21615394 ps |
T479 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_mailbox.1936523859 |
|
|
Sep 04 08:10:45 AM UTC 24 |
Sep 04 08:10:58 AM UTC 24 |
16296968339 ps |
T480 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_all.1136732927 |
|
|
Sep 04 08:11:28 AM UTC 24 |
Sep 04 08:11:30 AM UTC 24 |
39972190 ps |
T481 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_csb_read.1028555349 |
|
|
Sep 04 08:10:56 AM UTC 24 |
Sep 04 08:10:58 AM UTC 24 |
46528084 ps |
T482 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_read_hw_reg.3885388407 |
|
|
Sep 04 08:10:56 AM UTC 24 |
Sep 04 08:10:58 AM UTC 24 |
26433196 ps |
T483 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_sts_read.116747046 |
|
|
Sep 04 08:10:57 AM UTC 24 |
Sep 04 08:10:59 AM UTC 24 |
14688890 ps |
T404 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_rw.2609513413 |
|
|
Sep 04 08:10:57 AM UTC 24 |
Sep 04 08:11:00 AM UTC 24 |
156976037 ps |
T237 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_intercept.3950253884 |
|
|
Sep 04 08:10:43 AM UTC 24 |
Sep 04 08:11:02 AM UTC 24 |
1842336984 ps |
T224 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_and_tpm.717366341 |
|
|
Sep 04 08:10:35 AM UTC 24 |
Sep 04 08:11:02 AM UTC 24 |
1946534865 ps |
T484 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_mailbox.343539028 |
|
|
Sep 04 08:10:59 AM UTC 24 |
Sep 04 08:11:03 AM UTC 24 |
216083928 ps |
T127 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_cfg_cmd.684163300 |
|
|
Sep 04 08:10:59 AM UTC 24 |
Sep 04 08:11:03 AM UTC 24 |
44325402 ps |
T300 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_all.34399372 |
|
|
Sep 04 08:10:07 AM UTC 24 |
Sep 04 08:11:04 AM UTC 24 |
2272433929 ps |
T111 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_and_tpm.125743661 |
|
|
Sep 04 08:09:38 AM UTC 24 |
Sep 04 08:11:05 AM UTC 24 |
14161220684 ps |
T485 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_intercept.651538801 |
|
|
Sep 04 08:10:59 AM UTC 24 |
Sep 04 08:11:05 AM UTC 24 |
713092608 ps |
T486 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_alert_test.308047241 |
|
|
Sep 04 08:11:05 AM UTC 24 |
Sep 04 08:11:07 AM UTC 24 |
18501316 ps |
T320 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_pass_cmd_filtering.2822567464 |
|
|
Sep 04 08:10:57 AM UTC 24 |
Sep 04 08:11:07 AM UTC 24 |
4221661938 ps |
T487 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_csb_read.3393358389 |
|
|
Sep 04 08:11:06 AM UTC 24 |
Sep 04 08:11:08 AM UTC 24 |
49258514 ps |
T488 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_csb_read.211758677 |
|
|
Sep 04 08:11:26 AM UTC 24 |
Sep 04 08:11:29 AM UTC 24 |
18750646 ps |
T282 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_pass_addr_payload_swap.3942939045 |
|
|
Sep 04 08:10:59 AM UTC 24 |
Sep 04 08:11:11 AM UTC 24 |
2293930872 ps |
T239 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.3791803683 |
|
|
Sep 04 08:08:16 AM UTC 24 |
Sep 04 08:11:12 AM UTC 24 |
59329357005 ps |
T189 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_stress_all.3440413667 |
|
|
Sep 04 08:04:42 AM UTC 24 |
Sep 04 08:11:14 AM UTC 24 |
21634744121 ps |
T489 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_sts_read.1480109755 |
|
|
Sep 04 08:11:12 AM UTC 24 |
Sep 04 08:11:14 AM UTC 24 |
206827414 ps |
T490 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_rw.1291607883 |
|
|
Sep 04 08:11:12 AM UTC 24 |
Sep 04 08:11:14 AM UTC 24 |
26160843 ps |
T385 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_mode.3169718458 |
|
|
Sep 04 08:11:00 AM UTC 24 |
Sep 04 08:11:15 AM UTC 24 |
556456983 ps |
T242 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_intercept.504407212 |
|
|
Sep 04 08:11:15 AM UTC 24 |
Sep 04 08:11:27 AM UTC 24 |
6475337086 ps |
T301 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_mode_ignore_cmds.2816376648 |
|
|
Sep 04 08:11:01 AM UTC 24 |
Sep 04 08:11:15 AM UTC 24 |
19322099420 ps |
T491 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_read_buffer_direct.705403832 |
|
|
Sep 04 08:11:03 AM UTC 24 |
Sep 04 08:11:15 AM UTC 24 |
1398766154 ps |
T492 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_read_hw_reg.2551688156 |
|
|
Sep 04 08:11:08 AM UTC 24 |
Sep 04 08:11:16 AM UTC 24 |
1934455549 ps |
T409 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.1317142293 |
|
|
Sep 04 08:08:34 AM UTC 24 |
Sep 04 08:11:19 AM UTC 24 |
78337484702 ps |
T493 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_cfg_cmd.1170508656 |
|
|
Sep 04 08:11:16 AM UTC 24 |
Sep 04 08:11:20 AM UTC 24 |
73800570 ps |
T289 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_mailbox.1995212152 |
|
|
Sep 04 08:11:15 AM UTC 24 |
Sep 04 08:11:21 AM UTC 24 |
71562435 ps |
T270 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_pass_cmd_filtering.3885233865 |
|
|
Sep 04 08:11:13 AM UTC 24 |
Sep 04 08:11:22 AM UTC 24 |
2570857065 ps |
T494 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_mode.3575678622 |
|
|
Sep 04 08:11:16 AM UTC 24 |
Sep 04 08:11:23 AM UTC 24 |
760954540 ps |
T495 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_mode_ignore_cmds.2393109167 |
|
|
Sep 04 08:10:31 AM UTC 24 |
Sep 04 08:11:25 AM UTC 24 |
4948205066 ps |
T496 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_stress_all.4029307369 |
|
|
Sep 04 08:11:23 AM UTC 24 |
Sep 04 08:11:26 AM UTC 24 |
329105951 ps |
T497 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_alert_test.970566058 |
|
|
Sep 04 08:11:24 AM UTC 24 |
Sep 04 08:11:26 AM UTC 24 |
46814738 ps |
T498 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_read_buffer_direct.3173945936 |
|
|
Sep 04 08:11:20 AM UTC 24 |
Sep 04 08:11:27 AM UTC 24 |
489498600 ps |
T83 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.230752718 |
|
|
Sep 04 08:08:17 AM UTC 24 |
Sep 04 08:11:31 AM UTC 24 |
13487958259 ps |
T161 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_sts_read.3267148854 |
|
|
Sep 04 08:11:28 AM UTC 24 |
Sep 04 08:11:31 AM UTC 24 |
164855335 ps |
T162 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_all.504703648 |
|
|
Sep 04 08:10:57 AM UTC 24 |
Sep 04 08:11:32 AM UTC 24 |
1597461296 ps |
T163 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_rw.458246465 |
|
|
Sep 04 08:11:29 AM UTC 24 |
Sep 04 08:11:33 AM UTC 24 |
31986274 ps |
T164 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_all.1622195386 |
|
|
Sep 04 08:11:10 AM UTC 24 |
Sep 04 08:11:36 AM UTC 24 |
4644425943 ps |
T165 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_pass_addr_payload_swap.1908002998 |
|
|
Sep 04 08:11:30 AM UTC 24 |
Sep 04 08:11:38 AM UTC 24 |
16612130596 ps |
T166 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_upload.803397405 |
|
|
Sep 04 08:11:16 AM UTC 24 |
Sep 04 08:11:39 AM UTC 24 |
5470210050 ps |
T167 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_pass_cmd_filtering.1680158475 |
|
|
Sep 04 08:11:29 AM UTC 24 |
Sep 04 08:11:40 AM UTC 24 |
1332046296 ps |
T168 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_intercept.743418296 |
|
|
Sep 04 08:11:32 AM UTC 24 |
Sep 04 08:11:40 AM UTC 24 |
382723016 ps |
T169 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_upload.2261915088 |
|
|
Sep 04 08:11:32 AM UTC 24 |
Sep 04 08:11:44 AM UTC 24 |
2665089343 ps |
T341 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_mailbox.2158188936 |
|
|
Sep 04 08:11:32 AM UTC 24 |
Sep 04 08:11:46 AM UTC 24 |
692514223 ps |
T499 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_stress_all.3654221294 |
|
|
Sep 04 08:11:44 AM UTC 24 |
Sep 04 08:11:47 AM UTC 24 |
93294598 ps |
T500 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_read_hw_reg.357501368 |
|
|
Sep 04 08:11:27 AM UTC 24 |
Sep 04 08:11:48 AM UTC 24 |
5091590406 ps |
T501 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_alert_test.1916059214 |
|
|
Sep 04 08:11:47 AM UTC 24 |
Sep 04 08:11:50 AM UTC 24 |
24145768 ps |
T502 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_csb_read.762492539 |
|
|
Sep 04 08:11:48 AM UTC 24 |
Sep 04 08:11:50 AM UTC 24 |
76979583 ps |
T329 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_and_tpm_min_idle.157204594 |
|
|
Sep 04 08:11:04 AM UTC 24 |
Sep 04 08:11:50 AM UTC 24 |
2595347575 ps |
T295 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_and_tpm.2047327221 |
|
|
Sep 04 08:10:51 AM UTC 24 |
Sep 04 08:11:52 AM UTC 24 |
1879136750 ps |
T503 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_read_hw_reg.1712714228 |
|
|
Sep 04 08:11:51 AM UTC 24 |
Sep 04 08:11:53 AM UTC 24 |
11158742 ps |
T504 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_read_buffer_direct.188848193 |
|
|
Sep 04 08:11:39 AM UTC 24 |
Sep 04 08:11:53 AM UTC 24 |
2225464311 ps |
T505 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_sts_read.1995093313 |
|
|
Sep 04 08:11:51 AM UTC 24 |
Sep 04 08:11:53 AM UTC 24 |
119791120 ps |
T393 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_and_tpm_min_idle.1218031723 |
|
|
Sep 04 08:09:38 AM UTC 24 |
Sep 04 08:11:55 AM UTC 24 |
26857942445 ps |
T317 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_cfg_cmd.882636311 |
|
|
Sep 04 08:11:33 AM UTC 24 |
Sep 04 08:11:55 AM UTC 24 |
1825755525 ps |
T506 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_rw.1752837318 |
|
|
Sep 04 08:11:52 AM UTC 24 |
Sep 04 08:11:58 AM UTC 24 |
583953183 ps |
T507 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_mailbox.1942614003 |
|
|
Sep 04 08:11:54 AM UTC 24 |
Sep 04 08:11:58 AM UTC 24 |
103903853 ps |
T508 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_upload.2324506690 |
|
|
Sep 04 08:11:55 AM UTC 24 |
Sep 04 08:11:59 AM UTC 24 |
40617228 ps |
T314 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_pass_cmd_filtering.1153431105 |
|
|
Sep 04 08:11:53 AM UTC 24 |
Sep 04 08:12:00 AM UTC 24 |
1355301748 ps |
T509 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_cfg_cmd.3418897460 |
|
|
Sep 04 08:11:56 AM UTC 24 |
Sep 04 08:12:00 AM UTC 24 |
102653324 ps |
T346 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_pass_addr_payload_swap.3264960429 |
|
|
Sep 04 08:11:15 AM UTC 24 |
Sep 04 08:12:02 AM UTC 24 |
10948430760 ps |
T510 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_mode.695462430 |
|
|
Sep 04 08:11:59 AM UTC 24 |
Sep 04 08:12:04 AM UTC 24 |
284291881 ps |
T271 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_all.3510672266 |
|
|
Sep 04 08:11:03 AM UTC 24 |
Sep 04 08:12:05 AM UTC 24 |
32545630218 ps |
T258 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_pass_addr_payload_swap.3723628015 |
|
|
Sep 04 08:11:54 AM UTC 24 |
Sep 04 08:12:06 AM UTC 24 |
13361705362 ps |
T511 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_alert_test.2237203158 |
|
|
Sep 04 08:12:06 AM UTC 24 |
Sep 04 08:12:08 AM UTC 24 |
44350883 ps |
T512 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_csb_read.142323262 |
|
|
Sep 04 08:12:06 AM UTC 24 |
Sep 04 08:12:08 AM UTC 24 |
64384824 ps |
T293 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_stress_all.2980344061 |
|
|
Sep 04 08:10:11 AM UTC 24 |
Sep 04 08:12:10 AM UTC 24 |
36551599946 ps |
T41 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_stress_all.2153738294 |
|
|
Sep 04 08:04:02 AM UTC 24 |
Sep 04 08:12:12 AM UTC 24 |
176537972677 ps |
T513 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_sts_read.1107531746 |
|
|
Sep 04 08:12:11 AM UTC 24 |
Sep 04 08:12:13 AM UTC 24 |
121572280 ps |
T514 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_read_hw_reg.3864730871 |
|
|
Sep 04 08:12:09 AM UTC 24 |
Sep 04 08:12:14 AM UTC 24 |
6718899000 ps |
T515 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_rw.1620161958 |
|
|
Sep 04 08:12:13 AM UTC 24 |
Sep 04 08:12:16 AM UTC 24 |
19250525 ps |
T516 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_read_buffer_direct.2183660706 |
|
|
Sep 04 08:12:00 AM UTC 24 |
Sep 04 08:12:16 AM UTC 24 |
1904280264 ps |
T517 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_and_tpm.1140168105 |
|
|
Sep 04 08:11:03 AM UTC 24 |
Sep 04 08:12:17 AM UTC 24 |
13286531890 ps |
T331 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_pass_addr_payload_swap.279392344 |
|
|
Sep 04 08:12:14 AM UTC 24 |
Sep 04 08:12:19 AM UTC 24 |
62583747 ps |
T232 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode_ignore_cmds.1267617306 |
|
|
Sep 04 08:07:23 AM UTC 24 |
Sep 04 08:12:21 AM UTC 24 |
136060219013 ps |
T230 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_intercept.164555660 |
|
|
Sep 04 08:12:16 AM UTC 24 |
Sep 04 08:12:22 AM UTC 24 |
1171058401 ps |
T518 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_mode.3060759847 |
|
|
Sep 04 08:12:22 AM UTC 24 |
Sep 04 08:12:26 AM UTC 24 |
198170436 ps |
T519 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_and_tpm_min_idle.1042540805 |
|
|
Sep 04 08:10:10 AM UTC 24 |
Sep 04 08:12:27 AM UTC 24 |
66890502775 ps |
T520 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_cfg_cmd.2249568529 |
|
|
Sep 04 08:12:20 AM UTC 24 |
Sep 04 08:12:28 AM UTC 24 |
181641443 ps |
T298 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_pass_cmd_filtering.1774147757 |
|
|
Sep 04 08:12:14 AM UTC 24 |
Sep 04 08:12:28 AM UTC 24 |
850786661 ps |
T394 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_all.3311016974 |
|
|
Sep 04 08:11:51 AM UTC 24 |
Sep 04 08:12:29 AM UTC 24 |
27247840907 ps |
T521 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_intercept.598711176 |
|
|
Sep 04 08:11:54 AM UTC 24 |
Sep 04 08:12:33 AM UTC 24 |
12168235007 ps |
T382 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_mode.1164881952 |
|
|
Sep 04 08:11:34 AM UTC 24 |
Sep 04 08:12:33 AM UTC 24 |
3673136554 ps |
T522 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_read_buffer_direct.4066559165 |
|
|
Sep 04 08:12:27 AM UTC 24 |
Sep 04 08:12:33 AM UTC 24 |
357785830 ps |
T523 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_upload.3671733702 |
|
|
Sep 04 08:12:18 AM UTC 24 |
Sep 04 08:12:34 AM UTC 24 |
1738782979 ps |
T524 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_alert_test.1802234149 |
|
|
Sep 04 08:12:33 AM UTC 24 |
Sep 04 08:12:35 AM UTC 24 |
107013006 ps |
T525 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_csb_read.963581541 |
|
|
Sep 04 08:12:34 AM UTC 24 |
Sep 04 08:12:36 AM UTC 24 |
32748466 ps |
T526 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_sts_read.1133546435 |
|
|
Sep 04 08:12:37 AM UTC 24 |
Sep 04 08:12:39 AM UTC 24 |
80749096 ps |
T527 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_rw.241251416 |
|
|
Sep 04 08:12:38 AM UTC 24 |
Sep 04 08:12:41 AM UTC 24 |
247031189 ps |
T233 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_and_tpm.2091138616 |
|
|
Sep 04 08:09:12 AM UTC 24 |
Sep 04 08:12:45 AM UTC 24 |
45903010797 ps |
T528 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_intercept.3126097107 |
|
|
Sep 04 08:12:46 AM UTC 24 |
Sep 04 08:12:50 AM UTC 24 |
77329467 ps |
T529 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_pass_addr_payload_swap.1372097563 |
|
|
Sep 04 08:12:42 AM UTC 24 |
Sep 04 08:12:52 AM UTC 24 |
4366832401 ps |
T530 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_mode_ignore_cmds.191685237 |
|
|
Sep 04 08:11:37 AM UTC 24 |
Sep 04 08:12:56 AM UTC 24 |
37131028283 ps |
T531 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_all.1844510536 |
|
|
Sep 04 08:10:50 AM UTC 24 |
Sep 04 08:12:56 AM UTC 24 |
26886674120 ps |
T532 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_read_hw_reg.3720469895 |
|
|
Sep 04 08:12:34 AM UTC 24 |
Sep 04 08:12:57 AM UTC 24 |
5479320967 ps |
T533 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_upload.3644946287 |
|
|
Sep 04 08:12:53 AM UTC 24 |
Sep 04 08:12:58 AM UTC 24 |
172908365 ps |
T534 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_and_tpm.3603383186 |
|
|
Sep 04 08:11:21 AM UTC 24 |
Sep 04 08:13:07 AM UTC 24 |
5084905645 ps |
T535 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_read_buffer_direct.211875524 |
|
|
Sep 04 08:12:59 AM UTC 24 |
Sep 04 08:13:08 AM UTC 24 |
465729250 ps |
T536 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_mailbox.1396265645 |
|
|
Sep 04 08:12:16 AM UTC 24 |
Sep 04 08:13:08 AM UTC 24 |
33334847175 ps |
T537 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_mode.2533922123 |
|
|
Sep 04 08:12:57 AM UTC 24 |
Sep 04 08:13:09 AM UTC 24 |
3512312881 ps |
T538 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_mailbox.4208335472 |
|
|
Sep 04 08:12:51 AM UTC 24 |
Sep 04 08:13:11 AM UTC 24 |
2297873162 ps |
T539 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_cfg_cmd.2325475180 |
|
|
Sep 04 08:12:57 AM UTC 24 |
Sep 04 08:13:14 AM UTC 24 |
2967987036 ps |
T540 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_alert_test.2846522366 |
|
|
Sep 04 08:13:12 AM UTC 24 |
Sep 04 08:13:14 AM UTC 24 |
23074565 ps |
T226 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_all.3751779140 |
|
|
Sep 04 08:08:15 AM UTC 24 |
Sep 04 08:13:14 AM UTC 24 |
130893433852 ps |
T541 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_all.1309609083 |
|
|
Sep 04 08:12:35 AM UTC 24 |
Sep 04 08:13:15 AM UTC 24 |
3725957493 ps |
T542 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_csb_read.1540464060 |
|
|
Sep 04 08:13:15 AM UTC 24 |
Sep 04 08:13:17 AM UTC 24 |
13167218 ps |
T190 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_stress_all.3259052392 |
|
|
Sep 04 08:10:53 AM UTC 24 |
Sep 04 08:13:17 AM UTC 24 |
67037358316 ps |
T543 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_sts_read.614402547 |
|
|
Sep 04 08:13:15 AM UTC 24 |
Sep 04 08:13:17 AM UTC 24 |
58268130 ps |
T405 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_all.1378209729 |
|
|
Sep 04 08:12:09 AM UTC 24 |
Sep 04 08:13:20 AM UTC 24 |
26659801574 ps |
T544 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_rw.74905045 |
|
|
Sep 04 08:13:16 AM UTC 24 |
Sep 04 08:13:21 AM UTC 24 |
839513328 ps |
T287 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_intercept.670447504 |
|
|
Sep 04 08:13:18 AM UTC 24 |
Sep 04 08:13:23 AM UTC 24 |
44493577 ps |
T191 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_stress_all.1944283710 |
|
|
Sep 04 08:07:26 AM UTC 24 |
Sep 04 08:13:23 AM UTC 24 |
116750588957 ps |
T545 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_all.4193594562 |
|
|
Sep 04 08:13:15 AM UTC 24 |
Sep 04 08:13:25 AM UTC 24 |
485078425 ps |
T259 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_and_tpm.2274563551 |
|
|
Sep 04 08:11:41 AM UTC 24 |
Sep 04 08:13:25 AM UTC 24 |
46789294021 ps |
T546 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_and_tpm.2856392828 |
|
|
Sep 04 08:12:29 AM UTC 24 |
Sep 04 08:13:25 AM UTC 24 |
5219058591 ps |
T547 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_and_tpm.3763926010 |
|
|
Sep 04 08:13:08 AM UTC 24 |
Sep 04 08:13:30 AM UTC 24 |
1226085079 ps |
T231 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_pass_cmd_filtering.918062215 |
|
|
Sep 04 08:13:18 AM UTC 24 |
Sep 04 08:13:31 AM UTC 24 |
3573247563 ps |
T548 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_upload.4218933968 |
|
|
Sep 04 08:13:22 AM UTC 24 |
Sep 04 08:13:34 AM UTC 24 |
574731919 ps |
T397 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_and_tpm.1569257920 |
|
|
Sep 04 08:12:02 AM UTC 24 |
Sep 04 08:13:35 AM UTC 24 |
4669568315 ps |
T549 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_mailbox.3753058306 |
|
|
Sep 04 08:13:20 AM UTC 24 |
Sep 04 08:13:35 AM UTC 24 |
712897734 ps |
T294 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_pass_cmd_filtering.3230810684 |
|
|
Sep 04 08:12:40 AM UTC 24 |
Sep 04 08:13:36 AM UTC 24 |
49738045793 ps |
T550 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_alert_test.3704846816 |
|
|
Sep 04 08:13:35 AM UTC 24 |
Sep 04 08:13:37 AM UTC 24 |
108394060 ps |
T551 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_csb_read.2190617543 |
|
|
Sep 04 08:13:35 AM UTC 24 |
Sep 04 08:13:38 AM UTC 24 |
108981794 ps |
T244 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_mode_ignore_cmds.2023836876 |
|
|
Sep 04 08:11:59 AM UTC 24 |
Sep 04 08:13:38 AM UTC 24 |
5746823987 ps |
T552 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_read_buffer_direct.2905942628 |
|
|
Sep 04 08:13:26 AM UTC 24 |
Sep 04 08:13:39 AM UTC 24 |
4840585650 ps |
T553 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_sts_read.917528082 |
|
|
Sep 04 08:13:39 AM UTC 24 |
Sep 04 08:13:41 AM UTC 24 |
129435457 ps |
T554 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_read_hw_reg.1299519763 |
|
|
Sep 04 08:13:15 AM UTC 24 |
Sep 04 08:13:41 AM UTC 24 |
3821043793 ps |
T555 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_sts_read.4273187168 |
|
|
Sep 04 08:14:27 AM UTC 24 |
Sep 04 08:14:30 AM UTC 24 |
96716532 ps |
T252 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_and_tpm_min_idle.2490989206 |
|
|
Sep 04 08:12:03 AM UTC 24 |
Sep 04 08:13:42 AM UTC 24 |
21983110426 ps |
T556 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_pass_addr_payload_swap.1237717254 |
|
|
Sep 04 08:13:18 AM UTC 24 |
Sep 04 08:13:42 AM UTC 24 |
12637823583 ps |
T557 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_rw.1740066108 |
|
|
Sep 04 08:13:39 AM UTC 24 |
Sep 04 08:13:43 AM UTC 24 |
123917845 ps |
T307 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_and_tpm_min_idle.3702442732 |
|
|
Sep 04 08:11:22 AM UTC 24 |
Sep 04 08:13:45 AM UTC 24 |
68608674653 ps |
T383 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_mode.3983826074 |
|
|
Sep 04 08:13:24 AM UTC 24 |
Sep 04 08:13:45 AM UTC 24 |
686613046 ps |
T558 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_pass_cmd_filtering.406073561 |
|
|
Sep 04 08:13:39 AM UTC 24 |
Sep 04 08:13:46 AM UTC 24 |
2848178946 ps |
T349 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_intercept.3684802341 |
|
|
Sep 04 08:13:42 AM UTC 24 |
Sep 04 08:13:48 AM UTC 24 |
2581541876 ps |
T347 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_cfg_cmd.3493023318 |
|
|
Sep 04 08:13:42 AM UTC 24 |
Sep 04 08:13:48 AM UTC 24 |
697488876 ps |
T559 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_and_tpm_min_idle.1418803867 |
|
|
Sep 04 08:13:10 AM UTC 24 |
Sep 04 08:13:50 AM UTC 24 |
4440622621 ps |
T560 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_all.2310911369 |
|
|
Sep 04 08:13:27 AM UTC 24 |
Sep 04 08:13:51 AM UTC 24 |
4087124889 ps |
T561 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_mode_ignore_cmds.4268084533 |
|
|
Sep 04 08:12:23 AM UTC 24 |
Sep 04 08:13:51 AM UTC 24 |
18950610131 ps |
T562 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_alert_test.242869478 |
|
|
Sep 04 08:13:52 AM UTC 24 |
Sep 04 08:13:54 AM UTC 24 |
16227165 ps |
T563 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_csb_read.2471645922 |
|
|
Sep 04 08:13:52 AM UTC 24 |
Sep 04 08:13:54 AM UTC 24 |
76047298 ps |
T564 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_read_buffer_direct.2806079340 |
|
|
Sep 04 08:13:46 AM UTC 24 |
Sep 04 08:13:55 AM UTC 24 |
303243116 ps |
T389 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_mode.4162963386 |
|
|
Sep 04 08:13:43 AM UTC 24 |
Sep 04 08:13:55 AM UTC 24 |
735009564 ps |
T565 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_cfg_cmd.139016866 |
|
|
Sep 04 08:13:24 AM UTC 24 |
Sep 04 08:13:56 AM UTC 24 |
9103453061 ps |
T566 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_all.2577042839 |
|
|
Sep 04 08:13:55 AM UTC 24 |
Sep 04 08:13:57 AM UTC 24 |
23151593 ps |
T567 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_read_hw_reg.185819834 |
|
|
Sep 04 08:13:37 AM UTC 24 |
Sep 04 08:13:58 AM UTC 24 |
5669466739 ps |
T568 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_sts_read.1969560627 |
|
|
Sep 04 08:13:56 AM UTC 24 |
Sep 04 08:13:58 AM UTC 24 |
310953354 ps |
T569 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_rw.595119646 |
|
|
Sep 04 08:13:56 AM UTC 24 |
Sep 04 08:13:59 AM UTC 24 |
175555801 ps |
T265 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_and_tpm_min_idle.2270061185 |
|
|
Sep 04 08:12:29 AM UTC 24 |
Sep 04 08:14:00 AM UTC 24 |
5735786864 ps |
T570 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_read_hw_reg.1290405247 |
|
|
Sep 04 08:13:55 AM UTC 24 |
Sep 04 08:14:01 AM UTC 24 |
763249291 ps |
T571 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_all.1841105520 |
|
|
Sep 04 08:13:37 AM UTC 24 |
Sep 04 08:14:01 AM UTC 24 |
11326713918 ps |
T256 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_and_tpm_min_idle.1843426473 |
|
|
Sep 04 08:10:36 AM UTC 24 |
Sep 04 08:14:01 AM UTC 24 |
145925862755 ps |
T572 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_intercept.3825606292 |
|
|
Sep 04 08:13:58 AM UTC 24 |
Sep 04 08:14:04 AM UTC 24 |
519774778 ps |
T263 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_pass_addr_payload_swap.3608972794 |
|
|
Sep 04 08:13:40 AM UTC 24 |
Sep 04 08:14:05 AM UTC 24 |
5594367983 ps |
T573 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_cfg_cmd.178498234 |
|
|
Sep 04 08:14:00 AM UTC 24 |
Sep 04 08:14:08 AM UTC 24 |
241892138 ps |
T574 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_mode_ignore_cmds.4073394 |
|
|
Sep 04 08:14:02 AM UTC 24 |
Sep 04 08:14:08 AM UTC 24 |
151784327 ps |
T575 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_pass_addr_payload_swap.2386429646 |
|
|
Sep 04 08:13:58 AM UTC 24 |
Sep 04 08:14:09 AM UTC 24 |
22092839739 ps |
T576 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_stress_all.2692070658 |
|
|
Sep 04 08:14:08 AM UTC 24 |
Sep 04 08:14:11 AM UTC 24 |
89811371 ps |
T387 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_mode.805481136 |
|
|
Sep 04 08:14:01 AM UTC 24 |
Sep 04 08:14:11 AM UTC 24 |
256557208 ps |
T577 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_alert_test.3224837892 |
|
|
Sep 04 08:14:09 AM UTC 24 |
Sep 04 08:14:11 AM UTC 24 |
14135903 ps |
T578 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_csb_read.3524512042 |
|
|
Sep 04 08:14:10 AM UTC 24 |
Sep 04 08:14:13 AM UTC 24 |
20517993 ps |
T579 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_upload.1974777729 |
|
|
Sep 04 08:14:00 AM UTC 24 |
Sep 04 08:14:13 AM UTC 24 |
1472206792 ps |
T580 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_upload.4271997535 |
|
|
Sep 04 08:13:42 AM UTC 24 |
Sep 04 08:14:15 AM UTC 24 |
12809224723 ps |
T277 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_mode.435447691 |
|
|
Sep 04 08:14:19 AM UTC 24 |
Sep 04 08:14:30 AM UTC 24 |
745721865 ps |
T581 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_sts_read.2597927921 |
|
|
Sep 04 08:14:12 AM UTC 24 |
Sep 04 08:14:15 AM UTC 24 |
42468115 ps |
T582 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_rw.3324055701 |
|
|
Sep 04 08:14:14 AM UTC 24 |
Sep 04 08:14:16 AM UTC 24 |
86552894 ps |
T583 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_read_buffer_direct.3278568234 |
|
|
Sep 04 08:14:02 AM UTC 24 |
Sep 04 08:14:17 AM UTC 24 |
999799853 ps |
T584 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_pass_cmd_filtering.3160627966 |
|
|
Sep 04 08:13:57 AM UTC 24 |
Sep 04 08:14:18 AM UTC 24 |
4014252141 ps |
T253 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_all.1426951750 |
|
|
Sep 04 08:13:07 AM UTC 24 |
Sep 04 08:14:18 AM UTC 24 |
15395921024 ps |
T585 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_pass_addr_payload_swap.205989879 |
|
|
Sep 04 08:14:15 AM UTC 24 |
Sep 04 08:14:19 AM UTC 24 |
65032751 ps |
T586 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_all.3248220772 |
|
|
Sep 04 08:14:03 AM UTC 24 |
Sep 04 08:14:19 AM UTC 24 |
728156805 ps |
T587 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_mailbox.2970623636 |
|
|
Sep 04 08:14:16 AM UTC 24 |
Sep 04 08:14:20 AM UTC 24 |
62971129 ps |
T588 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_cfg_cmd.2113867616 |
|
|
Sep 04 08:14:17 AM UTC 24 |
Sep 04 08:14:21 AM UTC 24 |
65511686 ps |
T589 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_upload.1012511706 |
|
|
Sep 04 08:14:17 AM UTC 24 |
Sep 04 08:14:21 AM UTC 24 |
297983643 ps |
T302 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_intercept.3942705742 |
|
|
Sep 04 08:14:16 AM UTC 24 |
Sep 04 08:14:23 AM UTC 24 |
181665360 ps |
T590 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_all.1489461140 |
|
|
Sep 04 08:14:11 AM UTC 24 |
Sep 04 08:14:23 AM UTC 24 |
766472700 ps |
T342 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_mailbox.3208606804 |
|
|
Sep 04 08:13:59 AM UTC 24 |
Sep 04 08:14:24 AM UTC 24 |
5482635194 ps |
T591 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_alert_test.1624135585 |
|
|
Sep 04 08:14:24 AM UTC 24 |
Sep 04 08:14:26 AM UTC 24 |
123154063 ps |
T592 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_csb_read.2197129943 |
|
|
Sep 04 08:14:24 AM UTC 24 |
Sep 04 08:14:26 AM UTC 24 |
39979718 ps |
T593 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_read_buffer_direct.3512299266 |
|
|
Sep 04 08:14:19 AM UTC 24 |
Sep 04 08:14:26 AM UTC 24 |
1446396870 ps |
T254 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_mode_ignore_cmds.3883326464 |
|
|
Sep 04 08:11:17 AM UTC 24 |
Sep 04 08:14:26 AM UTC 24 |
20784665464 ps |
T128 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_mode_ignore_cmds.3097839708 |
|
|
Sep 04 08:10:48 AM UTC 24 |
Sep 04 08:14:27 AM UTC 24 |
50519709799 ps |
T594 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_all.798360116 |
|
|
Sep 04 08:14:27 AM UTC 24 |
Sep 04 08:14:29 AM UTC 24 |
29071607 ps |
T595 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_rw.1269808772 |
|
|
Sep 04 08:14:27 AM UTC 24 |
Sep 04 08:14:29 AM UTC 24 |
13030397 ps |
T596 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_read_hw_reg.2771389509 |
|
|
Sep 04 08:14:11 AM UTC 24 |
Sep 04 08:14:30 AM UTC 24 |
16810300979 ps |
T597 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_read_hw_reg.1145650986 |
|
|
Sep 04 08:14:25 AM UTC 24 |
Sep 04 08:14:30 AM UTC 24 |
1959812509 ps |
T234 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_all.3236329625 |
|
|
Sep 04 08:08:32 AM UTC 24 |
Sep 04 08:14:32 AM UTC 24 |
48597778969 ps |
T598 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_mode_ignore_cmds.1483218622 |
|
|
Sep 04 08:12:57 AM UTC 24 |
Sep 04 08:14:34 AM UTC 24 |
32697853755 ps |
T235 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_pass_addr_payload_swap.3061795631 |
|
|
Sep 04 08:14:28 AM UTC 24 |
Sep 04 08:14:35 AM UTC 24 |
1144641868 ps |
T599 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_cfg_cmd.3101301503 |
|
|
Sep 04 08:14:30 AM UTC 24 |
Sep 04 08:14:41 AM UTC 24 |
557609227 ps |
T600 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_mode.1626685118 |
|
|
Sep 04 08:14:30 AM UTC 24 |
Sep 04 08:14:42 AM UTC 24 |
1527424753 ps |
T246 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_mailbox.275449351 |
|
|
Sep 04 08:14:30 AM UTC 24 |
Sep 04 08:14:42 AM UTC 24 |
236394222 ps |
T601 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_intercept.1762520389 |
|
|
Sep 04 08:14:30 AM UTC 24 |
Sep 04 08:14:44 AM UTC 24 |
12662543914 ps |
T227 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_and_tpm_min_idle.1534320562 |
|
|
Sep 04 08:08:57 AM UTC 24 |
Sep 04 08:14:44 AM UTC 24 |
28132124034 ps |
T602 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_alert_test.1676661275 |
|
|
Sep 04 08:14:43 AM UTC 24 |
Sep 04 08:14:45 AM UTC 24 |
46417607 ps |
T603 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_mode_ignore_cmds.617575360 |
|
|
Sep 04 08:14:19 AM UTC 24 |
Sep 04 08:14:46 AM UTC 24 |
1621092889 ps |
T604 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_csb_read.2453987847 |
|
|
Sep 04 08:14:44 AM UTC 24 |
Sep 04 08:14:47 AM UTC 24 |
33509445 ps |
T605 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_read_buffer_direct.1523135608 |
|
|
Sep 04 08:14:34 AM UTC 24 |
Sep 04 08:14:49 AM UTC 24 |
6879573573 ps |
T606 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_sts_read.2513062388 |
|
|
Sep 04 08:14:46 AM UTC 24 |
Sep 04 08:14:49 AM UTC 24 |
127377721 ps |
T607 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_pass_cmd_filtering.1645223487 |
|
|
Sep 04 08:14:27 AM UTC 24 |
Sep 04 08:14:50 AM UTC 24 |
15101546667 ps |
T608 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_upload.1544905536 |
|
|
Sep 04 08:14:30 AM UTC 24 |
Sep 04 08:14:52 AM UTC 24 |
14520619213 ps |
T609 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_rw.2338171512 |
|
|
Sep 04 08:14:47 AM UTC 24 |
Sep 04 08:14:53 AM UTC 24 |
94455425 ps |
T247 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_all.1295350846 |
|
|
Sep 04 08:09:38 AM UTC 24 |
Sep 04 08:14:55 AM UTC 24 |
34971800940 ps |
T280 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_intercept.3853684344 |
|
|
Sep 04 08:14:51 AM UTC 24 |
Sep 04 08:14:57 AM UTC 24 |
958045396 ps |
T610 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_upload.3028128981 |
|
|
Sep 04 08:14:53 AM UTC 24 |
Sep 04 08:14:57 AM UTC 24 |
56326001 ps |
T611 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_all.3682528735 |
|
|
Sep 04 08:11:21 AM UTC 24 |
Sep 04 08:14:57 AM UTC 24 |
114339991205 ps |
T612 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_read_hw_reg.29767720 |
|
|
Sep 04 08:14:45 AM UTC 24 |
Sep 04 08:14:59 AM UTC 24 |
1587753667 ps |
T328 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_all.1214094772 |
|
|
Sep 04 08:11:40 AM UTC 24 |
Sep 04 08:15:00 AM UTC 24 |
93834171073 ps |
T613 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_pass_cmd_filtering.355966118 |
|
|
Sep 04 08:14:15 AM UTC 24 |
Sep 04 08:15:02 AM UTC 24 |
30788270342 ps |
T614 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_cfg_cmd.3164194087 |
|
|
Sep 04 08:14:54 AM UTC 24 |
Sep 04 08:15:02 AM UTC 24 |
557817222 ps |
T615 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_all.413880403 |
|
|
Sep 04 08:14:45 AM UTC 24 |
Sep 04 08:15:02 AM UTC 24 |
2465493589 ps |
T396 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.2582967247 |
|
|
Sep 04 08:08:32 AM UTC 24 |
Sep 04 08:15:04 AM UTC 24 |
40931579886 ps |
T616 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_alert_test.3977880939 |
|
|
Sep 04 08:15:02 AM UTC 24 |
Sep 04 08:15:05 AM UTC 24 |
24343195 ps |
T617 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_stress_all.3767128260 |
|
|
Sep 04 08:12:30 AM UTC 24 |
Sep 04 08:15:06 AM UTC 24 |
17136689418 ps |
T618 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_csb_read.2152276340 |
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|
Sep 04 08:15:04 AM UTC 24 |
Sep 04 08:15:06 AM UTC 24 |
21744645 ps |
T308 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_and_tpm.1381288458 |
|
|
Sep 04 08:13:27 AM UTC 24 |
Sep 04 08:15:06 AM UTC 24 |
13354161737 ps |
T619 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_pass_cmd_filtering.1610170256 |
|
|
Sep 04 08:14:48 AM UTC 24 |
Sep 04 08:15:08 AM UTC 24 |
12725023162 ps |
T620 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_read_buffer_direct.1332406002 |
|
|
Sep 04 08:14:58 AM UTC 24 |
Sep 04 08:15:08 AM UTC 24 |
3855963126 ps |
T621 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_sts_read.296115713 |
|
|
Sep 04 08:15:07 AM UTC 24 |
Sep 04 08:15:09 AM UTC 24 |
13174480 ps |
T622 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_rw.797510517 |
|
|
Sep 04 08:15:07 AM UTC 24 |
Sep 04 08:15:12 AM UTC 24 |
663599084 ps |
T623 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_pass_addr_payload_swap.1643307607 |
|
|
Sep 04 08:14:50 AM UTC 24 |
Sep 04 08:15:12 AM UTC 24 |
69265585074 ps |
T335 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_pass_addr_payload_swap.3486616687 |
|
|
Sep 04 08:15:09 AM UTC 24 |
Sep 04 08:15:13 AM UTC 24 |
157994040 ps |
T624 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_pass_cmd_filtering.3503767474 |
|
|
Sep 04 08:15:07 AM UTC 24 |
Sep 04 08:15:14 AM UTC 24 |
289938552 ps |