| T838 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm.2178554343 |
|
|
Sep 04 08:19:39 AM UTC 24 |
Sep 04 08:20:06 AM UTC 24 |
2236629846 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_all.3281657368 |
|
|
Sep 04 08:19:25 AM UTC 24 |
Sep 04 08:20:08 AM UTC 24 |
8014521240 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_upload.405240616 |
|
|
Sep 04 08:20:02 AM UTC 24 |
Sep 04 08:20:09 AM UTC 24 |
395586579 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_alert_test.1023175858 |
|
|
Sep 04 08:20:08 AM UTC 24 |
Sep 04 08:20:10 AM UTC 24 |
22946051 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_read_buffer_direct.1876450578 |
|
|
Sep 04 08:20:05 AM UTC 24 |
Sep 04 08:20:10 AM UTC 24 |
586376653 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_read_hw_reg.1037582980 |
|
|
Sep 04 08:20:09 AM UTC 24 |
Sep 04 08:20:11 AM UTC 24 |
42131434 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_csb_read.2879071558 |
|
|
Sep 04 08:20:09 AM UTC 24 |
Sep 04 08:20:11 AM UTC 24 |
13355593 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_sts_read.1509395975 |
|
|
Sep 04 08:20:11 AM UTC 24 |
Sep 04 08:20:14 AM UTC 24 |
59401314 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_intercept.1764075839 |
|
|
Sep 04 08:19:59 AM UTC 24 |
Sep 04 08:20:15 AM UTC 24 |
1303232231 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode.2269592104 |
|
|
Sep 04 08:20:03 AM UTC 24 |
Sep 04 08:20:15 AM UTC 24 |
12585101370 ps |
| T261 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_stress_all.2744118662 |
|
|
Sep 04 08:12:05 AM UTC 24 |
Sep 04 08:20:16 AM UTC 24 |
191956410672 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_all.215873056 |
|
|
Sep 04 08:20:11 AM UTC 24 |
Sep 04 08:20:18 AM UTC 24 |
280961318 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_rw.454608107 |
|
|
Sep 04 08:20:13 AM UTC 24 |
Sep 04 08:20:18 AM UTC 24 |
1141492637 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_all.2695078042 |
|
|
Sep 04 08:19:49 AM UTC 24 |
Sep 04 08:20:18 AM UTC 24 |
3771795686 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_upload.2509130146 |
|
|
Sep 04 08:20:17 AM UTC 24 |
Sep 04 08:20:22 AM UTC 24 |
114351354 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_addr_payload_swap.1581431931 |
|
|
Sep 04 08:20:15 AM UTC 24 |
Sep 04 08:20:22 AM UTC 24 |
12137995429 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_mode.3053907580 |
|
|
Sep 04 08:19:36 AM UTC 24 |
Sep 04 08:20:24 AM UTC 24 |
2541679958 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode.1380194634 |
|
|
Sep 04 08:20:19 AM UTC 24 |
Sep 04 08:20:24 AM UTC 24 |
63922801 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_cfg_cmd.3919821348 |
|
|
Sep 04 08:20:19 AM UTC 24 |
Sep 04 08:20:24 AM UTC 24 |
126951946 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_intercept.3693573949 |
|
|
Sep 04 08:20:16 AM UTC 24 |
Sep 04 08:20:26 AM UTC 24 |
4525353199 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_mode_ignore_cmds.3852842216 |
|
|
Sep 04 08:19:36 AM UTC 24 |
Sep 04 08:20:28 AM UTC 24 |
26712447870 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_alert_test.2209493807 |
|
|
Sep 04 08:20:27 AM UTC 24 |
Sep 04 08:20:29 AM UTC 24 |
24930020 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_read_buffer_direct.784319159 |
|
|
Sep 04 08:20:23 AM UTC 24 |
Sep 04 08:20:30 AM UTC 24 |
671702008 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_mode_ignore_cmds.2555802985 |
|
|
Sep 04 08:15:56 AM UTC 24 |
Sep 04 08:20:31 AM UTC 24 |
26759892660 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_csb_read.2068655369 |
|
|
Sep 04 08:20:29 AM UTC 24 |
Sep 04 08:20:31 AM UTC 24 |
194113210 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_cmd_filtering.1636753665 |
|
|
Sep 04 08:20:13 AM UTC 24 |
Sep 04 08:20:33 AM UTC 24 |
9505180663 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_sts_read.3611833435 |
|
|
Sep 04 08:20:31 AM UTC 24 |
Sep 04 08:20:34 AM UTC 24 |
286890741 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm_min_idle.141521613 |
|
|
Sep 04 08:19:18 AM UTC 24 |
Sep 04 08:20:34 AM UTC 24 |
13119522579 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_read_hw_reg.2103202548 |
|
|
Sep 04 08:20:30 AM UTC 24 |
Sep 04 08:20:35 AM UTC 24 |
266082559 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_mailbox.2171223424 |
|
|
Sep 04 08:20:16 AM UTC 24 |
Sep 04 08:20:35 AM UTC 24 |
2870647457 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_rw.3217341420 |
|
|
Sep 04 08:20:33 AM UTC 24 |
Sep 04 08:20:35 AM UTC 24 |
61146906 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_all.3838262360 |
|
|
Sep 04 08:20:31 AM UTC 24 |
Sep 04 08:20:38 AM UTC 24 |
378401122 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_cmd_filtering.613584841 |
|
|
Sep 04 08:20:33 AM UTC 24 |
Sep 04 08:20:40 AM UTC 24 |
6834944575 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_addr_payload_swap.1743736266 |
|
|
Sep 04 08:20:34 AM UTC 24 |
Sep 04 08:20:43 AM UTC 24 |
399622791 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm_min_idle.1485008900 |
|
|
Sep 04 08:20:26 AM UTC 24 |
Sep 04 08:20:43 AM UTC 24 |
3686881601 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm.1167917837 |
|
|
Sep 04 08:18:56 AM UTC 24 |
Sep 04 08:20:44 AM UTC 24 |
28610416865 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm_min_idle.3609766415 |
|
|
Sep 04 08:19:41 AM UTC 24 |
Sep 04 08:20:44 AM UTC 24 |
18748624970 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode.2086475370 |
|
|
Sep 04 08:20:37 AM UTC 24 |
Sep 04 08:20:45 AM UTC 24 |
740621645 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_cfg_cmd.2497677091 |
|
|
Sep 04 08:20:36 AM UTC 24 |
Sep 04 08:20:46 AM UTC 24 |
1937327424 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_alert_test.2978483391 |
|
|
Sep 04 08:20:46 AM UTC 24 |
Sep 04 08:20:48 AM UTC 24 |
15097373 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_all.3675715984 |
|
|
Sep 04 08:15:57 AM UTC 24 |
Sep 04 08:20:48 AM UTC 24 |
73945768087 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_upload.946947836 |
|
|
Sep 04 08:20:36 AM UTC 24 |
Sep 04 08:20:49 AM UTC 24 |
5258223511 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_csb_read.3859957245 |
|
|
Sep 04 08:20:47 AM UTC 24 |
Sep 04 08:20:49 AM UTC 24 |
23360805 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode_ignore_cmds.1262475805 |
|
|
Sep 04 08:20:19 AM UTC 24 |
Sep 04 08:20:51 AM UTC 24 |
2890581415 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_sts_read.167468925 |
|
|
Sep 04 08:20:51 AM UTC 24 |
Sep 04 08:20:53 AM UTC 24 |
20380733 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_stress_all.29370171 |
|
|
Sep 04 08:19:21 AM UTC 24 |
Sep 04 08:20:54 AM UTC 24 |
44158938582 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_cmd_filtering.2909977809 |
|
|
Sep 04 08:20:52 AM UTC 24 |
Sep 04 08:20:56 AM UTC 24 |
114458267 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_mode_ignore_cmds.1961258184 |
|
|
Sep 04 08:18:03 AM UTC 24 |
Sep 04 08:20:57 AM UTC 24 |
37198972242 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_rw.138495979 |
|
|
Sep 04 08:20:51 AM UTC 24 |
Sep 04 08:20:58 AM UTC 24 |
154734940 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_read_buffer_direct.536705231 |
|
|
Sep 04 08:20:41 AM UTC 24 |
Sep 04 08:20:58 AM UTC 24 |
1109130725 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_all.1549269303 |
|
|
Sep 04 08:19:18 AM UTC 24 |
Sep 04 08:20:59 AM UTC 24 |
34443621719 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_addr_payload_swap.4215780771 |
|
|
Sep 04 08:20:54 AM UTC 24 |
Sep 04 08:21:00 AM UTC 24 |
491049876 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_intercept.3621926919 |
|
|
Sep 04 08:20:35 AM UTC 24 |
Sep 04 08:21:02 AM UTC 24 |
2475533749 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode_ignore_cmds.2373460727 |
|
|
Sep 04 08:21:00 AM UTC 24 |
Sep 04 08:21:02 AM UTC 24 |
17077205 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_intercept.3181139516 |
|
|
Sep 04 08:20:55 AM UTC 24 |
Sep 04 08:21:04 AM UTC 24 |
180423970 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_mailbox.697105425 |
|
|
Sep 04 08:20:57 AM UTC 24 |
Sep 04 08:21:05 AM UTC 24 |
327436088 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_cfg_cmd.1502945430 |
|
|
Sep 04 08:20:59 AM UTC 24 |
Sep 04 08:21:06 AM UTC 24 |
229757593 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_read_hw_reg.3646446283 |
|
|
Sep 04 08:20:49 AM UTC 24 |
Sep 04 08:21:06 AM UTC 24 |
39134996393 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode.2303742767 |
|
|
Sep 04 08:20:59 AM UTC 24 |
Sep 04 08:21:07 AM UTC 24 |
359669097 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_read_buffer_direct.4007360449 |
|
|
Sep 04 08:21:01 AM UTC 24 |
Sep 04 08:21:07 AM UTC 24 |
377474950 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_alert_test.1563131517 |
|
|
Sep 04 08:21:07 AM UTC 24 |
Sep 04 08:21:09 AM UTC 24 |
17651507 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_csb_read.215441011 |
|
|
Sep 04 08:21:07 AM UTC 24 |
Sep 04 08:21:09 AM UTC 24 |
33764057 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_sts_read.3464651364 |
|
|
Sep 04 08:21:10 AM UTC 24 |
Sep 04 08:21:12 AM UTC 24 |
106152052 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_rw.2556939506 |
|
|
Sep 04 08:21:10 AM UTC 24 |
Sep 04 08:21:13 AM UTC 24 |
260576499 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_read_hw_reg.2297382459 |
|
|
Sep 04 08:21:08 AM UTC 24 |
Sep 04 08:21:14 AM UTC 24 |
730910168 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.3235455136 |
|
|
Sep 04 08:07:45 AM UTC 24 |
Sep 04 08:21:17 AM UTC 24 |
339238758140 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_addr_payload_swap.1400214278 |
|
|
Sep 04 08:21:14 AM UTC 24 |
Sep 04 08:21:22 AM UTC 24 |
133775824 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_cmd_filtering.2095570334 |
|
|
Sep 04 08:21:13 AM UTC 24 |
Sep 04 08:21:23 AM UTC 24 |
4773107327 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_mode_ignore_cmds.1202223176 |
|
|
Sep 04 08:19:17 AM UTC 24 |
Sep 04 08:21:23 AM UTC 24 |
23102457785 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_all.3923710125 |
|
|
Sep 04 08:20:49 AM UTC 24 |
Sep 04 08:21:27 AM UTC 24 |
1747354777 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_all.1538115613 |
|
|
Sep 04 08:20:44 AM UTC 24 |
Sep 04 08:21:28 AM UTC 24 |
11185328175 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode.3552715584 |
|
|
Sep 04 08:21:25 AM UTC 24 |
Sep 04 08:21:29 AM UTC 24 |
33445149 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_intercept.2469063027 |
|
|
Sep 04 08:21:15 AM UTC 24 |
Sep 04 08:21:30 AM UTC 24 |
878748867 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_mailbox.1221491432 |
|
|
Sep 04 08:20:36 AM UTC 24 |
Sep 04 08:21:30 AM UTC 24 |
8534225992 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_stress_all.581145752 |
|
|
Sep 04 08:15:02 AM UTC 24 |
Sep 04 08:21:31 AM UTC 24 |
30801658278 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_upload.1159183694 |
|
|
Sep 04 08:20:59 AM UTC 24 |
Sep 04 08:21:31 AM UTC 24 |
47889471378 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_all.3400832430 |
|
|
Sep 04 08:20:05 AM UTC 24 |
Sep 04 08:21:31 AM UTC 24 |
7849740797 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_cfg_cmd.478790279 |
|
|
Sep 04 08:21:24 AM UTC 24 |
Sep 04 08:21:31 AM UTC 24 |
355087889 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_and_tpm.3944850518 |
|
|
Sep 04 08:18:27 AM UTC 24 |
Sep 04 08:21:32 AM UTC 24 |
17665143504 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_alert_test.2613537016 |
|
|
Sep 04 08:21:32 AM UTC 24 |
Sep 04 08:21:35 AM UTC 24 |
43884103 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_csb_read.1762933366 |
|
|
Sep 04 08:21:32 AM UTC 24 |
Sep 04 08:21:35 AM UTC 24 |
101654009 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_stress_all.3405969871 |
|
|
Sep 04 08:21:32 AM UTC 24 |
Sep 04 08:21:35 AM UTC 24 |
110994554 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_read_hw_reg.3271567023 |
|
|
Sep 04 08:21:33 AM UTC 24 |
Sep 04 08:21:36 AM UTC 24 |
90177762 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_stress_all.3182805832 |
|
|
Sep 04 08:18:08 AM UTC 24 |
Sep 04 08:21:36 AM UTC 24 |
21203840050 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm.1074575798 |
|
|
Sep 04 08:20:06 AM UTC 24 |
Sep 04 08:21:37 AM UTC 24 |
43867987013 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_sts_read.99624038 |
|
|
Sep 04 08:21:36 AM UTC 24 |
Sep 04 08:21:39 AM UTC 24 |
147118634 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_read_buffer_direct.2192169749 |
|
|
Sep 04 08:21:29 AM UTC 24 |
Sep 04 08:21:39 AM UTC 24 |
869654575 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_rw.1463942166 |
|
|
Sep 04 08:21:36 AM UTC 24 |
Sep 04 08:21:42 AM UTC 24 |
535410695 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_all.27571195 |
|
|
Sep 04 08:21:08 AM UTC 24 |
Sep 04 08:21:43 AM UTC 24 |
15789290567 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm_min_idle.3131678039 |
|
|
Sep 04 08:21:06 AM UTC 24 |
Sep 04 08:21:44 AM UTC 24 |
4709145079 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_cfg_cmd.764816693 |
|
|
Sep 04 08:21:40 AM UTC 24 |
Sep 04 08:21:45 AM UTC 24 |
247153404 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_cmd_filtering.1397439451 |
|
|
Sep 04 08:21:36 AM UTC 24 |
Sep 04 08:21:45 AM UTC 24 |
847457932 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_intercept.1902985714 |
|
|
Sep 04 08:21:38 AM UTC 24 |
Sep 04 08:21:46 AM UTC 24 |
209126061 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_stress_all.1539966843 |
|
|
Sep 04 08:19:43 AM UTC 24 |
Sep 04 08:21:51 AM UTC 24 |
16259629803 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_read_buffer_direct.877741236 |
|
|
Sep 04 08:21:45 AM UTC 24 |
Sep 04 08:21:52 AM UTC 24 |
469856377 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_alert_test.1545917029 |
|
|
Sep 04 08:21:53 AM UTC 24 |
Sep 04 08:21:55 AM UTC 24 |
40036697 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm.3991998186 |
|
|
Sep 04 08:20:45 AM UTC 24 |
Sep 04 08:21:57 AM UTC 24 |
20253027697 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_csb_read.2110013321 |
|
|
Sep 04 08:21:56 AM UTC 24 |
Sep 04 08:21:58 AM UTC 24 |
20483023 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_all.3486430472 |
|
|
Sep 04 08:21:34 AM UTC 24 |
Sep 04 08:22:00 AM UTC 24 |
3063659037 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_mailbox.655497102 |
|
|
Sep 04 08:21:17 AM UTC 24 |
Sep 04 08:22:00 AM UTC 24 |
18456211970 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm.2757266424 |
|
|
Sep 04 08:21:47 AM UTC 24 |
Sep 04 08:22:01 AM UTC 24 |
938814801 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_addr_payload_swap.3740904693 |
|
|
Sep 04 08:21:36 AM UTC 24 |
Sep 04 08:22:01 AM UTC 24 |
6864428791 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_sts_read.3894129357 |
|
|
Sep 04 08:22:00 AM UTC 24 |
Sep 04 08:22:03 AM UTC 24 |
132751476 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode.151722662 |
|
|
Sep 04 08:21:43 AM UTC 24 |
Sep 04 08:22:03 AM UTC 24 |
887575165 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_rw.2200131840 |
|
|
Sep 04 08:22:02 AM UTC 24 |
Sep 04 08:22:05 AM UTC 24 |
67898698 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_upload.3056449496 |
|
|
Sep 04 08:21:40 AM UTC 24 |
Sep 04 08:22:05 AM UTC 24 |
4769338272 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_all.597191856 |
|
|
Sep 04 08:21:59 AM UTC 24 |
Sep 04 08:22:07 AM UTC 24 |
1957941202 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_and_tpm.1702104656 |
|
|
Sep 04 08:17:23 AM UTC 24 |
Sep 04 08:22:09 AM UTC 24 |
27359419873 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_all.3129063478 |
|
|
Sep 04 08:22:11 AM UTC 24 |
Sep 04 08:23:57 AM UTC 24 |
25486646817 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_read_hw_reg.1292799256 |
|
|
Sep 04 08:21:58 AM UTC 24 |
Sep 04 08:22:10 AM UTC 24 |
1536373220 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_intercept.78552847 |
|
|
Sep 04 08:22:03 AM UTC 24 |
Sep 04 08:22:10 AM UTC 24 |
153067853 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_cfg_cmd.2043164262 |
|
|
Sep 04 08:22:07 AM UTC 24 |
Sep 04 08:22:11 AM UTC 24 |
206206843 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_addr_payload_swap.3533107687 |
|
|
Sep 04 08:22:03 AM UTC 24 |
Sep 04 08:22:13 AM UTC 24 |
212440465 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode.3367529330 |
|
|
Sep 04 08:22:08 AM UTC 24 |
Sep 04 08:22:15 AM UTC 24 |
103926165 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode_ignore_cmds.3967917488 |
|
|
Sep 04 08:21:27 AM UTC 24 |
Sep 04 08:22:16 AM UTC 24 |
4077124659 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_upload.1404522450 |
|
|
Sep 04 08:21:23 AM UTC 24 |
Sep 04 08:22:16 AM UTC 24 |
65996930146 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_mode_ignore_cmds.384674627 |
|
|
Sep 04 08:18:49 AM UTC 24 |
Sep 04 08:22:18 AM UTC 24 |
98904317104 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_stress_all.1765441606 |
|
|
Sep 04 08:22:16 AM UTC 24 |
Sep 04 08:22:18 AM UTC 24 |
32916787 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_mailbox.3441107751 |
|
|
Sep 04 08:22:04 AM UTC 24 |
Sep 04 08:22:19 AM UTC 24 |
5056041855 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_cmd_filtering.4037825633 |
|
|
Sep 04 08:22:02 AM UTC 24 |
Sep 04 08:22:19 AM UTC 24 |
6129446726 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_alert_test.2474638660 |
|
|
Sep 04 08:22:17 AM UTC 24 |
Sep 04 08:22:19 AM UTC 24 |
39707025 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_csb_read.819901119 |
|
|
Sep 04 08:22:17 AM UTC 24 |
Sep 04 08:22:19 AM UTC 24 |
18218745 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_and_tpm.2627410771 |
|
|
Sep 04 08:15:19 AM UTC 24 |
Sep 04 08:22:21 AM UTC 24 |
34238918565 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm.3578293059 |
|
|
Sep 04 08:18:05 AM UTC 24 |
Sep 04 08:22:22 AM UTC 24 |
14758158010 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_read_buffer_direct.251546292 |
|
|
Sep 04 08:22:10 AM UTC 24 |
Sep 04 08:22:22 AM UTC 24 |
1566280730 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_rw.3971856850 |
|
|
Sep 04 08:22:20 AM UTC 24 |
Sep 04 08:22:22 AM UTC 24 |
40581233 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_sts_read.2209207950 |
|
|
Sep 04 08:22:20 AM UTC 24 |
Sep 04 08:22:22 AM UTC 24 |
67095312 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_all.643813628 |
|
|
Sep 04 08:22:20 AM UTC 24 |
Sep 04 08:22:24 AM UTC 24 |
1195206369 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_addr_payload_swap.782433758 |
|
|
Sep 04 08:22:20 AM UTC 24 |
Sep 04 08:22:25 AM UTC 24 |
254151387 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm_min_idle.1673096342 |
|
|
Sep 04 08:21:31 AM UTC 24 |
Sep 04 08:22:26 AM UTC 24 |
1525700067 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_upload.1258040671 |
|
|
Sep 04 08:22:23 AM UTC 24 |
Sep 04 08:22:30 AM UTC 24 |
261580114 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_upload.2847771734 |
|
|
Sep 04 08:22:05 AM UTC 24 |
Sep 04 08:22:30 AM UTC 24 |
20633137658 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_mailbox.859211082 |
|
|
Sep 04 08:21:38 AM UTC 24 |
Sep 04 08:22:31 AM UTC 24 |
38086469082 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_read_hw_reg.315581 |
|
|
Sep 04 08:22:20 AM UTC 24 |
Sep 04 08:22:32 AM UTC 24 |
15275952154 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode.2942952962 |
|
|
Sep 04 08:22:24 AM UTC 24 |
Sep 04 08:22:35 AM UTC 24 |
1091034045 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_read_buffer_direct.4209600853 |
|
|
Sep 04 08:22:26 AM UTC 24 |
Sep 04 08:22:35 AM UTC 24 |
717690401 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_alert_test.3061644311 |
|
|
Sep 04 08:22:32 AM UTC 24 |
Sep 04 08:22:35 AM UTC 24 |
46582380 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_cfg_cmd.3199336624 |
|
|
Sep 04 08:22:24 AM UTC 24 |
Sep 04 08:22:36 AM UTC 24 |
895836789 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_csb_read.331662839 |
|
|
Sep 04 08:22:36 AM UTC 24 |
Sep 04 08:22:38 AM UTC 24 |
62632649 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_sts_read.2166401188 |
|
|
Sep 04 08:22:37 AM UTC 24 |
Sep 04 08:22:39 AM UTC 24 |
29794542 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm.2190449834 |
|
|
Sep 04 08:21:03 AM UTC 24 |
Sep 04 08:22:39 AM UTC 24 |
32595492886 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_rw.2937431539 |
|
|
Sep 04 08:22:39 AM UTC 24 |
Sep 04 08:22:42 AM UTC 24 |
24971819 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_all.196311874 |
|
|
Sep 04 08:20:23 AM UTC 24 |
Sep 04 08:22:42 AM UTC 24 |
68113536714 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_stress_all.1312839527 |
|
|
Sep 04 08:20:08 AM UTC 24 |
Sep 04 08:22:43 AM UTC 24 |
11557204400 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_read_hw_reg.355475443 |
|
|
Sep 04 08:22:36 AM UTC 24 |
Sep 04 08:22:43 AM UTC 24 |
793896126 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_upload.2382161070 |
|
|
Sep 04 08:22:44 AM UTC 24 |
Sep 04 08:22:49 AM UTC 24 |
151479887 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_stress_all.2303663146 |
|
|
Sep 04 08:17:09 AM UTC 24 |
Sep 04 08:22:50 AM UTC 24 |
151644934463 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_cfg_cmd.1112630553 |
|
|
Sep 04 08:22:44 AM UTC 24 |
Sep 04 08:22:51 AM UTC 24 |
189025672 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_cmd_filtering.3022222159 |
|
|
Sep 04 08:22:20 AM UTC 24 |
Sep 04 08:22:51 AM UTC 24 |
17618807621 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_addr_payload_swap.169919545 |
|
|
Sep 04 08:22:41 AM UTC 24 |
Sep 04 08:22:54 AM UTC 24 |
1591964534 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_all.1441830114 |
|
|
Sep 04 08:22:52 AM UTC 24 |
Sep 04 08:22:55 AM UTC 24 |
22569715 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode.2905378686 |
|
|
Sep 04 08:22:50 AM UTC 24 |
Sep 04 08:22:56 AM UTC 24 |
573382120 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_cmd_filtering.2870905533 |
|
|
Sep 04 08:22:41 AM UTC 24 |
Sep 04 08:22:59 AM UTC 24 |
5028036004 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_read_buffer_direct.2091579350 |
|
|
Sep 04 08:22:52 AM UTC 24 |
Sep 04 08:23:00 AM UTC 24 |
127614726 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm_min_idle.2264687472 |
|
|
Sep 04 08:22:31 AM UTC 24 |
Sep 04 08:23:01 AM UTC 24 |
17822206042 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_alert_test.2966836564 |
|
|
Sep 04 08:23:00 AM UTC 24 |
Sep 04 08:23:02 AM UTC 24 |
38199742 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_stress_all.1422936550 |
|
|
Sep 04 08:17:24 AM UTC 24 |
Sep 04 08:23:02 AM UTC 24 |
26114456227 ps |
| T194 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_stress_all.956013725 |
|
|
Sep 04 08:13:32 AM UTC 24 |
Sep 04 08:23:05 AM UTC 24 |
105448315760 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_intercept.2492747256 |
|
|
Sep 04 08:22:43 AM UTC 24 |
Sep 04 08:23:06 AM UTC 24 |
2421161952 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_mailbox.1138732680 |
|
|
Sep 04 08:22:43 AM UTC 24 |
Sep 04 08:23:07 AM UTC 24 |
1255939967 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode_ignore_cmds.3177960694 |
|
|
Sep 04 08:22:10 AM UTC 24 |
Sep 04 08:23:09 AM UTC 24 |
6390985931 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_stress_all.3281271221 |
|
|
Sep 04 08:17:37 AM UTC 24 |
Sep 04 08:23:10 AM UTC 24 |
168028944009 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_intercept.1852806174 |
|
|
Sep 04 08:22:23 AM UTC 24 |
Sep 04 08:23:12 AM UTC 24 |
20417449091 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_all.2288276779 |
|
|
Sep 04 08:22:36 AM UTC 24 |
Sep 04 08:23:14 AM UTC 24 |
4933678547 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_stress_all.3610754699 |
|
|
Sep 04 08:22:32 AM UTC 24 |
Sep 04 08:23:15 AM UTC 24 |
4967704214 ps |
| T171 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm_min_idle.3269709764 |
|
|
Sep 04 08:18:06 AM UTC 24 |
Sep 04 08:23:19 AM UTC 24 |
139736592852 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_mailbox.2825369721 |
|
|
Sep 04 08:22:23 AM UTC 24 |
Sep 04 08:23:19 AM UTC 24 |
3699071625 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm.1112215528 |
|
|
Sep 04 08:22:13 AM UTC 24 |
Sep 04 08:23:31 AM UTC 24 |
20673213672 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_all.170566950 |
|
|
Sep 04 08:12:02 AM UTC 24 |
Sep 04 08:23:36 AM UTC 24 |
147263347901 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm_min_idle.1862254461 |
|
|
Sep 04 08:20:06 AM UTC 24 |
Sep 04 08:23:51 AM UTC 24 |
27996146656 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm_min_idle.3074588197 |
|
|
Sep 04 08:22:14 AM UTC 24 |
Sep 04 08:23:57 AM UTC 24 |
10781888119 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_and_tpm.2492691947 |
|
|
Sep 04 08:17:08 AM UTC 24 |
Sep 04 08:24:08 AM UTC 24 |
170741837384 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm.1453748389 |
|
|
Sep 04 08:21:31 AM UTC 24 |
Sep 04 08:24:14 AM UTC 24 |
15404790505 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_and_tpm.1586994160 |
|
|
Sep 04 08:16:23 AM UTC 24 |
Sep 04 08:24:16 AM UTC 24 |
231057597193 ps |
| T172 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_stress_all.1768116671 |
|
|
Sep 04 08:21:51 AM UTC 24 |
Sep 04 08:24:17 AM UTC 24 |
30992566909 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_all.2763373955 |
|
|
Sep 04 08:21:47 AM UTC 24 |
Sep 04 08:24:30 AM UTC 24 |
63526546121 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_all.3443113513 |
|
|
Sep 04 08:21:02 AM UTC 24 |
Sep 04 08:24:36 AM UTC 24 |
116295249290 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode_ignore_cmds.3093642113 |
|
|
Sep 04 08:21:45 AM UTC 24 |
Sep 04 08:24:38 AM UTC 24 |
71402629668 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode_ignore_cmds.3341787447 |
|
|
Sep 04 08:22:51 AM UTC 24 |
Sep 04 08:24:43 AM UTC 24 |
26279929583 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_stress_all.2294555819 |
|
|
Sep 04 08:18:58 AM UTC 24 |
Sep 04 08:24:46 AM UTC 24 |
406009984430 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_mode_ignore_cmds.2028498387 |
|
|
Sep 04 08:13:26 AM UTC 24 |
Sep 04 08:24:58 AM UTC 24 |
97269242374 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_stress_all.1748466433 |
|
|
Sep 04 08:22:57 AM UTC 24 |
Sep 04 08:25:03 AM UTC 24 |
9441429771 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm_min_idle.1607475790 |
|
|
Sep 04 08:22:56 AM UTC 24 |
Sep 04 08:25:14 AM UTC 24 |
83290851169 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm_min_idle.2116183596 |
|
|
Sep 04 08:20:45 AM UTC 24 |
Sep 04 08:25:16 AM UTC 24 |
90115665530 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_all.3432093352 |
|
|
Sep 04 08:19:39 AM UTC 24 |
Sep 04 08:25:18 AM UTC 24 |
469862703005 ps |
| T85 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm.3827794609 |
|
|
Sep 04 08:22:31 AM UTC 24 |
Sep 04 08:25:21 AM UTC 24 |
29567606753 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm_min_idle.3557005825 |
|
|
Sep 04 08:21:47 AM UTC 24 |
Sep 04 08:25:27 AM UTC 24 |
61166898010 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode_ignore_cmds.3641750085 |
|
|
Sep 04 08:20:04 AM UTC 24 |
Sep 04 08:25:28 AM UTC 24 |
42220297440 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_stress_all.3463975337 |
|
|
Sep 04 08:08:35 AM UTC 24 |
Sep 04 08:25:28 AM UTC 24 |
213766794878 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_and_tpm_min_idle.1532382782 |
|
|
Sep 04 08:17:24 AM UTC 24 |
Sep 04 08:25:30 AM UTC 24 |
166781160105 ps |
| T195 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_stress_all.1831846545 |
|
|
Sep 04 08:20:46 AM UTC 24 |
Sep 04 08:25:40 AM UTC 24 |
100410165352 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_and_tpm_min_idle.2064246203 |
|
|
Sep 04 08:17:35 AM UTC 24 |
Sep 04 08:25:42 AM UTC 24 |
421837604681 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_and_tpm.1026679739 |
|
|
Sep 04 08:15:00 AM UTC 24 |
Sep 04 08:25:48 AM UTC 24 |
418935508770 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_all.770969556 |
|
|
Sep 04 08:21:31 AM UTC 24 |
Sep 04 08:26:06 AM UTC 24 |
36246036807 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_stress_all.101543501 |
|
|
Sep 04 08:16:07 AM UTC 24 |
Sep 04 08:26:31 AM UTC 24 |
45764495159 ps |
| T1008 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm.2032566876 |
|
|
Sep 04 08:22:56 AM UTC 24 |
Sep 04 08:26:48 AM UTC 24 |
123318550801 ps |
| T1009 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_all.812976356 |
|
|
Sep 04 08:22:27 AM UTC 24 |
Sep 04 08:27:57 AM UTC 24 |
35692289236 ps |
| T1010 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_stress_all.921727288 |
|
|
Sep 04 08:20:26 AM UTC 24 |
Sep 04 08:28:19 AM UTC 24 |
45594152906 ps |
| T196 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_stress_all.888335342 |
|
|
Sep 04 08:18:29 AM UTC 24 |
Sep 04 08:29:26 AM UTC 24 |
130613057376 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode_ignore_cmds.1721941322 |
|
|
Sep 04 08:22:26 AM UTC 24 |
Sep 04 08:31:15 AM UTC 24 |
248089919239 ps |
| T86 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm.2360991403 |
|
|
Sep 04 08:20:24 AM UTC 24 |
Sep 04 08:31:42 AM UTC 24 |
148147702355 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_stress_all.1729078630 |
|
|
Sep 04 08:14:23 AM UTC 24 |
Sep 04 08:32:28 AM UTC 24 |
1090765963265 ps |
| T1011 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode_ignore_cmds.2795337411 |
|
|
Sep 04 08:20:39 AM UTC 24 |
Sep 04 08:32:37 AM UTC 24 |
181395058185 ps |
| T1012 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_stress_all.3269728758 |
|
|
Sep 04 08:11:04 AM UTC 24 |
Sep 04 08:32:53 AM UTC 24 |
125851895383 ps |
| T87 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_stress_all.3066718541 |
|
|
Sep 04 08:21:06 AM UTC 24 |
Sep 04 08:34:38 AM UTC 24 |
181191419934 ps |
| T1013 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.619832770 |
|
|
Sep 04 06:21:10 AM UTC 24 |
Sep 04 06:21:11 AM UTC 24 |
13070042 ps |
| T1014 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.2762077805 |
|
|
Sep 04 06:21:09 AM UTC 24 |
Sep 04 06:21:11 AM UTC 24 |
33754506 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.4142255121 |
|
|
Sep 04 06:21:10 AM UTC 24 |
Sep 04 06:21:12 AM UTC 24 |
39814304 ps |
| T148 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.563044225 |
|
|
Sep 04 06:21:10 AM UTC 24 |
Sep 04 06:21:13 AM UTC 24 |
198005503 ps |
| T149 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.2333654776 |
|
|
Sep 04 06:21:10 AM UTC 24 |
Sep 04 06:21:13 AM UTC 24 |
74068491 ps |
| T173 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3876552079 |
|
|
Sep 04 06:21:10 AM UTC 24 |
Sep 04 06:21:13 AM UTC 24 |
63307011 ps |
| T1015 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.331850194 |
|
|
Sep 04 06:21:12 AM UTC 24 |
Sep 04 06:21:14 AM UTC 24 |
64120800 ps |
| T1016 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.3049936997 |
|
|
Sep 04 06:21:12 AM UTC 24 |
Sep 04 06:21:14 AM UTC 24 |
46942463 ps |
| T104 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.486530474 |
|
|
Sep 04 06:21:12 AM UTC 24 |
Sep 04 06:21:14 AM UTC 24 |
93439362 ps |
| T1017 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_intr_test.4018935171 |
|
|
Sep 04 06:21:12 AM UTC 24 |
Sep 04 06:21:15 AM UTC 24 |
11558807 ps |
| T1018 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_walk.2003306082 |
|
|
Sep 04 06:21:12 AM UTC 24 |
Sep 04 06:21:15 AM UTC 24 |
24124589 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.858246163 |
|
|
Sep 04 06:21:12 AM UTC 24 |
Sep 04 06:21:15 AM UTC 24 |
22896474 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.643037380 |
|
|
Sep 04 06:21:09 AM UTC 24 |
Sep 04 06:21:15 AM UTC 24 |
208926664 ps |
| T150 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.1577352662 |
|
|
Sep 04 06:21:12 AM UTC 24 |
Sep 04 06:21:15 AM UTC 24 |
58187112 ps |
| T106 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.1537500906 |
|
|
Sep 04 06:21:12 AM UTC 24 |
Sep 04 06:21:16 AM UTC 24 |
449771614 ps |
| T151 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.3714232812 |
|
|
Sep 04 06:21:12 AM UTC 24 |
Sep 04 06:21:16 AM UTC 24 |
559808084 ps |
| T174 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1041421944 |
|
|
Sep 04 06:21:12 AM UTC 24 |
Sep 04 06:21:17 AM UTC 24 |
180866633 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2440586383 |
|
|
Sep 04 06:21:14 AM UTC 24 |
Sep 04 06:21:17 AM UTC 24 |
158637824 ps |
| T152 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_rw.1328933979 |
|
|
Sep 04 06:21:14 AM UTC 24 |
Sep 04 06:21:17 AM UTC 24 |
81618474 ps |
| T153 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_partial_access.678517367 |
|
|
Sep 04 06:21:14 AM UTC 24 |
Sep 04 06:21:17 AM UTC 24 |
49332890 ps |
| T1019 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_walk.782380415 |
|
|
Sep 04 06:21:16 AM UTC 24 |
Sep 04 06:21:18 AM UTC 24 |
31591914 ps |
| T1020 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_intr_test.3157628392 |
|
|
Sep 04 06:21:15 AM UTC 24 |
Sep 04 06:21:18 AM UTC 24 |
27148784 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1166802047 |
|
|
Sep 04 06:21:12 AM UTC 24 |
Sep 04 06:21:18 AM UTC 24 |
932233450 ps |
| T1021 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_partial_access.1085538751 |
|
|
Sep 04 06:21:16 AM UTC 24 |
Sep 04 06:21:18 AM UTC 24 |
63903444 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1073562667 |
|
|
Sep 04 06:21:16 AM UTC 24 |
Sep 04 06:21:18 AM UTC 24 |
49990227 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.730055378 |
|
|
Sep 04 06:21:14 AM UTC 24 |
Sep 04 06:21:18 AM UTC 24 |
160607336 ps |
| T180 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_rw.4135779376 |
|
|
Sep 04 06:21:16 AM UTC 24 |
Sep 04 06:21:19 AM UTC 24 |
49541844 ps |
| T1022 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3183822292 |
|
|
Sep 04 06:21:14 AM UTC 24 |
Sep 04 06:21:19 AM UTC 24 |
56715811 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.3845478521 |
|
|
Sep 04 06:21:12 AM UTC 24 |
Sep 04 06:21:19 AM UTC 24 |
245408043 ps |
| T1023 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_intr_test.952437576 |
|
|
Sep 04 06:21:18 AM UTC 24 |
Sep 04 06:21:20 AM UTC 24 |
16848478 ps |
| T143 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1865464549 |
|
|
Sep 04 06:21:17 AM UTC 24 |
Sep 04 06:21:20 AM UTC 24 |
25183784 ps |
| T1024 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_walk.2033685722 |
|
|
Sep 04 06:21:18 AM UTC 24 |
Sep 04 06:21:20 AM UTC 24 |
44925496 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_errors.314286430 |
|
|
Sep 04 06:21:14 AM UTC 24 |
Sep 04 06:21:20 AM UTC 24 |
148463400 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3980786563 |
|
|
Sep 04 06:21:18 AM UTC 24 |
Sep 04 06:21:21 AM UTC 24 |
24199853 ps |
| T154 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_aliasing.1409961612 |
|
|
Sep 04 06:21:17 AM UTC 24 |
Sep 04 06:21:34 AM UTC 24 |
393452314 ps |
| T159 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_partial_access.2976976465 |
|
|
Sep 04 06:21:18 AM UTC 24 |
Sep 04 06:21:21 AM UTC 24 |
43854116 ps |
| T155 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_rw.2298089470 |
|
|
Sep 04 06:21:18 AM UTC 24 |
Sep 04 06:21:21 AM UTC 24 |
23023255 ps |
| T1025 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3472380087 |
|
|
Sep 04 06:21:17 AM UTC 24 |
Sep 04 06:21:21 AM UTC 24 |
46884189 ps |
| T1026 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_intr_test.773419121 |
|
|
Sep 04 06:21:21 AM UTC 24 |
Sep 04 06:21:23 AM UTC 24 |
13366686 ps |
| T1027 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.945398410 |
|
|
Sep 04 06:21:19 AM UTC 24 |
Sep 04 06:21:24 AM UTC 24 |
165034999 ps |
| T156 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_rw.2951926571 |
|
|
Sep 04 06:21:21 AM UTC 24 |
Sep 04 06:21:24 AM UTC 24 |
439259026 ps |
| T1028 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.4275648160 |
|
|
Sep 04 06:21:21 AM UTC 24 |
Sep 04 06:21:24 AM UTC 24 |
228141873 ps |
| T1029 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_intr_test.3403049840 |
|
|
Sep 04 06:21:22 AM UTC 24 |
Sep 04 06:21:24 AM UTC 24 |
11778872 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_intg_err.1130773288 |
|
|
Sep 04 06:21:12 AM UTC 24 |
Sep 04 06:21:24 AM UTC 24 |
798752010 ps |
| T144 |
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3576521207 |
|
|
Sep 04 06:21:19 AM UTC 24 |
Sep 04 06:21:25 AM UTC 24 |
2315004895 ps |