Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3688989	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4293255

1

T1

1010

T2

1

T3

889

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4429560	1			T1	209		T2	43		T3	18
values[0x0]	1773610	1			T1	455		T3	436		T4	131
values[0x1]	1779074	1			T1	445		T3	447		T4	148

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2614257	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5367987

1

T1

1026

T2

17

T3

890

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29177	1			T3	3		T4	3		T6	212
valid_sources[0x01]	40506	1			T2	2		T3	9		T6	68
valid_sources[0x02]	27988	1			T3	5		T4	4		T9	3
valid_sources[0x03]	28780	1			T2	1		T3	1		T4	7
valid_sources[0x04]	30922	1			T2	2		T3	4		T4	6
valid_sources[0x05]	27865	1			T3	4		T4	2		T9	5
valid_sources[0x06]	33033	1			T3	4		T9	4		T27	2
valid_sources[0x07]	37408	1			T3	6		T9	10		T10	6
valid_sources[0x08]	28991	1			T3	2		T4	5		T9	3
valid_sources[0x09]	30199	1			T3	6		T4	2		T8	13
valid_sources[0x0a]	29372	1			T4	4		T6	24		T9	4
valid_sources[0x0b]	29556	1			T3	3		T4	5		T10	7
valid_sources[0x0c]	31969	1			T3	4		T4	4		T6	1
valid_sources[0x0d]	38486	1			T3	1		T9	5		T10	2
valid_sources[0x0e]	28816	1			T2	1		T3	1		T4	2
valid_sources[0x0f]	31045	1			T3	3		T4	6		T9	7
valid_sources[0x10]	32355	1			T3	1		T4	5		T9	5
valid_sources[0x11]	31943	1			T3	1		T9	8		T12	2
valid_sources[0x12]	33575	1			T2	1		T3	4		T4	4
valid_sources[0x13]	30353	1			T3	5		T9	6		T10	4
valid_sources[0x14]	31770	1			T3	7		T4	7		T9	9
valid_sources[0x15]	31252	1			T3	5		T4	3		T9	5
valid_sources[0x16]	50461	1			T3	5		T4	1		T8	1
valid_sources[0x17]	30598	1			T3	9		T4	2		T9	3
valid_sources[0x18]	30324	1			T3	1		T4	2		T9	5
valid_sources[0x19]	32004	1			T3	4		T4	4		T9	1
valid_sources[0x1a]	28843	1			T3	2		T4	2		T9	7
valid_sources[0x1b]	31808	1			T3	5		T4	3		T9	4
valid_sources[0x1c]	29870	1			T3	5		T4	1		T9	12
valid_sources[0x1d]	32879	1			T3	4		T4	6		T9	4
valid_sources[0x1e]	31176	1			T2	1		T3	7		T4	5
valid_sources[0x1f]	49651	1			T2	2		T3	7		T4	1
valid_sources[0x20]	31366	1			T3	4		T4	8		T9	6
valid_sources[0x21]	29009	1			T3	3		T4	3		T6	9
valid_sources[0x22]	30774	1			T3	10		T9	6		T10	2
valid_sources[0x23]	28395	1			T4	3		T9	2		T12	2
valid_sources[0x24]	26923	1			T3	2		T4	1		T7	416
valid_sources[0x25]	29101	1			T2	1		T3	2		T9	5
valid_sources[0x26]	30074	1			T3	1		T4	1		T9	4
valid_sources[0x27]	29982	1			T3	12		T4	4		T9	11
valid_sources[0x28]	29565	1			T3	2		T4	3		T9	4
valid_sources[0x29]	30355	1			T3	2		T4	4		T9	5
valid_sources[0x2a]	33911	1			T3	2		T4	5		T6	384
valid_sources[0x2b]	30935	1			T3	3		T4	2		T9	6
valid_sources[0x2c]	34437	1			T3	2		T4	3		T9	6
valid_sources[0x2d]	29066	1			T1	1		T3	1		T4	1
valid_sources[0x2e]	30923	1			T3	3		T9	7		T10	2
valid_sources[0x2f]	31323	1			T1	655		T4	2		T9	8
valid_sources[0x30]	30795	1			T3	2		T4	3		T9	4
valid_sources[0x31]	31469	1			T2	2		T3	2		T4	4
valid_sources[0x32]	31181	1			T3	3		T4	4		T9	4
valid_sources[0x33]	29494	1			T3	6		T4	5		T9	8
valid_sources[0x34]	27740	1			T3	5		T4	2		T6	1
valid_sources[0x35]	36384	1			T3	3		T4	2		T9	4
valid_sources[0x36]	27781	1			T3	1		T4	7		T9	11
valid_sources[0x37]	30099	1			T3	6		T4	1		T9	4
valid_sources[0x38]	30601	1			T2	1		T3	5		T4	1
valid_sources[0x39]	29436	1			T3	8		T4	2		T9	4
valid_sources[0x3a]	33012	1			T1	452		T3	5		T4	1
valid_sources[0x3b]	30302	1			T3	6		T9	8		T10	7
valid_sources[0x3c]	29686	1			T2	1		T3	1		T4	1
valid_sources[0x3d]	29672	1			T3	7		T4	8		T9	5
valid_sources[0x3e]	28141	1			T3	5		T4	2		T9	10
valid_sources[0x3f]	28522	1			T4	7		T9	7		T10	2
valid_sources[0x40]	27818	1			T3	2		T4	3		T9	9
valid_sources[0x41]	30202	1			T3	1		T9	2		T12	12
valid_sources[0x42]	28764	1			T2	1		T3	2		T4	1
valid_sources[0x43]	29910	1			T3	3		T4	1		T9	8
valid_sources[0x44]	29545	1			T4	2		T9	4		T10	1
valid_sources[0x45]	35859	1			T3	1		T4	4		T9	5
valid_sources[0x46]	30136	1			T3	5		T12	3		T13	14
valid_sources[0x47]	31942	1			T3	6		T4	1		T9	7
valid_sources[0x48]	29950	1			T3	5		T4	2		T9	4
valid_sources[0x49]	28990	1			T3	4		T9	6		T10	5
valid_sources[0x4a]	31397	1			T3	2		T4	1		T9	5
valid_sources[0x4b]	31855	1			T3	7		T4	2		T9	3
valid_sources[0x4c]	28342	1			T3	2		T4	5		T9	3
valid_sources[0x4d]	28399	1			T3	2		T4	2		T9	4
valid_sources[0x4e]	28321	1			T9	8		T10	3		T13	16
valid_sources[0x4f]	31566	1			T3	5		T4	3		T9	5
valid_sources[0x50]	31039	1			T3	1		T4	2		T9	7
valid_sources[0x51]	27559	1			T3	1		T6	5		T9	10
valid_sources[0x52]	32998	1			T3	1		T4	1		T9	9
valid_sources[0x53]	29416	1			T3	2		T9	3		T10	6
valid_sources[0x54]	30154	1			T3	2		T4	14		T9	7
valid_sources[0x55]	30982	1			T3	9		T4	5		T9	6
valid_sources[0x56]	27706	1			T2	1		T3	6		T4	8
valid_sources[0x57]	28529	1			T2	1		T3	7		T4	1
valid_sources[0x58]	67685	1			T3	1		T4	2		T9	5
valid_sources[0x59]	29580	1			T3	6		T4	3		T6	553
valid_sources[0x5a]	28464	1			T3	3		T4	5		T9	9
valid_sources[0x5b]	36373	1			T3	5		T4	3		T9	7
valid_sources[0x5c]	30928	1			T3	4		T4	1		T9	7
valid_sources[0x5d]	28978	1			T2	1		T3	5		T4	1
valid_sources[0x5e]	31532	1			T2	2		T3	4		T9	7
valid_sources[0x5f]	29744	1			T3	6		T4	1		T9	8
valid_sources[0x60]	29181	1			T3	5		T9	3		T10	4
valid_sources[0x61]	28851	1			T2	1		T9	9		T10	6
valid_sources[0x62]	31374	1			T3	3		T4	6		T9	3
valid_sources[0x63]	30788	1			T3	2		T4	3		T9	12
valid_sources[0x64]	32484	1			T3	2		T6	1		T9	8
valid_sources[0x65]	29362	1			T3	4		T9	4		T10	1
valid_sources[0x66]	28525	1			T3	5		T9	8		T10	4
valid_sources[0x67]	35067	1			T3	3		T4	1		T9	10
valid_sources[0x68]	30455	1			T3	3		T9	8		T10	2
valid_sources[0x69]	38391	1			T4	2		T9	2		T10	4
valid_sources[0x6a]	29145	1			T3	1		T4	5		T9	6
valid_sources[0x6b]	30375	1			T3	2		T7	473		T8	1326
valid_sources[0x6c]	34620	1			T3	3		T4	3		T9	5
valid_sources[0x6d]	33454	1			T3	5		T4	5		T9	2
valid_sources[0x6e]	31906	1			T3	3		T4	1		T9	4
valid_sources[0x6f]	32765	1			T2	1		T3	5		T4	1
valid_sources[0x70]	30190	1			T3	4		T4	8		T9	6
valid_sources[0x71]	28975	1			T3	5		T4	1		T5	1262
valid_sources[0x72]	34381	1			T2	1		T3	3		T6	1
valid_sources[0x73]	27442	1			T3	2		T4	2		T9	3
valid_sources[0x74]	29867	1			T3	2		T4	7		T9	6
valid_sources[0x75]	30215	1			T3	2		T9	7		T10	1
valid_sources[0x76]	28722	1			T3	3		T4	1		T9	8
valid_sources[0x77]	42498	1			T2	1		T4	1		T9	4
valid_sources[0x78]	30327	1			T3	6		T4	6		T9	7
valid_sources[0x79]	33392	1			T4	2		T9	8		T10	3
valid_sources[0x7a]	32440	1			T4	2		T6	144		T9	2
valid_sources[0x7b]	31843	1			T2	1		T3	4		T4	1
valid_sources[0x7c]	29479	1			T3	3		T9	10		T10	3
valid_sources[0x7d]	30306	1			T3	7		T4	1		T9	7
valid_sources[0x7e]	27079	1			T3	5		T4	1		T9	7
valid_sources[0x7f]	31575	1			T3	5		T4	1		T6	373
valid_sources[0x80]	29094	1			T2	1		T3	5		T4	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1073733

1

T1

117

T2

1

T3

9

values[0x0]

all_enables

biggest_size

1619716

1

T1

455

T3

434

T4

86

values[0x1]

all_enables

biggest_size

1599806

1

T1

438

T3

446

T4

91