Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3710492

1

T1

99

T2

42

T3

12

full_word

4294535

1

T1

1010

T2

1

T3

889

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8004667	1			T1	1109		T2	43		T3	901
auto[TlIntgErrCmd]	113	1			T83	3		T130	7		T131	5
auto[TlIntgErrData]	117	1			T83	2		T130	11		T131	2
auto[TlIntgErrBoth]	130	1			T83	5		T130	12		T131	13

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4434445

1

T1

209

T2

43

T3

18

auto[1]

3570582

1

T1

900

T3

883

T4

279

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3360182	1			T1	92		T2	42		T3	9
auto[TlIntgErrNone]	partial	auto[1]	349981	1			T1	7		T3	3		T4	102
auto[TlIntgErrNone]	full_word	auto[0]	1074097	1			T1	117		T2	1		T3	9
auto[TlIntgErrNone]	full_word	auto[1]	3220407	1			T1	893		T3	880		T4	177
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T83	2		T130	1		T131	2
auto[TlIntgErrCmd]	partial	auto[1]	67	1			T83	1		T130	6		T131	3
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T227	1		T228	1		T229	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T230	1		T231	1		T232	2
auto[TlIntgErrData]	partial	auto[0]	56	1			T83	1		T130	5		T131	2
auto[TlIntgErrData]	partial	auto[1]	51	1			T83	1		T130	4		T233	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T130	2		T224	1		T229	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T224	1		T234	1		T230	2
auto[TlIntgErrBoth]	partial	auto[0]	55	1			T83	2		T130	7		T131	4
auto[TlIntgErrBoth]	partial	auto[1]	63	1			T83	3		T130	5		T131	7
auto[TlIntgErrBoth]	full_word	auto[0]	8	1			T131	1		T230	1		T229	2
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T131	1		T228	1		T235	1