Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	482904819	2870152	0	0
DepthKnown_A	482904819	482776056	0	0
RvalidKnown_A	482904819	482776056	0	0
WreadyKnown_A	482904819	482776056	0	0
gen_passthru_fifo.paramCheckPass	1122	1122	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482904819	2870152	0	0
T1	18125	1663	0	0
T2	1597	0	0	0
T3	11309	832	0	0
T4	24683	0	0	0
T5	9341	832	0	0
T6	88558	0	0	0
T7	14577	1663	0	0
T8	21533	832	0	0
T9	27558	832	0	0
T10	67823	832	0	0
T11	0	1663	0	0
T12	0	832	0	0
T13	0	1663	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482904819	482776056	0	0
T1	18125	18047	0	0
T2	1597	1499	0	0
T3	11309	11246	0	0
T4	24683	24595	0	0
T5	9341	9244	0	0
T6	88558	88490	0	0
T7	14577	14520	0	0
T8	21533	21466	0	0
T9	27558	27508	0	0
T10	67823	67764	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482904819	482776056	0	0
T1	18125	18047	0	0
T2	1597	1499	0	0
T3	11309	11246	0	0
T4	24683	24595	0	0
T5	9341	9244	0	0
T6	88558	88490	0	0
T7	14577	14520	0	0
T8	21533	21466	0	0
T9	27558	27508	0	0
T10	67823	67764	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482904819	482776056	0	0
T1	18125	18047	0	0
T2	1597	1499	0	0
T3	11309	11246	0	0
T4	24683	24595	0	0
T5	9341	9244	0	0
T6	88558	88490	0	0
T7	14577	14520	0	0
T8	21533	21466	0	0
T9	27558	27508	0	0
T10	67823	67764	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1122	1122	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	482904819	3139553	0	0
DepthKnown_A	482904819	482776056	0	0
RvalidKnown_A	482904819	482776056	0	0
WreadyKnown_A	482904819	482776056	0	0
gen_passthru_fifo.paramCheckPass	1122	1122	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482904819	3139553	0	0
T1	18125	832	0	0
T2	1597	0	0	0
T3	11309	832	0	0
T4	24683	0	0	0
T5	9341	832	0	0
T6	88558	0	0	0
T7	14577	832	0	0
T8	21533	3759	0	0
T9	27558	3876	0	0
T10	67823	832	0	0
T11	0	832	0	0
T12	0	832	0	0
T13	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482904819	482776056	0	0
T1	18125	18047	0	0
T2	1597	1499	0	0
T3	11309	11246	0	0
T4	24683	24595	0	0
T5	9341	9244	0	0
T6	88558	88490	0	0
T7	14577	14520	0	0
T8	21533	21466	0	0
T9	27558	27508	0	0
T10	67823	67764	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482904819	482776056	0	0
T1	18125	18047	0	0
T2	1597	1499	0	0
T3	11309	11246	0	0
T4	24683	24595	0	0
T5	9341	9244	0	0
T6	88558	88490	0	0
T7	14577	14520	0	0
T8	21533	21466	0	0
T9	27558	27508	0	0
T10	67823	67764	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482904819	482776056	0	0
T1	18125	18047	0	0
T2	1597	1499	0	0
T3	11309	11246	0	0
T4	24683	24595	0	0
T5	9341	9244	0	0
T6	88558	88490	0	0
T7	14577	14520	0	0
T8	21533	21466	0	0
T9	27558	27508	0	0
T10	67823	67764	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1122	1122	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	482904819	188940	0	0
DepthKnown_A	482904819	482776056	0	0
RvalidKnown_A	482904819	482776056	0	0
WreadyKnown_A	482904819	482776056	0	0
gen_passthru_fifo.paramCheckPass	1122	1122	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482904819	188940	0	0
T4	24683	107	0	0
T5	9341	0	0	0
T6	88558	331	0	0
T7	14577	0	0	0
T8	21533	0	0	0
T9	27558	0	0	0
T10	67823	0	0	0
T11	38848	0	0	0
T12	263792	0	0	0
T23	0	28	0	0
T26	3646	0	0	0
T27	0	1	0	0
T28	0	146	0	0
T31	0	55	0	0
T37	0	6	0	0
T41	0	116	0	0
T44	0	50	0	0
T45	0	128	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482904819	482776056	0	0
T1	18125	18047	0	0
T2	1597	1499	0	0
T3	11309	11246	0	0
T4	24683	24595	0	0
T5	9341	9244	0	0
T6	88558	88490	0	0
T7	14577	14520	0	0
T8	21533	21466	0	0
T9	27558	27508	0	0
T10	67823	67764	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482904819	482776056	0	0
T1	18125	18047	0	0
T2	1597	1499	0	0
T3	11309	11246	0	0
T4	24683	24595	0	0
T5	9341	9244	0	0
T6	88558	88490	0	0
T7	14577	14520	0	0
T8	21533	21466	0	0
T9	27558	27508	0	0
T10	67823	67764	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482904819	482776056	0	0
T1	18125	18047	0	0
T2	1597	1499	0	0
T3	11309	11246	0	0
T4	24683	24595	0	0
T5	9341	9244	0	0
T6	88558	88490	0	0
T7	14577	14520	0	0
T8	21533	21466	0	0
T9	27558	27508	0	0
T10	67823	67764	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1122	1122	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	482904819	410088	0	0
DepthKnown_A	482904819	482776056	0	0
RvalidKnown_A	482904819	482776056	0	0
WreadyKnown_A	482904819	482776056	0	0
gen_passthru_fifo.paramCheckPass	1122	1122	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482904819	410088	0	0
T4	24683	107	0	0
T5	9341	0	0	0
T6	88558	331	0	0
T7	14577	0	0	0
T8	21533	0	0	0
T9	27558	0	0	0
T10	67823	0	0	0
T11	38848	0	0	0
T12	263792	0	0	0
T23	0	28	0	0
T26	3646	0	0	0
T27	0	1	0	0
T28	0	146	0	0
T31	0	55	0	0
T37	0	6	0	0
T41	0	344	0	0
T44	0	50	0	0
T45	0	128	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482904819	482776056	0	0
T1	18125	18047	0	0
T2	1597	1499	0	0
T3	11309	11246	0	0
T4	24683	24595	0	0
T5	9341	9244	0	0
T6	88558	88490	0	0
T7	14577	14520	0	0
T8	21533	21466	0	0
T9	27558	27508	0	0
T10	67823	67764	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482904819	482776056	0	0
T1	18125	18047	0	0
T2	1597	1499	0	0
T3	11309	11246	0	0
T4	24683	24595	0	0
T5	9341	9244	0	0
T6	88558	88490	0	0
T7	14577	14520	0	0
T8	21533	21466	0	0
T9	27558	27508	0	0
T10	67823	67764	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482904819	482776056	0	0
T1	18125	18047	0	0
T2	1597	1499	0	0
T3	11309	11246	0	0
T4	24683	24595	0	0
T5	9341	9244	0	0
T6	88558	88490	0	0
T7	14577	14520	0	0
T8	21533	21466	0	0
T9	27558	27508	0	0
T10	67823	67764	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1122	1122	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	482904819	6278645	0	0
DepthKnown_A	482904819	482776056	0	0
RvalidKnown_A	482904819	482776056	0	0
WreadyKnown_A	482904819	482776056	0	0
gen_passthru_fifo.paramCheckPass	1122	1122	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482904819	6278645	0	0
T1	18125	278	0	0
T2	1597	43	0	0
T3	11309	71	0	0
T4	24683	609	0	0
T5	9341	430	0	0
T6	88558	3351	0	0
T7	14577	77	0	0
T8	21533	557	0	0
T9	27558	654	0	0
T10	67823	56	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482904819	482776056	0	0
T1	18125	18047	0	0
T2	1597	1499	0	0
T3	11309	11246	0	0
T4	24683	24595	0	0
T5	9341	9244	0	0
T6	88558	88490	0	0
T7	14577	14520	0	0
T8	21533	21466	0	0
T9	27558	27508	0	0
T10	67823	67764	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482904819	482776056	0	0
T1	18125	18047	0	0
T2	1597	1499	0	0
T3	11309	11246	0	0
T4	24683	24595	0	0
T5	9341	9244	0	0
T6	88558	88490	0	0
T7	14577	14520	0	0
T8	21533	21466	0	0
T9	27558	27508	0	0
T10	67823	67764	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482904819	482776056	0	0
T1	18125	18047	0	0
T2	1597	1499	0	0
T3	11309	11246	0	0
T4	24683	24595	0	0
T5	9341	9244	0	0
T6	88558	88490	0	0
T7	14577	14520	0	0
T8	21533	21466	0	0
T9	27558	27508	0	0
T10	67823	67764	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1122	1122	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	482904819	12681247	0	0
DepthKnown_A	482904819	482776056	0	0
RvalidKnown_A	482904819	482776056	0	0
WreadyKnown_A	482904819	482776056	0	0
gen_passthru_fifo.paramCheckPass	1122	1122	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482904819	12681247	0	0
T1	18125	1164	0	0
T2	1597	163	0	0
T3	11309	69	0	0
T4	24683	607	0	0
T5	9341	430	0	0
T6	88558	3301	0	0
T7	14577	198	0	0
T8	21533	2343	0	0
T9	27558	2933	0	0
T10	67823	56	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482904819	482776056	0	0
T1	18125	18047	0	0
T2	1597	1499	0	0
T3	11309	11246	0	0
T4	24683	24595	0	0
T5	9341	9244	0	0
T6	88558	88490	0	0
T7	14577	14520	0	0
T8	21533	21466	0	0
T9	27558	27508	0	0
T10	67823	67764	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482904819	482776056	0	0
T1	18125	18047	0	0
T2	1597	1499	0	0
T3	11309	11246	0	0
T4	24683	24595	0	0
T5	9341	9244	0	0
T6	88558	88490	0	0
T7	14577	14520	0	0
T8	21533	21466	0	0
T9	27558	27508	0	0
T10	67823	67764	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482904819	482776056	0	0
T1	18125	18047	0	0
T2	1597	1499	0	0
T3	11309	11246	0	0
T4	24683	24595	0	0
T5	9341	9244	0	0
T6	88558	88490	0	0
T7	14577	14520	0	0
T8	21533	21466	0	0
T9	27558	27508	0	0
T10	67823	67764	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1122	1122	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0