Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3559793	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4303745

1

T3

290

T4

12

T5

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4241969	1			T1	63		T2	1		T3	1
values[0x0]	1811112	1			T3	187		T4	6		T5	3
values[0x1]	1810457	1			T3	164		T4	10		T5	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2524963	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5338575

1

T1

22

T3

309

T4

12

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	34801	1			T5	1		T11	3		T12	1
valid_sources[0x01]	29249	1			T5	1		T7	2		T8	7
valid_sources[0x02]	29754	1			T5	2		T7	1		T8	6
valid_sources[0x03]	29838	1			T4	1		T5	3		T6	2
valid_sources[0x04]	31705	1			T4	4		T5	1		T6	14
valid_sources[0x05]	32656	1			T5	1		T6	17		T7	3
valid_sources[0x06]	34497	1			T5	1		T6	17		T7	4
valid_sources[0x07]	28314	1			T5	3		T6	16		T7	7
valid_sources[0x08]	29774	1			T5	2		T6	15		T7	5
valid_sources[0x09]	34369	1			T5	5		T7	4		T8	2
valid_sources[0x0a]	30096	1			T7	9		T8	4		T11	3
valid_sources[0x0b]	41604	1			T5	5		T7	1		T8	3
valid_sources[0x0c]	30609	1			T5	3		T8	6		T10	3
valid_sources[0x0d]	29115	1			T7	1		T8	9		T12	8
valid_sources[0x0e]	30810	1			T8	8		T10	6		T11	6
valid_sources[0x0f]	31509	1			T5	4		T7	6		T8	3
valid_sources[0x10]	29190	1			T5	3		T7	8		T8	7
valid_sources[0x11]	30014	1			T8	4		T24	2		T16	61
valid_sources[0x12]	40457	1			T5	1		T8	3		T10	3
valid_sources[0x13]	29711	1			T5	2		T7	3		T8	2
valid_sources[0x14]	30580	1			T7	7		T8	3		T11	1
valid_sources[0x15]	28964	1			T5	1		T7	1		T8	9
valid_sources[0x16]	31588	1			T5	3		T7	1		T8	1
valid_sources[0x17]	34829	1			T5	1		T7	2		T8	13
valid_sources[0x18]	33239	1			T5	1		T7	5		T8	5
valid_sources[0x19]	29744	1			T5	1		T6	33		T7	5
valid_sources[0x1a]	28233	1			T6	30		T7	2		T8	7
valid_sources[0x1b]	30311	1			T5	1		T7	5		T8	5
valid_sources[0x1c]	29109	1			T5	3		T7	3		T10	9
valid_sources[0x1d]	29515	1			T5	2		T7	3		T8	6
valid_sources[0x1e]	29863	1			T5	3		T7	8		T8	15
valid_sources[0x1f]	27702	1			T5	2		T7	1		T9	879
valid_sources[0x20]	30410	1			T5	1		T7	4		T8	7
valid_sources[0x21]	30950	1			T5	3		T6	1		T7	1
valid_sources[0x22]	38843	1			T5	1		T7	6		T8	7
valid_sources[0x23]	31872	1			T6	13		T7	6		T10	5
valid_sources[0x24]	30107	1			T5	2		T7	5		T8	5
valid_sources[0x25]	27997	1			T8	2		T11	1		T16	113
valid_sources[0x26]	30295	1			T5	3		T6	26		T7	11
valid_sources[0x27]	29153	1			T5	2		T6	5		T8	8
valid_sources[0x28]	29726	1			T5	1		T6	2		T7	1
valid_sources[0x29]	29242	1			T5	2		T6	3		T7	4
valid_sources[0x2a]	30857	1			T7	4		T8	5		T9	4
valid_sources[0x2b]	27542	1			T5	4		T6	1		T8	3
valid_sources[0x2c]	29902	1			T5	2		T7	3		T10	1
valid_sources[0x2d]	29926	1			T5	1		T7	3		T8	5
valid_sources[0x2e]	45883	1			T5	2		T7	5		T8	1
valid_sources[0x2f]	29758	1			T5	1		T7	1		T8	4
valid_sources[0x30]	30253	1			T5	3		T6	14		T7	4
valid_sources[0x31]	27420	1			T5	4		T7	3		T8	5
valid_sources[0x32]	28933	1			T8	2		T12	15		T16	61
valid_sources[0x33]	38970	1			T6	41		T7	12		T8	1
valid_sources[0x34]	31599	1			T5	2		T7	4		T8	2
valid_sources[0x35]	31921	1			T5	1		T7	6		T8	6
valid_sources[0x36]	31111	1			T7	3		T8	4		T9	530
valid_sources[0x37]	30608	1			T5	2		T7	4		T8	4
valid_sources[0x38]	31856	1			T5	4		T6	10		T7	1
valid_sources[0x39]	31541	1			T5	2		T7	6		T8	6
valid_sources[0x3a]	32630	1			T6	12		T7	3		T8	4
valid_sources[0x3b]	27356	1			T7	9		T8	11		T10	2
valid_sources[0x3c]	35098	1			T5	1		T7	12		T9	1
valid_sources[0x3d]	27639	1			T7	6		T8	6		T12	1
valid_sources[0x3e]	29020	1			T5	2		T6	40		T7	2
valid_sources[0x3f]	28804	1			T5	1		T6	2		T7	2
valid_sources[0x40]	29261	1			T7	3		T8	3		T11	4
valid_sources[0x41]	30026	1			T5	3		T7	4		T8	1
valid_sources[0x42]	29941	1			T5	5		T7	8		T8	6
valid_sources[0x43]	28108	1			T5	5		T7	3		T8	4
valid_sources[0x44]	29127	1			T5	4		T7	4		T8	1
valid_sources[0x45]	33744	1			T5	2		T7	6		T8	2
valid_sources[0x46]	31803	1			T7	8		T8	3		T11	2
valid_sources[0x47]	29302	1			T5	3		T8	2		T10	6
valid_sources[0x48]	29159	1			T5	5		T7	2		T8	1
valid_sources[0x49]	30061	1			T7	6		T8	3		T10	7
valid_sources[0x4a]	29324	1			T5	3		T7	2		T8	1
valid_sources[0x4b]	31684	1			T5	2		T7	6		T8	6
valid_sources[0x4c]	26560	1			T5	1		T7	5		T8	5
valid_sources[0x4d]	33936	1			T5	1		T7	2		T8	4
valid_sources[0x4e]	29696	1			T5	2		T7	3		T8	4
valid_sources[0x4f]	29674	1			T5	4		T6	6		T8	10
valid_sources[0x50]	32869	1			T5	3		T7	2		T8	4
valid_sources[0x51]	29621	1			T5	2		T6	23		T7	3
valid_sources[0x52]	28033	1			T7	1		T8	1		T12	1
valid_sources[0x53]	28065	1			T5	4		T7	6		T8	3
valid_sources[0x54]	33328	1			T5	2		T6	27		T7	2
valid_sources[0x55]	28085	1			T7	1		T8	1		T11	13
valid_sources[0x56]	32931	1			T5	1		T7	5		T8	2
valid_sources[0x57]	28635	1			T5	1		T6	5		T7	5
valid_sources[0x58]	31988	1			T5	1		T6	20		T8	8
valid_sources[0x59]	31878	1			T5	2		T8	3		T10	5
valid_sources[0x5a]	30174	1			T5	2		T6	31		T7	3
valid_sources[0x5b]	29731	1			T5	2		T6	20		T7	11
valid_sources[0x5c]	30999	1			T3	352		T5	6		T7	5
valid_sources[0x5d]	28892	1			T7	4		T8	10		T10	1
valid_sources[0x5e]	29461	1			T5	2		T7	2		T8	2
valid_sources[0x5f]	29873	1			T5	1		T7	1		T8	3
valid_sources[0x60]	29508	1			T5	2		T7	4		T8	4
valid_sources[0x61]	29095	1			T5	1		T6	20		T7	2
valid_sources[0x62]	28638	1			T5	3		T7	3		T8	1
valid_sources[0x63]	30827	1			T5	2		T7	2		T8	8
valid_sources[0x64]	30707	1			T5	2		T6	7		T7	2
valid_sources[0x65]	29687	1			T7	3		T10	8		T11	7
valid_sources[0x66]	46307	1			T5	2		T6	16		T7	2
valid_sources[0x67]	27653	1			T5	1		T7	1		T10	12
valid_sources[0x68]	28593	1			T5	1		T6	3		T7	2
valid_sources[0x69]	28749	1			T4	2		T5	1		T7	3
valid_sources[0x6a]	31242	1			T5	4		T7	1		T8	6
valid_sources[0x6b]	29991	1			T6	6		T7	2		T12	4
valid_sources[0x6c]	27622	1			T4	1		T5	6		T7	6
valid_sources[0x6d]	32962	1			T5	1		T10	7		T11	7
valid_sources[0x6e]	32577	1			T5	1		T6	1		T7	1
valid_sources[0x6f]	31175	1			T5	2		T6	3		T7	2
valid_sources[0x70]	30355	1			T5	2		T6	4		T7	3
valid_sources[0x71]	34298	1			T5	5		T6	14		T7	2
valid_sources[0x72]	28855	1			T5	1		T7	6		T8	4
valid_sources[0x73]	30232	1			T5	2		T7	7		T8	3
valid_sources[0x74]	29927	1			T5	5		T6	1		T7	1
valid_sources[0x75]	28643	1			T6	2		T7	3		T8	1
valid_sources[0x76]	30599	1			T4	2		T5	2		T8	3
valid_sources[0x77]	28709	1			T5	1		T7	5		T10	26
valid_sources[0x78]	30261	1			T6	18		T7	1		T8	4
valid_sources[0x79]	27349	1			T6	11		T7	3		T8	2
valid_sources[0x7a]	28713	1			T5	2		T7	6		T11	1
valid_sources[0x7b]	31932	1			T5	1		T7	4		T8	3
valid_sources[0x7c]	29569	1			T5	4		T7	4		T8	1
valid_sources[0x7d]	32838	1			T5	2		T7	4		T8	5
valid_sources[0x7e]	30213	1			T5	1		T6	7		T7	7
valid_sources[0x7f]	30533	1			T5	1		T7	3		T8	3
valid_sources[0x80]	30929	1			T7	2		T8	8		T10	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1025119

1

T4

1

T5

2

T6

3

values[0x0]

all_enables

biggest_size

1652598

1

T3

152

T4

4

T5

1

values[0x1]

all_enables

biggest_size

1626028

1

T3

138

T4

7

T5

1