Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3582300

1

T1

63

T2

1

T3

62

full_word

4305111

1

T3

290

T4

12

T5

4

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7887091	1			T1	63		T2	1		T3	352
auto[TlIntgErrCmd]	98	1			T89	5		T105	1		T106	1
auto[TlIntgErrData]	117	1			T89	9		T105	4		T106	5
auto[TlIntgErrBoth]	105	1			T89	6		T105	5		T106	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4246876

1

T1

63

T2

1

T3

1

auto[1]

3640535

1

T3

351

T4

16

T5

8

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3221249	1			T1	63		T2	1		T3	1
auto[TlIntgErrNone]	partial	auto[1]	360763	1			T3	61		T4	5		T5	6
auto[TlIntgErrNone]	full_word	auto[0]	1025478	1			T4	1		T5	2		T6	3
auto[TlIntgErrNone]	full_word	auto[1]	3279601	1			T3	290		T4	11		T5	2
auto[TlIntgErrCmd]	partial	auto[0]	35	1			T119	1		T181	3		T183	1
auto[TlIntgErrCmd]	partial	auto[1]	52	1			T89	4		T105	1		T106	1
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T89	1		T184	1		T185	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T181	1		T183	1		T186	1
auto[TlIntgErrData]	partial	auto[0]	55	1			T89	4		T105	3		T106	1
auto[TlIntgErrData]	partial	auto[1]	48	1			T89	5		T105	1		T106	4
auto[TlIntgErrData]	full_word	auto[0]	6	1			T186	1		T180	1		T187	2
auto[TlIntgErrData]	full_word	auto[1]	8	1			T119	1		T181	1		T188	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T89	1		T105	4		T106	2
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T89	4		T105	1		T106	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T89	1		T187	1		T189	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T106	1		T122	1		T190	1