Unified Coverage Report :: Module :: spid_fifo2sram_adapter

Module : spid_fifo2sram_adapter

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.87	100.00	79.49			100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_tpm_rd_buffer	89.74	100.00	69.23			100.00
tb.dut.u_upload.u_payload_buffer	96.15	100.00	84.62			100.00	100.00
tb.dut.u_spi_tpm.u_tpm_wr_buffer	96.15	100.00	84.62			100.00	100.00

---

Module Instance : tb.dut.u_spi_tpm.u_tpm_rd_buffer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.74	100.00	69.23			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.74	100.00	69.23			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.79	99.29	91.20		91.67	96.77	100.00	u_spi_tpm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_payload_buffer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.15	100.00	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.15	100.00	84.62			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.37	100.00	86.11		100.00	95.74	100.00	u_upload

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spi_tpm.u_tpm_wr_buffer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.15	100.00	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.15	100.00	84.62			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.79	99.29	91.20		91.67	96.77	100.00	u_spi_tpm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : spid_fifo2sram_adapter ( parameter FifoWidth=8,FifoDepth=256,SramAw=10,SramDw=32,SramBaseAddr=896,EnPack=1,FifoPtrW=8,NumEntryPerWord=4,g_multiple_entry_per_word.SubWordW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
96.15	100.00

tb.dut.u_upload.u_payload_buffer

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	57	1	1	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	73	1	1	100.00
ALWAYS	76	6	6	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	97	5	5	100.00

51                        logic [FifoPtrW-1:0] fifoptr;
52         1/1            assign wdepth_o = fifoptr;
           Tests:       T1 T2 T3 
53                      
54                        logic sram_ack, fifoptr_inc;
55                      
56         1/1            assign sram_req_o = wvalid_i & !clr_i;
           Tests:       T1 T2 T3 
57         1/1            assign wready_o   = sram_gnt_i & !clr_i;
           Tests:       T1 T2 T3 
58                      
59                        assign sram_write_o = 1'b 1;
60                      
61                        logic unused_sram_read;
62         1/1            assign unused_sram_read = ^{sram_rvalid_i, sram_rdata_i, sram_rerror_i};
           Tests:       T1 T2 T3 
63                      
64                        if (EnPack == 1 && NumEntryPerWord != 1) begin : g_multiple_entry_per_word
65                          // If pack, the FifoWidth shall divide SramDw
66                          `ASSERT_INIT(WidthDivideSramDw_A, SramDw == (SramDw/FifoWidth)*FifoWidth)
67                      
68                          localparam int unsigned SubWordW = $clog2(NumEntryPerWord);
69                      
70                          // Should be multiple of 2
71                          `ASSERT_INIT(NumEntryPerWordPowerOf2_A, NumEntryPerWord == 2**SubWordW)
72                      
73         1/1              assign sram_addr_o = SramBaseAddr + SramAw'(fifoptr[FifoPtrW-1:SubWordW]);
           Tests:       T1 T2 T3 
74                      
75                          always_comb begin
76         1/1                sram_wdata_o = '0;
           Tests:       T1 T2 T3 
77         1/1                sram_wmask_o = '0;
           Tests:       T1 T2 T3 
78         1/1                for(int unsigned i = 0; i < NumEntryPerWord ; i++) begin
           Tests:       T1 T2 T3 
79         1/1                  if (fifoptr[0+:SubWordW] == i) begin
           Tests:       T1 T2 T3 
80         1/1                    sram_wdata_o[i*FifoWidth+:FifoWidth] = wdata_i;
           Tests:       T1 T2 T3 
81         1/1                    sram_wmask_o[i*FifoWidth+:FifoWidth] = {FifoWidth{1'b1}};
           Tests:       T1 T2 T3 
82                              end
                        MISSING_ELSE
83                            end
84                          end
85                      
86                        end else begin : g_one_entry_per_word
87                          assign sram_addr_o = SramBaseAddr + SramAw'(fifoptr);
88                          assign sram_wdata_o = SramDw'(wdata_i);
89                          assign sram_wmask_o = SramDw'({1'b0, {FifoWidth{1'b1}}});
90                        end
91                      
92         1/1            assign sram_ack = sram_req_o && sram_gnt_i;
           Tests:       T1 T2 T3 
93                      
94         1/1            assign fifoptr_inc = sram_ack;
           Tests:       T1 T2 T3 
95                      
96                        always_ff @(posedge clk_i or negedge rst_ni) begin
97         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
98         1/1                fifoptr <= '0;
           Tests:       T1 T2 T3 
99         1/1              end else if (clr_i) begin
           Tests:       T6 T7 T8 
100        unreachable        fifoptr <= '0;
101        1/1              end else if (fifoptr_inc) begin
           Tests:       T6 T7 T8 
102        1/1                fifoptr <= (fifoptr == FifoPtrW'(FifoDepth-1))
           Tests:       T40 T47 T48 
103                                    ? '0 : fifoptr + 1'b1;
104                         end
                        MISSING_ELSE

---

Line Coverage for Module : spid_fifo2sram_adapter ( parameter FifoWidth=8,FifoDepth=64,SramAw=10,SramDw=32,SramBaseAddr=992,EnPack=1,FifoPtrW=6,NumEntryPerWord=4,g_multiple_entry_per_word.SubWordW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
96.15	100.00

tb.dut.u_spi_tpm.u_tpm_wr_buffer

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	57	1	1	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	73	1	1	100.00
ALWAYS	76	6	6	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	97	5	5	100.00

51                        logic [FifoPtrW-1:0] fifoptr;
52         1/1            assign wdepth_o = fifoptr;
           Tests:       T1 T2 T3 
53                      
54                        logic sram_ack, fifoptr_inc;
55                      
56         1/1            assign sram_req_o = wvalid_i & !clr_i;
           Tests:       T1 T2 T3 
57         1/1            assign wready_o   = sram_gnt_i & !clr_i;
           Tests:       T1 T2 T3 
58                      
59                        assign sram_write_o = 1'b 1;
60                      
61                        logic unused_sram_read;
62         1/1            assign unused_sram_read = ^{sram_rvalid_i, sram_rdata_i, sram_rerror_i};
           Tests:       T1 T2 T3 
63                      
64                        if (EnPack == 1 && NumEntryPerWord != 1) begin : g_multiple_entry_per_word
65                          // If pack, the FifoWidth shall divide SramDw
66                          `ASSERT_INIT(WidthDivideSramDw_A, SramDw == (SramDw/FifoWidth)*FifoWidth)
67                      
68                          localparam int unsigned SubWordW = $clog2(NumEntryPerWord);
69                      
70                          // Should be multiple of 2
71                          `ASSERT_INIT(NumEntryPerWordPowerOf2_A, NumEntryPerWord == 2**SubWordW)
72                      
73         1/1              assign sram_addr_o = SramBaseAddr + SramAw'(fifoptr[FifoPtrW-1:SubWordW]);
           Tests:       T1 T2 T3 
74                      
75                          always_comb begin
76         1/1                sram_wdata_o = '0;
           Tests:       T1 T2 T3 
77         1/1                sram_wmask_o = '0;
           Tests:       T1 T2 T3 
78         1/1                for(int unsigned i = 0; i < NumEntryPerWord ; i++) begin
           Tests:       T1 T2 T3 
79         1/1                  if (fifoptr[0+:SubWordW] == i) begin
           Tests:       T1 T2 T3 
80         1/1                    sram_wdata_o[i*FifoWidth+:FifoWidth] = wdata_i;
           Tests:       T1 T2 T3 
81         1/1                    sram_wmask_o[i*FifoWidth+:FifoWidth] = {FifoWidth{1'b1}};
           Tests:       T1 T2 T3 
82                              end
                        MISSING_ELSE
83                            end
84                          end
85                      
86                        end else begin : g_one_entry_per_word
87                          assign sram_addr_o = SramBaseAddr + SramAw'(fifoptr);
88                          assign sram_wdata_o = SramDw'(wdata_i);
89                          assign sram_wmask_o = SramDw'({1'b0, {FifoWidth{1'b1}}});
90                        end
91                      
92         1/1            assign sram_ack = sram_req_o && sram_gnt_i;
           Tests:       T1 T2 T3 
93                      
94         1/1            assign fifoptr_inc = sram_ack;
           Tests:       T1 T2 T3 
95                      
96                        always_ff @(posedge clk_i or negedge rst_ni) begin
97         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
98         1/1                fifoptr <= '0;
           Tests:       T1 T2 T3 
99         1/1              end else if (clr_i) begin
           Tests:       T3 T4 T5 
100        unreachable        fifoptr <= '0;
101        1/1              end else if (fifoptr_inc) begin
           Tests:       T3 T4 T5 
102        1/1                fifoptr <= (fifoptr == FifoPtrW'(FifoDepth-1))
           Tests:       T5 T9 T26 
103                                    ? '0 : fifoptr + 1'b1;
104                         end
                        MISSING_ELSE

---

Line Coverage for Module : spid_fifo2sram_adapter ( parameter FifoWidth=32,FifoDepth=16,SramAw=10,SramDw=32,SramBaseAddr=832,EnPack=1,FifoPtrW=4,NumEntryPerWord=1 )
Line Coverage for Module self-instances :

SCORE	LINE
89.74	100.00

tb.dut.u_spi_tpm.u_tpm_rd_buffer

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	57	1	1	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	97	6	6	100.00

51                        logic [FifoPtrW-1:0] fifoptr;
52         1/1            assign wdepth_o = fifoptr;
           Tests:       T1 T2 T3 
53                      
54                        logic sram_ack, fifoptr_inc;
55                      
56         1/1            assign sram_req_o = wvalid_i & !clr_i;
           Tests:       T1 T2 T3 
57         1/1            assign wready_o   = sram_gnt_i & !clr_i;
           Tests:       T1 T2 T3 
58                      
59                        assign sram_write_o = 1'b 1;
60                      
61                        logic unused_sram_read;
62         1/1            assign unused_sram_read = ^{sram_rvalid_i, sram_rdata_i, sram_rerror_i};
           Tests:       T1 T2 T3 
63                      
64                        if (EnPack == 1 && NumEntryPerWord != 1) begin : g_multiple_entry_per_word
65                          // If pack, the FifoWidth shall divide SramDw
66                          `ASSERT_INIT(WidthDivideSramDw_A, SramDw == (SramDw/FifoWidth)*FifoWidth)
67                      
68                          localparam int unsigned SubWordW = $clog2(NumEntryPerWord);
69                      
70                          // Should be multiple of 2
71                          `ASSERT_INIT(NumEntryPerWordPowerOf2_A, NumEntryPerWord == 2**SubWordW)
72                      
73                          assign sram_addr_o = SramBaseAddr + SramAw'(fifoptr[FifoPtrW-1:SubWordW]);
74                      
75                          always_comb begin
76                            sram_wdata_o = '0;
77                            sram_wmask_o = '0;
78                            for(int unsigned i = 0; i < NumEntryPerWord ; i++) begin
79                              if (fifoptr[0+:SubWordW] == i) begin
80                                sram_wdata_o[i*FifoWidth+:FifoWidth] = wdata_i;
81                                sram_wmask_o[i*FifoWidth+:FifoWidth] = {FifoWidth{1'b1}};
82                              end
83                            end
84                          end
85                      
86                        end else begin : g_one_entry_per_word
87         1/1              assign sram_addr_o = SramBaseAddr + SramAw'(fifoptr);
           Tests:       T1 T2 T3 
88         1/1              assign sram_wdata_o = SramDw'(wdata_i);
           Tests:       T1 T2 T3 
89                          assign sram_wmask_o = SramDw'({1'b0, {FifoWidth{1'b1}}});
90                        end
91                      
92         1/1            assign sram_ack = sram_req_o && sram_gnt_i;
           Tests:       T1 T2 T3 
93                      
94         1/1            assign fifoptr_inc = sram_ack;
           Tests:       T5 T9 T26 
95                      
96                        always_ff @(posedge clk_i or negedge rst_ni) begin
97         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
98         1/1                fifoptr <= '0;
           Tests:       T1 T2 T3 
99         1/1              end else if (clr_i) begin
           Tests:       T1 T2 T3 
100        1/1                fifoptr <= '0;
           Tests:       T1 T2 T3 
101        1/1              end else if (fifoptr_inc) begin
           Tests:       T5 T9 T26 
102        1/1                fifoptr <= (fifoptr == FifoPtrW'(FifoDepth-1))
           Tests:       T5 T9 T26 
103                                    ? '0 : fifoptr + 1'b1;
104                         end
                        MISSING_ELSE

---

Cond Coverage for Module : spid_fifo2sram_adapter ( parameter FifoWidth=8,FifoDepth=256,SramAw=10,SramDw=32,SramBaseAddr=896,EnPack=1,FifoPtrW=8,NumEntryPerWord=4,g_multiple_entry_per_word.SubWordW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
96.15	84.62

tb.dut.u_upload.u_payload_buffer

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       56
 EXPRESSION (wvalid_i & ((!clr_i)))
             ----1---   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T40,T47,T48

 LINE       57
 EXPRESSION (sram_gnt_i & ((!clr_i)))
             -----1----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T40,T47,T48

 LINE       79
 EXPRESSION (fifoptr[0+:g_multiple_entry_per_word.SubWordW] == i)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T40,T47,T48

 LINE       102
 EXPRESSION ((fifoptr == 8'((FifoDepth - 1))) ? '0 : ((fifoptr + 1'b1)))
             ----------------1---------------

-1-	Status	Tests
0	Covered	T40,T47,T48
1	Covered	T40,T47,T48

 LINE       102
 SUB-EXPRESSION (fifoptr == 8'((FifoDepth - 1)))
                ----------------1---------------

-1-	Status	Tests
0	Covered	T40,T47,T48
1	Covered	T40,T47,T48

---

Cond Coverage for Module : spid_fifo2sram_adapter ( parameter FifoWidth=8,FifoDepth=64,SramAw=10,SramDw=32,SramBaseAddr=992,EnPack=1,FifoPtrW=6,NumEntryPerWord=4,g_multiple_entry_per_word.SubWordW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
96.15	84.62

tb.dut.u_spi_tpm.u_tpm_wr_buffer

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       56
 EXPRESSION (wvalid_i & ((!clr_i)))
             ----1---   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T5,T9,T26

 LINE       57
 EXPRESSION (sram_gnt_i & ((!clr_i)))
             -----1----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T5,T9,T26

 LINE       79
 EXPRESSION (fifoptr[0+:g_multiple_entry_per_word.SubWordW] == i)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T5,T9,T26

 LINE       102
 EXPRESSION ((fifoptr == 6'((FifoDepth - 1))) ? '0 : ((fifoptr + 1'b1)))
             ----------------1---------------

-1-	Status	Tests
0	Covered	T5,T9,T26
1	Covered	T9,T44,T47

 LINE       102
 SUB-EXPRESSION (fifoptr == 6'((FifoDepth - 1)))
                ----------------1---------------

-1-	Status	Tests
0	Covered	T5,T9,T26
1	Covered	T9,T44,T47

---

Cond Coverage for Module : spid_fifo2sram_adapter ( parameter FifoWidth=32,FifoDepth=16,SramAw=10,SramDw=32,SramBaseAddr=832,EnPack=1,FifoPtrW=4,NumEntryPerWord=1 )
Cond Coverage for Module self-instances :

SCORE	COND
89.74	69.23

tb.dut.u_spi_tpm.u_tpm_rd_buffer

	Total	Covered	Percent
Conditions	13	9	69.23
Logical	13	9	69.23
Non-Logical	0	0
Event	0	0

 LINE       56
 EXPRESSION (wvalid_i & ((!clr_i)))
             ----1---   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T9,T26
1	0	Not Covered
1	1	Covered	T5,T9,T26

 LINE       57
 EXPRESSION (sram_gnt_i & ((!clr_i)))
             -----1----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T9,T26
1	0	Not Covered
1	1	Covered	T5,T9,T26

 LINE       92
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T5,T9,T26

 LINE       102
 EXPRESSION ((fifoptr == 4'((FifoDepth - 1))) ? '0 : ((fifoptr + 1'b1)))
             ----------------1---------------

-1-	Status	Tests
0	Covered	T5,T9,T26
1	Covered	T9,T31,T44

 LINE       102
 SUB-EXPRESSION (fifoptr == 4'((FifoDepth - 1)))
                ----------------1---------------

-1-	Status	Tests
0	Covered	T5,T9,T26
1	Covered	T9,T31,T44

---

Branch Coverage for Module : spid_fifo2sram_adapter ( parameter FifoWidth=8,FifoDepth=256,SramAw=10,SramDw=32,SramBaseAddr=896,EnPack=1,FifoPtrW=8,NumEntryPerWord=4,g_multiple_entry_per_word.SubWordW=2 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
96.15	100.00

tb.dut.u_upload.u_payload_buffer

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	97	4	4	100.00
IF	79	2	2	100.00

97             if (!rst_ni) begin
               -1-  
98               fifoptr <= '0;
                 ==>
99             end else if (clr_i) begin
                        -2-  
100              fifoptr <= '0;
                 ==> (Unreachable)
101            end else if (fifoptr_inc) begin
                        -3-     
102              fifoptr <= (fifoptr == FifoPtrW'(FifoDepth-1))
                                                               
103                       ? '0 : fifoptr + 1'b1;
                          -4-  
                          ==>  
                          ==>  
104            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	1	Covered	T40,T47,T48
0	0	1	0	Covered	T40,T47,T48
0	0	0	-	Covered	T6,T7,T8

79                 if (fifoptr[0+:SubWordW] == i) begin
                   -1-     
80                   sram_wdata_o[i*FifoWidth+:FifoWidth] = wdata_i;
                     ==>
81                   sram_wmask_o[i*FifoWidth+:FifoWidth] = {FifoWidth{1'b1}};
82                 end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Branch Coverage for Module : spid_fifo2sram_adapter ( parameter FifoWidth=8,FifoDepth=64,SramAw=10,SramDw=32,SramBaseAddr=992,EnPack=1,FifoPtrW=6,NumEntryPerWord=4,g_multiple_entry_per_word.SubWordW=2 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
96.15	100.00

tb.dut.u_spi_tpm.u_tpm_wr_buffer

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	97	4	4	100.00
IF	79	2	2	100.00

97             if (!rst_ni) begin
               -1-  
98               fifoptr <= '0;
                 ==>
99             end else if (clr_i) begin
                        -2-  
100              fifoptr <= '0;
                 ==> (Unreachable)
101            end else if (fifoptr_inc) begin
                        -3-     
102              fifoptr <= (fifoptr == FifoPtrW'(FifoDepth-1))
                                                               
103                       ? '0 : fifoptr + 1'b1;
                          -4-  
                          ==>  
                          ==>  
104            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	1	Covered	T9,T44,T47
0	0	1	0	Covered	T5,T9,T26
0	0	0	-	Covered	T3,T4,T5

79                 if (fifoptr[0+:SubWordW] == i) begin
                   -1-     
80                   sram_wdata_o[i*FifoWidth+:FifoWidth] = wdata_i;
                     ==>
81                   sram_wmask_o[i*FifoWidth+:FifoWidth] = {FifoWidth{1'b1}};
82                 end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Branch Coverage for Module : spid_fifo2sram_adapter ( parameter FifoWidth=32,FifoDepth=16,SramAw=10,SramDw=32,SramBaseAddr=832,EnPack=1,FifoPtrW=4,NumEntryPerWord=1 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
89.74	100.00

tb.dut.u_spi_tpm.u_tpm_rd_buffer

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	97	5	5	100.00

97             if (!rst_ni) begin
               -1-  
98               fifoptr <= '0;
                 ==>
99             end else if (clr_i) begin
                        -2-  
100              fifoptr <= '0;
                 ==>
101            end else if (fifoptr_inc) begin
                        -3-     
102              fifoptr <= (fifoptr == FifoPtrW'(FifoDepth-1))
                                                               
103                       ? '0 : fifoptr + 1'b1;
                          -4-  
                          ==>  
                          ==>  
104            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T1,T2,T3
0	0	1	1	Covered	T9,T31,T44
0	0	1	0	Covered	T5,T9,T26
0	0	0	-	Covered	T5,T9,T26

---

Assert Coverage for Module : spid_fifo2sram_adapter

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_multiple_entry_per_word.NumEntryPerWordPowerOf2_A	1912	1912	0	0
g_multiple_entry_per_word.WidthDivideSramDw_A	1912	1912	0	0

g_multiple_entry_per_word.NumEntryPerWordPowerOf2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1912	1912	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T8	2	2	0	0
T9	2	2	0	0
T10	2	2	0	0

g_multiple_entry_per_word.WidthDivideSramDw_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1912	1912	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T8	2	2	0	0
T9	2	2	0	0
T10	2	2	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_tpm_rd_buffer

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	57	1	1	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	97	6	6	100.00

51                        logic [FifoPtrW-1:0] fifoptr;
52         1/1            assign wdepth_o = fifoptr;
           Tests:       T1 T2 T3 
53                      
54                        logic sram_ack, fifoptr_inc;
55                      
56         1/1            assign sram_req_o = wvalid_i & !clr_i;
           Tests:       T1 T2 T3 
57         1/1            assign wready_o   = sram_gnt_i & !clr_i;
           Tests:       T1 T2 T3 
58                      
59                        assign sram_write_o = 1'b 1;
60                      
61                        logic unused_sram_read;
62         1/1            assign unused_sram_read = ^{sram_rvalid_i, sram_rdata_i, sram_rerror_i};
           Tests:       T1 T2 T3 
63                      
64                        if (EnPack == 1 && NumEntryPerWord != 1) begin : g_multiple_entry_per_word
65                          // If pack, the FifoWidth shall divide SramDw
66                          `ASSERT_INIT(WidthDivideSramDw_A, SramDw == (SramDw/FifoWidth)*FifoWidth)
67                      
68                          localparam int unsigned SubWordW = $clog2(NumEntryPerWord);
69                      
70                          // Should be multiple of 2
71                          `ASSERT_INIT(NumEntryPerWordPowerOf2_A, NumEntryPerWord == 2**SubWordW)
72                      
73                          assign sram_addr_o = SramBaseAddr + SramAw'(fifoptr[FifoPtrW-1:SubWordW]);
74                      
75                          always_comb begin
76                            sram_wdata_o = '0;
77                            sram_wmask_o = '0;
78                            for(int unsigned i = 0; i < NumEntryPerWord ; i++) begin
79                              if (fifoptr[0+:SubWordW] == i) begin
80                                sram_wdata_o[i*FifoWidth+:FifoWidth] = wdata_i;
81                                sram_wmask_o[i*FifoWidth+:FifoWidth] = {FifoWidth{1'b1}};
82                              end
83                            end
84                          end
85                      
86                        end else begin : g_one_entry_per_word
87         1/1              assign sram_addr_o = SramBaseAddr + SramAw'(fifoptr);
           Tests:       T1 T2 T3 
88         1/1              assign sram_wdata_o = SramDw'(wdata_i);
           Tests:       T1 T2 T3 
89                          assign sram_wmask_o = SramDw'({1'b0, {FifoWidth{1'b1}}});
90                        end
91                      
92         1/1            assign sram_ack = sram_req_o && sram_gnt_i;
           Tests:       T1 T2 T3 
93                      
94         1/1            assign fifoptr_inc = sram_ack;
           Tests:       T5 T9 T26 
95                      
96                        always_ff @(posedge clk_i or negedge rst_ni) begin
97         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
98         1/1                fifoptr <= '0;
           Tests:       T1 T2 T3 
99         1/1              end else if (clr_i) begin
           Tests:       T1 T2 T3 
100        1/1                fifoptr <= '0;
           Tests:       T1 T2 T3 
101        1/1              end else if (fifoptr_inc) begin
           Tests:       T5 T9 T26 
102        1/1                fifoptr <= (fifoptr == FifoPtrW'(FifoDepth-1))
           Tests:       T5 T9 T26 
103                                    ? '0 : fifoptr + 1'b1;
104                         end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_tpm_rd_buffer

	Total	Covered	Percent
Conditions	13	9	69.23
Logical	13	9	69.23
Non-Logical	0	0
Event	0	0

 LINE       56
 EXPRESSION (wvalid_i & ((!clr_i)))
             ----1---   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T9,T26
1	0	Not Covered
1	1	Covered	T5,T9,T26

 LINE       57
 EXPRESSION (sram_gnt_i & ((!clr_i)))
             -----1----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T9,T26
1	0	Not Covered
1	1	Covered	T5,T9,T26

 LINE       92
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T5,T9,T26

 LINE       102
 EXPRESSION ((fifoptr == 4'((FifoDepth - 1))) ? '0 : ((fifoptr + 1'b1)))
             ----------------1---------------

-1-	Status	Tests
0	Covered	T5,T9,T26
1	Covered	T9,T31,T44

 LINE       102
 SUB-EXPRESSION (fifoptr == 4'((FifoDepth - 1)))
                ----------------1---------------

-1-	Status	Tests
0	Covered	T5,T9,T26
1	Covered	T9,T31,T44

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_tpm_rd_buffer

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	97	5	5	100.00

97             if (!rst_ni) begin
               -1-  
98               fifoptr <= '0;
                 ==>
99             end else if (clr_i) begin
                        -2-  
100              fifoptr <= '0;
                 ==>
101            end else if (fifoptr_inc) begin
                        -3-     
102              fifoptr <= (fifoptr == FifoPtrW'(FifoDepth-1))
                                                               
103                       ? '0 : fifoptr + 1'b1;
                          -4-  
                          ==>  
                          ==>  
104            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T1,T2,T3
0	0	1	1	Covered	T9,T31,T44
0	0	1	0	Covered	T5,T9,T26
0	0	0	-	Covered	T5,T9,T26

Line Coverage for Instance : tb.dut.u_upload.u_payload_buffer

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	57	1	1	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	73	1	1	100.00
ALWAYS	76	6	6	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	97	5	5	100.00

51                        logic [FifoPtrW-1:0] fifoptr;
52         1/1            assign wdepth_o = fifoptr;
           Tests:       T1 T2 T3 
53                      
54                        logic sram_ack, fifoptr_inc;
55                      
56         1/1            assign sram_req_o = wvalid_i & !clr_i;
           Tests:       T1 T2 T3 
57         1/1            assign wready_o   = sram_gnt_i & !clr_i;
           Tests:       T1 T2 T3 
58                      
59                        assign sram_write_o = 1'b 1;
60                      
61                        logic unused_sram_read;
62         1/1            assign unused_sram_read = ^{sram_rvalid_i, sram_rdata_i, sram_rerror_i};
           Tests:       T1 T2 T3 
63                      
64                        if (EnPack == 1 && NumEntryPerWord != 1) begin : g_multiple_entry_per_word
65                          // If pack, the FifoWidth shall divide SramDw
66                          `ASSERT_INIT(WidthDivideSramDw_A, SramDw == (SramDw/FifoWidth)*FifoWidth)
67                      
68                          localparam int unsigned SubWordW = $clog2(NumEntryPerWord);
69                      
70                          // Should be multiple of 2
71                          `ASSERT_INIT(NumEntryPerWordPowerOf2_A, NumEntryPerWord == 2**SubWordW)
72                      
73         1/1              assign sram_addr_o = SramBaseAddr + SramAw'(fifoptr[FifoPtrW-1:SubWordW]);
           Tests:       T1 T2 T3 
74                      
75                          always_comb begin
76         1/1                sram_wdata_o = '0;
           Tests:       T1 T2 T3 
77         1/1                sram_wmask_o = '0;
           Tests:       T1 T2 T3 
78         1/1                for(int unsigned i = 0; i < NumEntryPerWord ; i++) begin
           Tests:       T1 T2 T3 
79         1/1                  if (fifoptr[0+:SubWordW] == i) begin
           Tests:       T1 T2 T3 
80         1/1                    sram_wdata_o[i*FifoWidth+:FifoWidth] = wdata_i;
           Tests:       T1 T2 T3 
81         1/1                    sram_wmask_o[i*FifoWidth+:FifoWidth] = {FifoWidth{1'b1}};
           Tests:       T1 T2 T3 
82                              end
                        MISSING_ELSE
83                            end
84                          end
85                      
86                        end else begin : g_one_entry_per_word
87                          assign sram_addr_o = SramBaseAddr + SramAw'(fifoptr);
88                          assign sram_wdata_o = SramDw'(wdata_i);
89                          assign sram_wmask_o = SramDw'({1'b0, {FifoWidth{1'b1}}});
90                        end
91                      
92         1/1            assign sram_ack = sram_req_o && sram_gnt_i;
           Tests:       T1 T2 T3 
93                      
94         1/1            assign fifoptr_inc = sram_ack;
           Tests:       T1 T2 T3 
95                      
96                        always_ff @(posedge clk_i or negedge rst_ni) begin
97         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
98         1/1                fifoptr <= '0;
           Tests:       T1 T2 T3 
99         1/1              end else if (clr_i) begin
           Tests:       T6 T7 T8 
100        unreachable        fifoptr <= '0;
101        1/1              end else if (fifoptr_inc) begin
           Tests:       T6 T7 T8 
102        1/1                fifoptr <= (fifoptr == FifoPtrW'(FifoDepth-1))
           Tests:       T40 T47 T48 
103                                    ? '0 : fifoptr + 1'b1;
104                         end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_payload_buffer

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       56
 EXPRESSION (wvalid_i & ((!clr_i)))
             ----1---   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T40,T47,T48

 LINE       57
 EXPRESSION (sram_gnt_i & ((!clr_i)))
             -----1----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T40,T47,T48

 LINE       79
 EXPRESSION (fifoptr[0+:g_multiple_entry_per_word.SubWordW] == i)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T40,T47,T48

 LINE       102
 EXPRESSION ((fifoptr == 8'((FifoDepth - 1))) ? '0 : ((fifoptr + 1'b1)))
             ----------------1---------------

-1-	Status	Tests
0	Covered	T40,T47,T48
1	Covered	T40,T47,T48

 LINE       102
 SUB-EXPRESSION (fifoptr == 8'((FifoDepth - 1)))
                ----------------1---------------

-1-	Status	Tests
0	Covered	T40,T47,T48
1	Covered	T40,T47,T48

---

Branch Coverage for Instance : tb.dut.u_upload.u_payload_buffer

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	97	4	4	100.00
IF	79	2	2	100.00

97             if (!rst_ni) begin
               -1-  
98               fifoptr <= '0;
                 ==>
99             end else if (clr_i) begin
                        -2-  
100              fifoptr <= '0;
                 ==> (Unreachable)
101            end else if (fifoptr_inc) begin
                        -3-     
102              fifoptr <= (fifoptr == FifoPtrW'(FifoDepth-1))
                                                               
103                       ? '0 : fifoptr + 1'b1;
                          -4-  
                          ==>  
                          ==>  
104            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	1	Covered	T40,T47,T48
0	0	1	0	Covered	T40,T47,T48
0	0	0	-	Covered	T6,T7,T8

79                 if (fifoptr[0+:SubWordW] == i) begin
                   -1-     
80                   sram_wdata_o[i*FifoWidth+:FifoWidth] = wdata_i;
                     ==>
81                   sram_wmask_o[i*FifoWidth+:FifoWidth] = {FifoWidth{1'b1}};
82                 end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_payload_buffer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_multiple_entry_per_word.NumEntryPerWordPowerOf2_A	956	956	0	0
g_multiple_entry_per_word.WidthDivideSramDw_A	956	956	0	0

g_multiple_entry_per_word.NumEntryPerWordPowerOf2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

g_multiple_entry_per_word.WidthDivideSramDw_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_tpm_wr_buffer

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	57	1	1	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	73	1	1	100.00
ALWAYS	76	6	6	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	97	5	5	100.00

51                        logic [FifoPtrW-1:0] fifoptr;
52         1/1            assign wdepth_o = fifoptr;
           Tests:       T1 T2 T3 
53                      
54                        logic sram_ack, fifoptr_inc;
55                      
56         1/1            assign sram_req_o = wvalid_i & !clr_i;
           Tests:       T1 T2 T3 
57         1/1            assign wready_o   = sram_gnt_i & !clr_i;
           Tests:       T1 T2 T3 
58                      
59                        assign sram_write_o = 1'b 1;
60                      
61                        logic unused_sram_read;
62         1/1            assign unused_sram_read = ^{sram_rvalid_i, sram_rdata_i, sram_rerror_i};
           Tests:       T1 T2 T3 
63                      
64                        if (EnPack == 1 && NumEntryPerWord != 1) begin : g_multiple_entry_per_word
65                          // If pack, the FifoWidth shall divide SramDw
66                          `ASSERT_INIT(WidthDivideSramDw_A, SramDw == (SramDw/FifoWidth)*FifoWidth)
67                      
68                          localparam int unsigned SubWordW = $clog2(NumEntryPerWord);
69                      
70                          // Should be multiple of 2
71                          `ASSERT_INIT(NumEntryPerWordPowerOf2_A, NumEntryPerWord == 2**SubWordW)
72                      
73         1/1              assign sram_addr_o = SramBaseAddr + SramAw'(fifoptr[FifoPtrW-1:SubWordW]);
           Tests:       T1 T2 T3 
74                      
75                          always_comb begin
76         1/1                sram_wdata_o = '0;
           Tests:       T1 T2 T3 
77         1/1                sram_wmask_o = '0;
           Tests:       T1 T2 T3 
78         1/1                for(int unsigned i = 0; i < NumEntryPerWord ; i++) begin
           Tests:       T1 T2 T3 
79         1/1                  if (fifoptr[0+:SubWordW] == i) begin
           Tests:       T1 T2 T3 
80         1/1                    sram_wdata_o[i*FifoWidth+:FifoWidth] = wdata_i;
           Tests:       T1 T2 T3 
81         1/1                    sram_wmask_o[i*FifoWidth+:FifoWidth] = {FifoWidth{1'b1}};
           Tests:       T1 T2 T3 
82                              end
                        MISSING_ELSE
83                            end
84                          end
85                      
86                        end else begin : g_one_entry_per_word
87                          assign sram_addr_o = SramBaseAddr + SramAw'(fifoptr);
88                          assign sram_wdata_o = SramDw'(wdata_i);
89                          assign sram_wmask_o = SramDw'({1'b0, {FifoWidth{1'b1}}});
90                        end
91                      
92         1/1            assign sram_ack = sram_req_o && sram_gnt_i;
           Tests:       T1 T2 T3 
93                      
94         1/1            assign fifoptr_inc = sram_ack;
           Tests:       T1 T2 T3 
95                      
96                        always_ff @(posedge clk_i or negedge rst_ni) begin
97         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
98         1/1                fifoptr <= '0;
           Tests:       T1 T2 T3 
99         1/1              end else if (clr_i) begin
           Tests:       T3 T4 T5 
100        unreachable        fifoptr <= '0;
101        1/1              end else if (fifoptr_inc) begin
           Tests:       T3 T4 T5 
102        1/1                fifoptr <= (fifoptr == FifoPtrW'(FifoDepth-1))
           Tests:       T5 T9 T26 
103                                    ? '0 : fifoptr + 1'b1;
104                         end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_tpm_wr_buffer

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       56
 EXPRESSION (wvalid_i & ((!clr_i)))
             ----1---   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T5,T9,T26

 LINE       57
 EXPRESSION (sram_gnt_i & ((!clr_i)))
             -----1----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T5,T9,T26

 LINE       79
 EXPRESSION (fifoptr[0+:g_multiple_entry_per_word.SubWordW] == i)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T5,T9,T26

 LINE       102
 EXPRESSION ((fifoptr == 6'((FifoDepth - 1))) ? '0 : ((fifoptr + 1'b1)))
             ----------------1---------------

-1-	Status	Tests
0	Covered	T5,T9,T26
1	Covered	T9,T44,T47

 LINE       102
 SUB-EXPRESSION (fifoptr == 6'((FifoDepth - 1)))
                ----------------1---------------

-1-	Status	Tests
0	Covered	T5,T9,T26
1	Covered	T9,T44,T47

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_tpm_wr_buffer

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	97	4	4	100.00
IF	79	2	2	100.00

97             if (!rst_ni) begin
               -1-  
98               fifoptr <= '0;
                 ==>
99             end else if (clr_i) begin
                        -2-  
100              fifoptr <= '0;
                 ==> (Unreachable)
101            end else if (fifoptr_inc) begin
                        -3-     
102              fifoptr <= (fifoptr == FifoPtrW'(FifoDepth-1))
                                                               
103                       ? '0 : fifoptr + 1'b1;
                          -4-  
                          ==>  
                          ==>  
104            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	1	Covered	T9,T44,T47
0	0	1	0	Covered	T5,T9,T26
0	0	0	-	Covered	T3,T4,T5

79                 if (fifoptr[0+:SubWordW] == i) begin
                   -1-     
80                   sram_wdata_o[i*FifoWidth+:FifoWidth] = wdata_i;
                     ==>
81                   sram_wmask_o[i*FifoWidth+:FifoWidth] = {FifoWidth{1'b1}};
82                 end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_tpm_wr_buffer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_multiple_entry_per_word.NumEntryPerWordPowerOf2_A	956	956	0	0
g_multiple_entry_per_word.WidthDivideSramDw_A	956	956	0	0

g_multiple_entry_per_word.NumEntryPerWordPowerOf2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

g_multiple_entry_per_word.WidthDivideSramDw_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0