Unified Coverage Report :: Module :: prim_generic_clock_buf

Module : prim_generic_clock_buf

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_prim_generic_clock_buf_0/rtl/prim_generic_clock_buf.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_clk_spi_in_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_spi_out_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_csb_buf.gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.u_clk_spi_in_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_clk_spi_in_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_clk_spi_out_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_clk_spi_out_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_clk_csb_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_clk_csb_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_clock_buf

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	20	1	1	100.00
CONT_ASSIGN	21	1	1	100.00

19                        logic inv;
20         1/1            assign inv = ~clk_i;
           Tests:       T1 T2 T3 
21         1/1            assign clk_o = ~inv;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_clk_spi_in_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	20	1	1	100.00
CONT_ASSIGN	21	1	1	100.00

19                        logic inv;
20         1/1            assign inv = ~clk_i;
           Tests:       T1 T2 T3 
21         1/1            assign clk_o = ~inv;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_clk_spi_out_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	20	1	1	100.00
CONT_ASSIGN	21	1	1	100.00

19                        logic inv;
20         1/1            assign inv = ~clk_i;
           Tests:       T1 T2 T3 
21         1/1            assign clk_o = ~inv;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_clk_csb_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	20	1	1	100.00
CONT_ASSIGN	21	1	1	100.00

19                        logic inv;
20         1/1            assign inv = ~clk_i;
           Tests:       T1 T2 T3 
21         1/1            assign clk_o = ~inv;
           Tests:       T1 T2 T3