Line Coverage for Module :
prim_sram_arbiter ( parameter N=3,SramDw=32,SramAw=10,ArbiterImpl="PPC",EnMask=1 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 15 | 15 | 100.00 |
| CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 67 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 68 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 70 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 125 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 147 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
55 for (genvar i = 0 ; i < N ; i++) begin : gen_reqs
56 3/3 assign req_packed[i] = {
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3
57 req_write_i[i],
58 req_addr_i [i],
59 req_wdata_i[i],
60 (EnMask) ? req_wmask_i[i] : {SramDw{1'b1}}
61 };
62 end
63
64 localparam int ARB_DW = $bits(req_t);
65
66 req_t sram_packed;
67 1/1 assign sram_write_o = sram_packed.write;
Tests: T1 T2 T3
68 1/1 assign sram_addr_o = sram_packed.addr;
Tests: T1 T2 T3
69 1/1 assign sram_wdata_o = sram_packed.wdata;
Tests: T1 T2 T3
70 1/1 assign sram_wmask_o = (EnMask) ? sram_packed.wmask : {SramDw{1'b1}};
Tests: T1 T2 T3
71
72 if (EnMask == 1'b 0) begin : g_unused
73 logic unused_wmask;
74
75 always_comb begin
76 unused_wmask = 1'b 1;
77 for (int unsigned i = 0 ; i < N ; i++) begin
78 unused_wmask ^= ^req_wmask_i[i];
79 end
80 unused_wmask ^= ^sram_packed.wmask;
81 end
82 end
83
84
85 if (ArbiterImpl == "PPC") begin : gen_arb_ppc
86 prim_arbiter_ppc #(
87 .N (N),
88 .DW(ARB_DW)
89 ) u_reqarb (
90 .clk_i,
91 .rst_ni,
92 .req_chk_i ( 1'b1 ),
93 .req_i,
94 .data_i ( req_packed ),
95 .gnt_o,
96 .idx_o ( ),
97 .valid_o ( sram_req_o ),
98 .data_o ( sram_packed ),
99 .ready_i ( 1'b1 )
100 );
101 end else if (ArbiterImpl == "BINTREE") begin : gen_tree_arb
102 prim_arbiter_tree #(
103 .N (N),
104 .DW(ARB_DW)
105 ) u_reqarb (
106 .clk_i,
107 .rst_ni,
108 .req_chk_i ( 1'b1 ),
109 .req_i,
110 .data_i ( req_packed ),
111 .gnt_o,
112 .idx_o ( ),
113 .valid_o ( sram_req_o ),
114 .data_o ( sram_packed ),
115 .ready_i ( 1'b1 )
116 );
117 end else begin : gen_unknown
118 `ASSERT_INIT(UnknownArbImpl_A, 0)
119 end
120
121
122 logic [N-1:0] steer; // Steering sram_rvalid_i
123 logic sram_ack; // Ack for rvalid. |sram_rvalid_i
124
125 1/1 assign sram_ack = sram_rvalid_i & (|steer);
Tests: T1 T2 T3
126
127 // Request FIFO
128 prim_fifo_sync #(
129 .Width (N),
130 .Pass (1'b0),
131 .Depth (4) // Assume at most 4 pipelined
132 ) u_req_fifo (
133 .clk_i,
134 .rst_ni,
135 .clr_i (1'b0),
136 .wvalid_i (sram_req_o & ~sram_write_o), // Push only for read
137 .wready_o (), // TODO: Generate Error
138 .wdata_i (gnt_o),
139 .rvalid_o (), // TODO; Generate error if sram_rvalid_i but rvalid==0
140 .rready_i (sram_ack),
141 .rdata_o (steer),
142 .full_o (),
143 .depth_o (), // Not used
144 .err_o ()
145 );
146
147 1/1 assign rsp_rvalid_o = steer & {N{sram_rvalid_i}};
Tests: T1 T2 T3
148
149 for (genvar i = 0 ; i < N ; i++) begin : gen_rsp
150 3/3 assign rsp_rdata_o[i] = sram_rdata_i;
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3
151 3/3 assign rsp_error_o[i] = sram_rerror_i; // No SECDED yet
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3
Line Coverage for Module :
prim_sram_arbiter ( parameter N=2,SramDw=32,SramAw=10,ArbiterImpl="PPC",EnMask=1 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 12 | 12 | 100.00 |
| CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 67 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 68 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 70 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 125 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 147 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
55 for (genvar i = 0 ; i < N ; i++) begin : gen_reqs
56 2/2 assign req_packed[i] = {
Tests: T1 T2 T3 | T1 T2 T3
57 req_write_i[i],
58 req_addr_i [i],
59 req_wdata_i[i],
60 (EnMask) ? req_wmask_i[i] : {SramDw{1'b1}}
61 };
62 end
63
64 localparam int ARB_DW = $bits(req_t);
65
66 req_t sram_packed;
67 1/1 assign sram_write_o = sram_packed.write;
Tests: T1 T2 T3
68 1/1 assign sram_addr_o = sram_packed.addr;
Tests: T1 T2 T3
69 1/1 assign sram_wdata_o = sram_packed.wdata;
Tests: T1 T2 T3
70 1/1 assign sram_wmask_o = (EnMask) ? sram_packed.wmask : {SramDw{1'b1}};
Tests: T1 T2 T3
71
72 if (EnMask == 1'b 0) begin : g_unused
73 logic unused_wmask;
74
75 always_comb begin
76 unused_wmask = 1'b 1;
77 for (int unsigned i = 0 ; i < N ; i++) begin
78 unused_wmask ^= ^req_wmask_i[i];
79 end
80 unused_wmask ^= ^sram_packed.wmask;
81 end
82 end
83
84
85 if (ArbiterImpl == "PPC") begin : gen_arb_ppc
86 prim_arbiter_ppc #(
87 .N (N),
88 .DW(ARB_DW)
89 ) u_reqarb (
90 .clk_i,
91 .rst_ni,
92 .req_chk_i ( 1'b1 ),
93 .req_i,
94 .data_i ( req_packed ),
95 .gnt_o,
96 .idx_o ( ),
97 .valid_o ( sram_req_o ),
98 .data_o ( sram_packed ),
99 .ready_i ( 1'b1 )
100 );
101 end else if (ArbiterImpl == "BINTREE") begin : gen_tree_arb
102 prim_arbiter_tree #(
103 .N (N),
104 .DW(ARB_DW)
105 ) u_reqarb (
106 .clk_i,
107 .rst_ni,
108 .req_chk_i ( 1'b1 ),
109 .req_i,
110 .data_i ( req_packed ),
111 .gnt_o,
112 .idx_o ( ),
113 .valid_o ( sram_req_o ),
114 .data_o ( sram_packed ),
115 .ready_i ( 1'b1 )
116 );
117 end else begin : gen_unknown
118 `ASSERT_INIT(UnknownArbImpl_A, 0)
119 end
120
121
122 logic [N-1:0] steer; // Steering sram_rvalid_i
123 logic sram_ack; // Ack for rvalid. |sram_rvalid_i
124
125 1/1 assign sram_ack = sram_rvalid_i & (|steer);
Tests: T1 T2 T3
126
127 // Request FIFO
128 prim_fifo_sync #(
129 .Width (N),
130 .Pass (1'b0),
131 .Depth (4) // Assume at most 4 pipelined
132 ) u_req_fifo (
133 .clk_i,
134 .rst_ni,
135 .clr_i (1'b0),
136 .wvalid_i (sram_req_o & ~sram_write_o), // Push only for read
137 .wready_o (), // TODO: Generate Error
138 .wdata_i (gnt_o),
139 .rvalid_o (), // TODO; Generate error if sram_rvalid_i but rvalid==0
140 .rready_i (sram_ack),
141 .rdata_o (steer),
142 .full_o (),
143 .depth_o (), // Not used
144 .err_o ()
145 );
146
147 1/1 assign rsp_rvalid_o = steer & {N{sram_rvalid_i}};
Tests: T1 T2 T3
148
149 for (genvar i = 0 ; i < N ; i++) begin : gen_rsp
150 2/2 assign rsp_rdata_o[i] = sram_rdata_i;
Tests: T1 T2 T3 | T1 T2 T3
151 2/2 assign rsp_error_o[i] = sram_rerror_i; // No SECDED yet
Tests: T1 T2 T3 | T1 T2 T3
Line Coverage for Module :
prim_sram_arbiter ( parameter N=5,SramDw=32,SramAw=10,ArbiterImpl="PPC",EnMask=1 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 21 | 21 | 100.00 |
| CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 67 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 68 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 70 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 125 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 147 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
55 for (genvar i = 0 ; i < N ; i++) begin : gen_reqs
56 5/5 assign req_packed[i] = {
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
57 req_write_i[i],
58 req_addr_i [i],
59 req_wdata_i[i],
60 (EnMask) ? req_wmask_i[i] : {SramDw{1'b1}}
61 };
62 end
63
64 localparam int ARB_DW = $bits(req_t);
65
66 req_t sram_packed;
67 1/1 assign sram_write_o = sram_packed.write;
Tests: T1 T2 T3
68 1/1 assign sram_addr_o = sram_packed.addr;
Tests: T1 T2 T3
69 1/1 assign sram_wdata_o = sram_packed.wdata;
Tests: T1 T2 T3
70 1/1 assign sram_wmask_o = (EnMask) ? sram_packed.wmask : {SramDw{1'b1}};
Tests: T1 T2 T3
71
72 if (EnMask == 1'b 0) begin : g_unused
73 logic unused_wmask;
74
75 always_comb begin
76 unused_wmask = 1'b 1;
77 for (int unsigned i = 0 ; i < N ; i++) begin
78 unused_wmask ^= ^req_wmask_i[i];
79 end
80 unused_wmask ^= ^sram_packed.wmask;
81 end
82 end
83
84
85 if (ArbiterImpl == "PPC") begin : gen_arb_ppc
86 prim_arbiter_ppc #(
87 .N (N),
88 .DW(ARB_DW)
89 ) u_reqarb (
90 .clk_i,
91 .rst_ni,
92 .req_chk_i ( 1'b1 ),
93 .req_i,
94 .data_i ( req_packed ),
95 .gnt_o,
96 .idx_o ( ),
97 .valid_o ( sram_req_o ),
98 .data_o ( sram_packed ),
99 .ready_i ( 1'b1 )
100 );
101 end else if (ArbiterImpl == "BINTREE") begin : gen_tree_arb
102 prim_arbiter_tree #(
103 .N (N),
104 .DW(ARB_DW)
105 ) u_reqarb (
106 .clk_i,
107 .rst_ni,
108 .req_chk_i ( 1'b1 ),
109 .req_i,
110 .data_i ( req_packed ),
111 .gnt_o,
112 .idx_o ( ),
113 .valid_o ( sram_req_o ),
114 .data_o ( sram_packed ),
115 .ready_i ( 1'b1 )
116 );
117 end else begin : gen_unknown
118 `ASSERT_INIT(UnknownArbImpl_A, 0)
119 end
120
121
122 logic [N-1:0] steer; // Steering sram_rvalid_i
123 logic sram_ack; // Ack for rvalid. |sram_rvalid_i
124
125 1/1 assign sram_ack = sram_rvalid_i & (|steer);
Tests: T1 T2 T3
126
127 // Request FIFO
128 prim_fifo_sync #(
129 .Width (N),
130 .Pass (1'b0),
131 .Depth (4) // Assume at most 4 pipelined
132 ) u_req_fifo (
133 .clk_i,
134 .rst_ni,
135 .clr_i (1'b0),
136 .wvalid_i (sram_req_o & ~sram_write_o), // Push only for read
137 .wready_o (), // TODO: Generate Error
138 .wdata_i (gnt_o),
139 .rvalid_o (), // TODO; Generate error if sram_rvalid_i but rvalid==0
140 .rready_i (sram_ack),
141 .rdata_o (steer),
142 .full_o (),
143 .depth_o (), // Not used
144 .err_o ()
145 );
146
147 1/1 assign rsp_rvalid_o = steer & {N{sram_rvalid_i}};
Tests: T1 T2 T3
148
149 for (genvar i = 0 ; i < N ; i++) begin : gen_rsp
150 5/5 assign rsp_rdata_o[i] = sram_rdata_i;
Tests: T5 T9 T26 | T5 T9 T26 | T5 T9 T26 | T5 T9 T26 | T5 T9 T26
151 5/5 assign rsp_error_o[i] = sram_rerror_i; // No SECDED yet
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
Cond Coverage for Module :
prim_sram_arbiter
| Total | Covered | Percent |
|---|
| Conditions | 6 | 5 | 83.33 |
| Logical | 6 | 5 | 83.33 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 125
EXPRESSION (sram_rvalid_i & ((|steer)))
------1------ -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T47,T49,T45 |
| 1 | 1 | Covered | T5,T9,T26 |
LINE 132
EXPRESSION (sram_req_o & ((~sram_write_o)))
-----1---- --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T5,T6,T7 |
| 1 | 1 | Covered | T5,T9,T26 |
Line Coverage for Instance : tb.dut.u_upload.u_arbiter
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 15 | 15 | 100.00 |
| CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 67 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 68 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 70 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 125 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 147 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
55 for (genvar i = 0 ; i < N ; i++) begin : gen_reqs
56 3/3 assign req_packed[i] = {
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3
57 req_write_i[i],
58 req_addr_i [i],
59 req_wdata_i[i],
60 (EnMask) ? req_wmask_i[i] : {SramDw{1'b1}}
61 };
62 end
63
64 localparam int ARB_DW = $bits(req_t);
65
66 req_t sram_packed;
67 1/1 assign sram_write_o = sram_packed.write;
Tests: T1 T2 T3
68 1/1 assign sram_addr_o = sram_packed.addr;
Tests: T1 T2 T3
69 1/1 assign sram_wdata_o = sram_packed.wdata;
Tests: T1 T2 T3
70 1/1 assign sram_wmask_o = (EnMask) ? sram_packed.wmask : {SramDw{1'b1}};
Tests: T1 T2 T3
71
72 if (EnMask == 1'b 0) begin : g_unused
73 logic unused_wmask;
74
75 always_comb begin
76 unused_wmask = 1'b 1;
77 for (int unsigned i = 0 ; i < N ; i++) begin
78 unused_wmask ^= ^req_wmask_i[i];
79 end
80 unused_wmask ^= ^sram_packed.wmask;
81 end
82 end
83
84
85 if (ArbiterImpl == "PPC") begin : gen_arb_ppc
86 prim_arbiter_ppc #(
87 .N (N),
88 .DW(ARB_DW)
89 ) u_reqarb (
90 .clk_i,
91 .rst_ni,
92 .req_chk_i ( 1'b1 ),
93 .req_i,
94 .data_i ( req_packed ),
95 .gnt_o,
96 .idx_o ( ),
97 .valid_o ( sram_req_o ),
98 .data_o ( sram_packed ),
99 .ready_i ( 1'b1 )
100 );
101 end else if (ArbiterImpl == "BINTREE") begin : gen_tree_arb
102 prim_arbiter_tree #(
103 .N (N),
104 .DW(ARB_DW)
105 ) u_reqarb (
106 .clk_i,
107 .rst_ni,
108 .req_chk_i ( 1'b1 ),
109 .req_i,
110 .data_i ( req_packed ),
111 .gnt_o,
112 .idx_o ( ),
113 .valid_o ( sram_req_o ),
114 .data_o ( sram_packed ),
115 .ready_i ( 1'b1 )
116 );
117 end else begin : gen_unknown
118 `ASSERT_INIT(UnknownArbImpl_A, 0)
119 end
120
121
122 logic [N-1:0] steer; // Steering sram_rvalid_i
123 logic sram_ack; // Ack for rvalid. |sram_rvalid_i
124
125 1/1 assign sram_ack = sram_rvalid_i & (|steer);
Tests: T1 T2 T3
126
127 // Request FIFO
128 prim_fifo_sync #(
129 .Width (N),
130 .Pass (1'b0),
131 .Depth (4) // Assume at most 4 pipelined
132 ) u_req_fifo (
133 .clk_i,
134 .rst_ni,
135 .clr_i (1'b0),
136 .wvalid_i (sram_req_o & ~sram_write_o), // Push only for read
137 .wready_o (), // TODO: Generate Error
138 .wdata_i (gnt_o),
139 .rvalid_o (), // TODO; Generate error if sram_rvalid_i but rvalid==0
140 .rready_i (sram_ack),
141 .rdata_o (steer),
142 .full_o (),
143 .depth_o (), // Not used
144 .err_o ()
145 );
146
147 1/1 assign rsp_rvalid_o = steer & {N{sram_rvalid_i}};
Tests: T1 T2 T3
148
149 for (genvar i = 0 ; i < N ; i++) begin : gen_rsp
150 3/3 assign rsp_rdata_o[i] = sram_rdata_i;
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3
151 3/3 assign rsp_error_o[i] = sram_rerror_i; // No SECDED yet
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3
Cond Coverage for Instance : tb.dut.u_upload.u_arbiter
| Total | Covered | Percent |
|---|
| Conditions | 6 | 2 | 33.33 |
| Logical | 6 | 2 | 33.33 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 125
EXPRESSION (sram_rvalid_i & ((|steer)))
------1------ -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 132
EXPRESSION (sram_req_o & ((~sram_write_o)))
-----1---- --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T40,T47,T48 |
| 1 | 1 | Not Covered | |
Line Coverage for Instance : tb.dut.u_sys_sram_arbiter
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 21 | 21 | 100.00 |
| CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 67 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 68 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 70 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 125 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 147 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
55 for (genvar i = 0 ; i < N ; i++) begin : gen_reqs
56 5/5 assign req_packed[i] = {
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
57 req_write_i[i],
58 req_addr_i [i],
59 req_wdata_i[i],
60 (EnMask) ? req_wmask_i[i] : {SramDw{1'b1}}
61 };
62 end
63
64 localparam int ARB_DW = $bits(req_t);
65
66 req_t sram_packed;
67 1/1 assign sram_write_o = sram_packed.write;
Tests: T1 T2 T3
68 1/1 assign sram_addr_o = sram_packed.addr;
Tests: T1 T2 T3
69 1/1 assign sram_wdata_o = sram_packed.wdata;
Tests: T1 T2 T3
70 1/1 assign sram_wmask_o = (EnMask) ? sram_packed.wmask : {SramDw{1'b1}};
Tests: T1 T2 T3
71
72 if (EnMask == 1'b 0) begin : g_unused
73 logic unused_wmask;
74
75 always_comb begin
76 unused_wmask = 1'b 1;
77 for (int unsigned i = 0 ; i < N ; i++) begin
78 unused_wmask ^= ^req_wmask_i[i];
79 end
80 unused_wmask ^= ^sram_packed.wmask;
81 end
82 end
83
84
85 if (ArbiterImpl == "PPC") begin : gen_arb_ppc
86 prim_arbiter_ppc #(
87 .N (N),
88 .DW(ARB_DW)
89 ) u_reqarb (
90 .clk_i,
91 .rst_ni,
92 .req_chk_i ( 1'b1 ),
93 .req_i,
94 .data_i ( req_packed ),
95 .gnt_o,
96 .idx_o ( ),
97 .valid_o ( sram_req_o ),
98 .data_o ( sram_packed ),
99 .ready_i ( 1'b1 )
100 );
101 end else if (ArbiterImpl == "BINTREE") begin : gen_tree_arb
102 prim_arbiter_tree #(
103 .N (N),
104 .DW(ARB_DW)
105 ) u_reqarb (
106 .clk_i,
107 .rst_ni,
108 .req_chk_i ( 1'b1 ),
109 .req_i,
110 .data_i ( req_packed ),
111 .gnt_o,
112 .idx_o ( ),
113 .valid_o ( sram_req_o ),
114 .data_o ( sram_packed ),
115 .ready_i ( 1'b1 )
116 );
117 end else begin : gen_unknown
118 `ASSERT_INIT(UnknownArbImpl_A, 0)
119 end
120
121
122 logic [N-1:0] steer; // Steering sram_rvalid_i
123 logic sram_ack; // Ack for rvalid. |sram_rvalid_i
124
125 1/1 assign sram_ack = sram_rvalid_i & (|steer);
Tests: T1 T2 T3
126
127 // Request FIFO
128 prim_fifo_sync #(
129 .Width (N),
130 .Pass (1'b0),
131 .Depth (4) // Assume at most 4 pipelined
132 ) u_req_fifo (
133 .clk_i,
134 .rst_ni,
135 .clr_i (1'b0),
136 .wvalid_i (sram_req_o & ~sram_write_o), // Push only for read
137 .wready_o (), // TODO: Generate Error
138 .wdata_i (gnt_o),
139 .rvalid_o (), // TODO; Generate error if sram_rvalid_i but rvalid==0
140 .rready_i (sram_ack),
141 .rdata_o (steer),
142 .full_o (),
143 .depth_o (), // Not used
144 .err_o ()
145 );
146
147 1/1 assign rsp_rvalid_o = steer & {N{sram_rvalid_i}};
Tests: T1 T2 T3
148
149 for (genvar i = 0 ; i < N ; i++) begin : gen_rsp
150 5/5 assign rsp_rdata_o[i] = sram_rdata_i;
Tests: T5 T9 T26 | T5 T9 T26 | T5 T9 T26 | T5 T9 T26 | T5 T9 T26
151 5/5 assign rsp_error_o[i] = sram_rerror_i; // No SECDED yet
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter
| Total | Covered | Percent |
|---|
| Conditions | 6 | 4 | 66.67 |
| Logical | 6 | 4 | 66.67 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 125
EXPRESSION (sram_rvalid_i & ((|steer)))
------1------ -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T5,T9,T26 |
LINE 132
EXPRESSION (sram_req_o & ((~sram_write_o)))
-----1---- --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T5,T6,T7 |
| 1 | 1 | Covered | T5,T9,T26 |
Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 12 | 12 | 100.00 |
| CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 67 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 68 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 70 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 125 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 147 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
55 for (genvar i = 0 ; i < N ; i++) begin : gen_reqs
56 2/2 assign req_packed[i] = {
Tests: T1 T2 T3 | T1 T2 T3
57 req_write_i[i],
58 req_addr_i [i],
59 req_wdata_i[i],
60 (EnMask) ? req_wmask_i[i] : {SramDw{1'b1}}
61 };
62 end
63
64 localparam int ARB_DW = $bits(req_t);
65
66 req_t sram_packed;
67 1/1 assign sram_write_o = sram_packed.write;
Tests: T1 T2 T3
68 1/1 assign sram_addr_o = sram_packed.addr;
Tests: T1 T2 T3
69 1/1 assign sram_wdata_o = sram_packed.wdata;
Tests: T1 T2 T3
70 1/1 assign sram_wmask_o = (EnMask) ? sram_packed.wmask : {SramDw{1'b1}};
Tests: T1 T2 T3
71
72 if (EnMask == 1'b 0) begin : g_unused
73 logic unused_wmask;
74
75 always_comb begin
76 unused_wmask = 1'b 1;
77 for (int unsigned i = 0 ; i < N ; i++) begin
78 unused_wmask ^= ^req_wmask_i[i];
79 end
80 unused_wmask ^= ^sram_packed.wmask;
81 end
82 end
83
84
85 if (ArbiterImpl == "PPC") begin : gen_arb_ppc
86 prim_arbiter_ppc #(
87 .N (N),
88 .DW(ARB_DW)
89 ) u_reqarb (
90 .clk_i,
91 .rst_ni,
92 .req_chk_i ( 1'b1 ),
93 .req_i,
94 .data_i ( req_packed ),
95 .gnt_o,
96 .idx_o ( ),
97 .valid_o ( sram_req_o ),
98 .data_o ( sram_packed ),
99 .ready_i ( 1'b1 )
100 );
101 end else if (ArbiterImpl == "BINTREE") begin : gen_tree_arb
102 prim_arbiter_tree #(
103 .N (N),
104 .DW(ARB_DW)
105 ) u_reqarb (
106 .clk_i,
107 .rst_ni,
108 .req_chk_i ( 1'b1 ),
109 .req_i,
110 .data_i ( req_packed ),
111 .gnt_o,
112 .idx_o ( ),
113 .valid_o ( sram_req_o ),
114 .data_o ( sram_packed ),
115 .ready_i ( 1'b1 )
116 );
117 end else begin : gen_unknown
118 `ASSERT_INIT(UnknownArbImpl_A, 0)
119 end
120
121
122 logic [N-1:0] steer; // Steering sram_rvalid_i
123 logic sram_ack; // Ack for rvalid. |sram_rvalid_i
124
125 1/1 assign sram_ack = sram_rvalid_i & (|steer);
Tests: T1 T2 T3
126
127 // Request FIFO
128 prim_fifo_sync #(
129 .Width (N),
130 .Pass (1'b0),
131 .Depth (4) // Assume at most 4 pipelined
132 ) u_req_fifo (
133 .clk_i,
134 .rst_ni,
135 .clr_i (1'b0),
136 .wvalid_i (sram_req_o & ~sram_write_o), // Push only for read
137 .wready_o (), // TODO: Generate Error
138 .wdata_i (gnt_o),
139 .rvalid_o (), // TODO; Generate error if sram_rvalid_i but rvalid==0
140 .rready_i (sram_ack),
141 .rdata_o (steer),
142 .full_o (),
143 .depth_o (), // Not used
144 .err_o ()
145 );
146
147 1/1 assign rsp_rvalid_o = steer & {N{sram_rvalid_i}};
Tests: T1 T2 T3
148
149 for (genvar i = 0 ; i < N ; i++) begin : gen_rsp
150 2/2 assign rsp_rdata_o[i] = sram_rdata_i;
Tests: T1 T2 T3 | T1 T2 T3
151 2/2 assign rsp_error_o[i] = sram_rerror_i; // No SECDED yet
Tests: T1 T2 T3 | T1 T2 T3
Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter
| Total | Covered | Percent |
|---|
| Conditions | 6 | 5 | 83.33 |
| Logical | 6 | 5 | 83.33 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 125
EXPRESSION (sram_rvalid_i & ((|steer)))
------1------ -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T47,T49,T45 |
| 1 | 1 | Covered | T5,T9,T26 |
LINE 132
EXPRESSION (sram_req_o & ((~sram_write_o)))
-----1---- --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T5,T9,T26 |
| 1 | 1 | Covered | T5,T9,T26 |