Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	437635185	2943785	0	0
DepthKnown_A	437635185	437510202	0	0
RvalidKnown_A	437635185	437510202	0	0
WreadyKnown_A	437635185	437510202	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437635185	2943785	0	0
T6	35391	832	0	0
T7	135296	832	0	0
T8	6995	1663	0	0
T9	134827	0	0	0
T10	4487	1663	0	0
T11	12375	832	0	0
T12	141906	1666	0	0
T13	158548	1663	0	0
T14	8761	0	0	0
T16	0	1666	0	0
T17	0	832	0	0
T18	0	1663	0	0
T39	881	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437635185	437510202	0	0
T1	1736	1677	0	0
T2	1517	1437	0	0
T3	59373	59322	0	0
T4	1691	1639	0	0
T5	1730	1666	0	0
T6	35391	35336	0	0
T7	135296	135234	0	0
T8	6995	6928	0	0
T9	134827	134737	0	0
T10	4487	4431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437635185	437510202	0	0
T1	1736	1677	0	0
T2	1517	1437	0	0
T3	59373	59322	0	0
T4	1691	1639	0	0
T5	1730	1666	0	0
T6	35391	35336	0	0
T7	135296	135234	0	0
T8	6995	6928	0	0
T9	134827	134737	0	0
T10	4487	4431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437635185	437510202	0	0
T1	1736	1677	0	0
T2	1517	1437	0	0
T3	59373	59322	0	0
T4	1691	1639	0	0
T5	1730	1666	0	0
T6	35391	35336	0	0
T7	135296	135234	0	0
T8	6995	6928	0	0
T9	134827	134737	0	0
T10	4487	4431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	437635185	3316226	0	0
DepthKnown_A	437635185	437510202	0	0
RvalidKnown_A	437635185	437510202	0	0
WreadyKnown_A	437635185	437510202	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437635185	3316226	0	0
T6	35391	3801	0	0
T7	135296	832	0	0
T8	6995	832	0	0
T9	134827	0	0	0
T10	4487	832	0	0
T11	12375	2539	0	0
T12	141906	835	0	0
T13	158548	832	0	0
T14	8761	0	0	0
T16	0	835	0	0
T17	0	3744	0	0
T18	0	832	0	0
T39	881	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437635185	437510202	0	0
T1	1736	1677	0	0
T2	1517	1437	0	0
T3	59373	59322	0	0
T4	1691	1639	0	0
T5	1730	1666	0	0
T6	35391	35336	0	0
T7	135296	135234	0	0
T8	6995	6928	0	0
T9	134827	134737	0	0
T10	4487	4431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437635185	437510202	0	0
T1	1736	1677	0	0
T2	1517	1437	0	0
T3	59373	59322	0	0
T4	1691	1639	0	0
T5	1730	1666	0	0
T6	35391	35336	0	0
T7	135296	135234	0	0
T8	6995	6928	0	0
T9	134827	134737	0	0
T10	4487	4431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437635185	437510202	0	0
T1	1736	1677	0	0
T2	1517	1437	0	0
T3	59373	59322	0	0
T4	1691	1639	0	0
T5	1730	1666	0	0
T6	35391	35336	0	0
T7	135296	135234	0	0
T8	6995	6928	0	0
T9	134827	134737	0	0
T10	4487	4431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	437635185	203640	0	0
DepthKnown_A	437635185	437510202	0	0
RvalidKnown_A	437635185	437510202	0	0
WreadyKnown_A	437635185	437510202	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437635185	203640	0	0
T5	1730	2	0	0
T6	35391	0	0	0
T7	135296	0	0	0
T8	6995	0	0	0
T9	134827	812	0	0
T10	4487	0	0	0
T11	12375	0	0	0
T12	141906	0	0	0
T13	158548	0	0	0
T26	0	7	0	0
T31	0	30	0	0
T39	881	0	0	0
T40	0	128	0	0
T44	0	768	0	0
T47	0	976	0	0
T48	0	193	0	0
T49	0	241	0	0
T50	0	43	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437635185	437510202	0	0
T1	1736	1677	0	0
T2	1517	1437	0	0
T3	59373	59322	0	0
T4	1691	1639	0	0
T5	1730	1666	0	0
T6	35391	35336	0	0
T7	135296	135234	0	0
T8	6995	6928	0	0
T9	134827	134737	0	0
T10	4487	4431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437635185	437510202	0	0
T1	1736	1677	0	0
T2	1517	1437	0	0
T3	59373	59322	0	0
T4	1691	1639	0	0
T5	1730	1666	0	0
T6	35391	35336	0	0
T7	135296	135234	0	0
T8	6995	6928	0	0
T9	134827	134737	0	0
T10	4487	4431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437635185	437510202	0	0
T1	1736	1677	0	0
T2	1517	1437	0	0
T3	59373	59322	0	0
T4	1691	1639	0	0
T5	1730	1666	0	0
T6	35391	35336	0	0
T7	135296	135234	0	0
T8	6995	6928	0	0
T9	134827	134737	0	0
T10	4487	4431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	437635185	452809	0	0
DepthKnown_A	437635185	437510202	0	0
RvalidKnown_A	437635185	437510202	0	0
WreadyKnown_A	437635185	437510202	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437635185	452809	0	0
T5	1730	2	0	0
T6	35391	0	0	0
T7	135296	0	0	0
T8	6995	0	0	0
T9	134827	812	0	0
T10	4487	0	0	0
T11	12375	0	0	0
T12	141906	0	0	0
T13	158548	0	0	0
T26	0	7	0	0
T31	0	30	0	0
T39	881	0	0	0
T40	0	128	0	0
T44	0	768	0	0
T47	0	975	0	0
T48	0	193	0	0
T49	0	241	0	0
T50	0	43	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437635185	437510202	0	0
T1	1736	1677	0	0
T2	1517	1437	0	0
T3	59373	59322	0	0
T4	1691	1639	0	0
T5	1730	1666	0	0
T6	35391	35336	0	0
T7	135296	135234	0	0
T8	6995	6928	0	0
T9	134827	134737	0	0
T10	4487	4431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437635185	437510202	0	0
T1	1736	1677	0	0
T2	1517	1437	0	0
T3	59373	59322	0	0
T4	1691	1639	0	0
T5	1730	1666	0	0
T6	35391	35336	0	0
T7	135296	135234	0	0
T8	6995	6928	0	0
T9	134827	134737	0	0
T10	4487	4431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437635185	437510202	0	0
T1	1736	1677	0	0
T2	1517	1437	0	0
T3	59373	59322	0	0
T4	1691	1639	0	0
T5	1730	1666	0	0
T6	35391	35336	0	0
T7	135296	135234	0	0
T8	6995	6928	0	0
T9	134827	134737	0	0
T10	4487	4431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	437635185	6122933	0	0
DepthKnown_A	437635185	437510202	0	0
RvalidKnown_A	437635185	437510202	0	0
WreadyKnown_A	437635185	437510202	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437635185	6122933	0	0
T1	1736	63	0	0
T2	1517	1	0	0
T3	59373	352	0	0
T4	1691	17	0	0
T5	1730	458	0	0
T6	35391	63	0	0
T7	135296	54	0	0
T8	6995	203	0	0
T9	134827	6625	0	0
T10	4487	114	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437635185	437510202	0	0
T1	1736	1677	0	0
T2	1517	1437	0	0
T3	59373	59322	0	0
T4	1691	1639	0	0
T5	1730	1666	0	0
T6	35391	35336	0	0
T7	135296	135234	0	0
T8	6995	6928	0	0
T9	134827	134737	0	0
T10	4487	4431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437635185	437510202	0	0
T1	1736	1677	0	0
T2	1517	1437	0	0
T3	59373	59322	0	0
T4	1691	1639	0	0
T5	1730	1666	0	0
T6	35391	35336	0	0
T7	135296	135234	0	0
T8	6995	6928	0	0
T9	134827	134737	0	0
T10	4487	4431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437635185	437510202	0	0
T1	1736	1677	0	0
T2	1517	1437	0	0
T3	59373	59322	0	0
T4	1691	1639	0	0
T5	1730	1666	0	0
T6	35391	35336	0	0
T7	135296	135234	0	0
T8	6995	6928	0	0
T9	134827	134737	0	0
T10	4487	4431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	437635185	12580048	0	0
DepthKnown_A	437635185	437510202	0	0
RvalidKnown_A	437635185	437510202	0	0
WreadyKnown_A	437635185	437510202	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437635185	12580048	0	0
T1	1736	188	0	0
T2	1517	2	0	0
T3	59373	352	0	0
T4	1691	17	0	0
T5	1730	458	0	0
T6	35391	278	0	0
T7	135296	54	0	0
T8	6995	203	0	0
T9	134827	6492	0	0
T10	4487	297	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437635185	437510202	0	0
T1	1736	1677	0	0
T2	1517	1437	0	0
T3	59373	59322	0	0
T4	1691	1639	0	0
T5	1730	1666	0	0
T6	35391	35336	0	0
T7	135296	135234	0	0
T8	6995	6928	0	0
T9	134827	134737	0	0
T10	4487	4431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437635185	437510202	0	0
T1	1736	1677	0	0
T2	1517	1437	0	0
T3	59373	59322	0	0
T4	1691	1639	0	0
T5	1730	1666	0	0
T6	35391	35336	0	0
T7	135296	135234	0	0
T8	6995	6928	0	0
T9	134827	134737	0	0
T10	4487	4431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437635185	437510202	0	0
T1	1736	1677	0	0
T2	1517	1437	0	0
T3	59373	59322	0	0
T4	1691	1639	0	0
T5	1730	1666	0	0
T6	35391	35336	0	0
T7	135296	135234	0	0
T8	6995	6928	0	0
T9	134827	134737	0	0
T10	4487	4431	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0