Assert Coverage for Module : 
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
3750 | 
0 | 
0 | 
| T87 | 
7951 | 
111 | 
0 | 
0 | 
| T88 | 
4633 | 
15 | 
0 | 
0 | 
| T89 | 
20784 | 
2 | 
0 | 
0 | 
| T103 | 
20129 | 
227 | 
0 | 
0 | 
| T107 | 
6908 | 
136 | 
0 | 
0 | 
| T108 | 
9953 | 
86 | 
0 | 
0 | 
| T110 | 
8952 | 
100 | 
0 | 
0 | 
| T114 | 
12228 | 
13 | 
0 | 
0 | 
| T115 | 
11162 | 
2 | 
0 | 
0 | 
| T121 | 
3809 | 
22 | 
0 | 
0 | 
addr_swap_data_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
2644 | 
0 | 
0 | 
| T115 | 
11162 | 
12 | 
0 | 
0 | 
| T116 | 
13862 | 
19 | 
0 | 
0 | 
| T119 | 
33128 | 
16 | 
0 | 
0 | 
| T122 | 
37825 | 
25 | 
0 | 
0 | 
| T130 | 
10363 | 
13 | 
0 | 
0 | 
| T148 | 
13878 | 
48 | 
0 | 
0 | 
| T154 | 
7664 | 
21 | 
0 | 
0 | 
| T155 | 
35366 | 
160 | 
0 | 
0 | 
| T156 | 
89955 | 
210 | 
0 | 
0 | 
| T157 | 
124620 | 
810 | 
0 | 
0 | 
addr_swap_mask_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
2570 | 
0 | 
0 | 
| T115 | 
11162 | 
17 | 
0 | 
0 | 
| T116 | 
13862 | 
19 | 
0 | 
0 | 
| T119 | 
33128 | 
17 | 
0 | 
0 | 
| T122 | 
37825 | 
26 | 
0 | 
0 | 
| T130 | 
10363 | 
6 | 
0 | 
0 | 
| T148 | 
13878 | 
37 | 
0 | 
0 | 
| T154 | 
7664 | 
8 | 
0 | 
0 | 
| T155 | 
35366 | 
130 | 
0 | 
0 | 
| T156 | 
89955 | 
241 | 
0 | 
0 | 
| T157 | 
124620 | 
778 | 
0 | 
0 | 
cfg_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
3042 | 
0 | 
0 | 
| T115 | 
11162 | 
18 | 
0 | 
0 | 
| T116 | 
13862 | 
37 | 
0 | 
0 | 
| T119 | 
33128 | 
37 | 
0 | 
0 | 
| T122 | 
37825 | 
71 | 
0 | 
0 | 
| T130 | 
10363 | 
16 | 
0 | 
0 | 
| T148 | 
13878 | 
72 | 
0 | 
0 | 
| T154 | 
7664 | 
16 | 
0 | 
0 | 
| T155 | 
35366 | 
139 | 
0 | 
0 | 
| T156 | 
89955 | 
233 | 
0 | 
0 | 
| T157 | 
124620 | 
791 | 
0 | 
0 | 
cmd_filter_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
9630 | 
0 | 
0 | 
| T115 | 
11162 | 
266 | 
0 | 
0 | 
| T116 | 
13862 | 
156 | 
0 | 
0 | 
| T119 | 
33128 | 
263 | 
0 | 
0 | 
| T122 | 
37825 | 
656 | 
0 | 
0 | 
| T130 | 
10363 | 
118 | 
0 | 
0 | 
| T148 | 
13878 | 
51 | 
0 | 
0 | 
| T154 | 
7664 | 
41 | 
0 | 
0 | 
| T155 | 
35366 | 
164 | 
0 | 
0 | 
| T156 | 
89955 | 
242 | 
0 | 
0 | 
| T157 | 
124620 | 
865 | 
0 | 
0 | 
cmd_filter_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
10363 | 
0 | 
0 | 
| T115 | 
11162 | 
128 | 
0 | 
0 | 
| T116 | 
13862 | 
212 | 
0 | 
0 | 
| T119 | 
33128 | 
395 | 
0 | 
0 | 
| T122 | 
37825 | 
715 | 
0 | 
0 | 
| T130 | 
10363 | 
76 | 
0 | 
0 | 
| T148 | 
13878 | 
13 | 
0 | 
0 | 
| T154 | 
7664 | 
43 | 
0 | 
0 | 
| T155 | 
35366 | 
158 | 
0 | 
0 | 
| T156 | 
89955 | 
238 | 
0 | 
0 | 
| T157 | 
124620 | 
722 | 
0 | 
0 | 
cmd_filter_2_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
9318 | 
0 | 
0 | 
| T115 | 
11162 | 
250 | 
0 | 
0 | 
| T116 | 
13862 | 
112 | 
0 | 
0 | 
| T119 | 
33128 | 
227 | 
0 | 
0 | 
| T122 | 
37825 | 
855 | 
0 | 
0 | 
| T130 | 
10363 | 
2 | 
0 | 
0 | 
| T148 | 
13878 | 
34 | 
0 | 
0 | 
| T154 | 
7664 | 
12 | 
0 | 
0 | 
| T155 | 
35366 | 
116 | 
0 | 
0 | 
| T156 | 
89955 | 
224 | 
0 | 
0 | 
| T157 | 
124620 | 
858 | 
0 | 
0 | 
cmd_filter_3_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
9390 | 
0 | 
0 | 
| T115 | 
11162 | 
211 | 
0 | 
0 | 
| T116 | 
13862 | 
230 | 
0 | 
0 | 
| T119 | 
33128 | 
347 | 
0 | 
0 | 
| T122 | 
37825 | 
778 | 
0 | 
0 | 
| T130 | 
10363 | 
153 | 
0 | 
0 | 
| T148 | 
13878 | 
27 | 
0 | 
0 | 
| T154 | 
7664 | 
47 | 
0 | 
0 | 
| T155 | 
35366 | 
125 | 
0 | 
0 | 
| T156 | 
89955 | 
216 | 
0 | 
0 | 
| T157 | 
124620 | 
742 | 
0 | 
0 | 
cmd_filter_4_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
10062 | 
0 | 
0 | 
| T115 | 
11162 | 
149 | 
0 | 
0 | 
| T116 | 
13862 | 
126 | 
0 | 
0 | 
| T119 | 
33128 | 
250 | 
0 | 
0 | 
| T122 | 
37825 | 
625 | 
0 | 
0 | 
| T130 | 
10363 | 
67 | 
0 | 
0 | 
| T148 | 
13878 | 
42 | 
0 | 
0 | 
| T154 | 
7664 | 
28 | 
0 | 
0 | 
| T155 | 
35366 | 
170 | 
0 | 
0 | 
| T156 | 
89955 | 
213 | 
0 | 
0 | 
| T157 | 
124620 | 
790 | 
0 | 
0 | 
cmd_filter_5_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
10108 | 
0 | 
0 | 
| T115 | 
11162 | 
134 | 
0 | 
0 | 
| T116 | 
13862 | 
150 | 
0 | 
0 | 
| T119 | 
33128 | 
484 | 
0 | 
0 | 
| T122 | 
37825 | 
609 | 
0 | 
0 | 
| T130 | 
10363 | 
117 | 
0 | 
0 | 
| T148 | 
13878 | 
38 | 
0 | 
0 | 
| T154 | 
7664 | 
21 | 
0 | 
0 | 
| T155 | 
35366 | 
155 | 
0 | 
0 | 
| T156 | 
89955 | 
213 | 
0 | 
0 | 
| T157 | 
124620 | 
819 | 
0 | 
0 | 
cmd_filter_6_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
10150 | 
0 | 
0 | 
| T115 | 
11162 | 
16 | 
0 | 
0 | 
| T116 | 
13862 | 
140 | 
0 | 
0 | 
| T119 | 
33128 | 
357 | 
0 | 
0 | 
| T122 | 
37825 | 
837 | 
0 | 
0 | 
| T130 | 
10363 | 
182 | 
0 | 
0 | 
| T148 | 
13878 | 
48 | 
0 | 
0 | 
| T154 | 
7664 | 
32 | 
0 | 
0 | 
| T155 | 
35366 | 
128 | 
0 | 
0 | 
| T156 | 
89955 | 
261 | 
0 | 
0 | 
| T157 | 
124620 | 
797 | 
0 | 
0 | 
cmd_filter_7_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
9650 | 
0 | 
0 | 
| T115 | 
11162 | 
181 | 
0 | 
0 | 
| T116 | 
13862 | 
23 | 
0 | 
0 | 
| T119 | 
33128 | 
438 | 
0 | 
0 | 
| T122 | 
37825 | 
503 | 
0 | 
0 | 
| T130 | 
10363 | 
132 | 
0 | 
0 | 
| T148 | 
13878 | 
40 | 
0 | 
0 | 
| T154 | 
7664 | 
19 | 
0 | 
0 | 
| T155 | 
35366 | 
159 | 
0 | 
0 | 
| T156 | 
89955 | 
228 | 
0 | 
0 | 
| T157 | 
124620 | 
798 | 
0 | 
0 | 
cmd_info_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
5070 | 
0 | 
0 | 
| T115 | 
11162 | 
63 | 
0 | 
0 | 
| T116 | 
13862 | 
149 | 
0 | 
0 | 
| T119 | 
33128 | 
139 | 
0 | 
0 | 
| T122 | 
37825 | 
258 | 
0 | 
0 | 
| T130 | 
10363 | 
64 | 
0 | 
0 | 
| T148 | 
13878 | 
65 | 
0 | 
0 | 
| T154 | 
7664 | 
15 | 
0 | 
0 | 
| T155 | 
35366 | 
154 | 
0 | 
0 | 
| T156 | 
89955 | 
194 | 
0 | 
0 | 
| T157 | 
124620 | 
753 | 
0 | 
0 | 
cmd_info_10_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
5194 | 
0 | 
0 | 
| T115 | 
11162 | 
71 | 
0 | 
0 | 
| T116 | 
13862 | 
142 | 
0 | 
0 | 
| T119 | 
33128 | 
229 | 
0 | 
0 | 
| T122 | 
37825 | 
248 | 
0 | 
0 | 
| T130 | 
10363 | 
80 | 
0 | 
0 | 
| T148 | 
13878 | 
19 | 
0 | 
0 | 
| T154 | 
7664 | 
12 | 
0 | 
0 | 
| T155 | 
35366 | 
151 | 
0 | 
0 | 
| T156 | 
89955 | 
203 | 
0 | 
0 | 
| T157 | 
124620 | 
750 | 
0 | 
0 | 
cmd_info_11_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
5701 | 
0 | 
0 | 
| T115 | 
11162 | 
55 | 
0 | 
0 | 
| T116 | 
13862 | 
161 | 
0 | 
0 | 
| T119 | 
33128 | 
230 | 
0 | 
0 | 
| T122 | 
37825 | 
381 | 
0 | 
0 | 
| T130 | 
10363 | 
21 | 
0 | 
0 | 
| T148 | 
13878 | 
45 | 
0 | 
0 | 
| T154 | 
7664 | 
18 | 
0 | 
0 | 
| T155 | 
35366 | 
170 | 
0 | 
0 | 
| T156 | 
89955 | 
214 | 
0 | 
0 | 
| T157 | 
124620 | 
864 | 
0 | 
0 | 
cmd_info_12_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
5743 | 
0 | 
0 | 
| T115 | 
11162 | 
22 | 
0 | 
0 | 
| T116 | 
13862 | 
88 | 
0 | 
0 | 
| T119 | 
33128 | 
162 | 
0 | 
0 | 
| T122 | 
37825 | 
301 | 
0 | 
0 | 
| T130 | 
10363 | 
35 | 
0 | 
0 | 
| T148 | 
13878 | 
61 | 
0 | 
0 | 
| T154 | 
7664 | 
5 | 
0 | 
0 | 
| T155 | 
35366 | 
158 | 
0 | 
0 | 
| T156 | 
89955 | 
185 | 
0 | 
0 | 
| T157 | 
124620 | 
935 | 
0 | 
0 | 
cmd_info_13_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
5237 | 
0 | 
0 | 
| T115 | 
11162 | 
88 | 
0 | 
0 | 
| T116 | 
13862 | 
21 | 
0 | 
0 | 
| T119 | 
33128 | 
154 | 
0 | 
0 | 
| T122 | 
37825 | 
349 | 
0 | 
0 | 
| T130 | 
10363 | 
30 | 
0 | 
0 | 
| T148 | 
13878 | 
23 | 
0 | 
0 | 
| T154 | 
7664 | 
20 | 
0 | 
0 | 
| T155 | 
35366 | 
114 | 
0 | 
0 | 
| T156 | 
89955 | 
206 | 
0 | 
0 | 
| T157 | 
124620 | 
802 | 
0 | 
0 | 
cmd_info_14_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
5135 | 
0 | 
0 | 
| T115 | 
11162 | 
9 | 
0 | 
0 | 
| T116 | 
13862 | 
50 | 
0 | 
0 | 
| T119 | 
33128 | 
92 | 
0 | 
0 | 
| T122 | 
37825 | 
328 | 
0 | 
0 | 
| T130 | 
10363 | 
36 | 
0 | 
0 | 
| T148 | 
13878 | 
40 | 
0 | 
0 | 
| T154 | 
7664 | 
24 | 
0 | 
0 | 
| T155 | 
35366 | 
158 | 
0 | 
0 | 
| T156 | 
89955 | 
247 | 
0 | 
0 | 
| T157 | 
124620 | 
815 | 
0 | 
0 | 
cmd_info_15_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
5484 | 
0 | 
0 | 
| T115 | 
11162 | 
59 | 
0 | 
0 | 
| T116 | 
13862 | 
79 | 
0 | 
0 | 
| T119 | 
33128 | 
130 | 
0 | 
0 | 
| T122 | 
37825 | 
225 | 
0 | 
0 | 
| T130 | 
10363 | 
48 | 
0 | 
0 | 
| T148 | 
13878 | 
37 | 
0 | 
0 | 
| T154 | 
7664 | 
17 | 
0 | 
0 | 
| T155 | 
35366 | 
210 | 
0 | 
0 | 
| T156 | 
89955 | 
222 | 
0 | 
0 | 
| T157 | 
124620 | 
752 | 
0 | 
0 | 
cmd_info_16_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
5303 | 
0 | 
0 | 
| T115 | 
11162 | 
114 | 
0 | 
0 | 
| T116 | 
13862 | 
180 | 
0 | 
0 | 
| T119 | 
33128 | 
72 | 
0 | 
0 | 
| T122 | 
37825 | 
301 | 
0 | 
0 | 
| T130 | 
10363 | 
54 | 
0 | 
0 | 
| T148 | 
13878 | 
24 | 
0 | 
0 | 
| T154 | 
7664 | 
26 | 
0 | 
0 | 
| T155 | 
35366 | 
157 | 
0 | 
0 | 
| T156 | 
89955 | 
254 | 
0 | 
0 | 
| T157 | 
124620 | 
850 | 
0 | 
0 | 
cmd_info_17_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
5742 | 
0 | 
0 | 
| T115 | 
11162 | 
35 | 
0 | 
0 | 
| T116 | 
13862 | 
8 | 
0 | 
0 | 
| T119 | 
33128 | 
190 | 
0 | 
0 | 
| T122 | 
37825 | 
346 | 
0 | 
0 | 
| T130 | 
10363 | 
64 | 
0 | 
0 | 
| T148 | 
13878 | 
27 | 
0 | 
0 | 
| T154 | 
7664 | 
55 | 
0 | 
0 | 
| T155 | 
35366 | 
152 | 
0 | 
0 | 
| T156 | 
89955 | 
231 | 
0 | 
0 | 
| T157 | 
124620 | 
755 | 
0 | 
0 | 
cmd_info_18_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
5378 | 
0 | 
0 | 
| T115 | 
11162 | 
3 | 
0 | 
0 | 
| T116 | 
13862 | 
132 | 
0 | 
0 | 
| T119 | 
33128 | 
114 | 
0 | 
0 | 
| T122 | 
37825 | 
180 | 
0 | 
0 | 
| T130 | 
10363 | 
40 | 
0 | 
0 | 
| T148 | 
13878 | 
33 | 
0 | 
0 | 
| T154 | 
7664 | 
24 | 
0 | 
0 | 
| T155 | 
35366 | 
208 | 
0 | 
0 | 
| T156 | 
89955 | 
194 | 
0 | 
0 | 
| T157 | 
124620 | 
792 | 
0 | 
0 | 
cmd_info_19_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
4834 | 
0 | 
0 | 
| T115 | 
11162 | 
20 | 
0 | 
0 | 
| T116 | 
13862 | 
76 | 
0 | 
0 | 
| T119 | 
33128 | 
94 | 
0 | 
0 | 
| T122 | 
37825 | 
115 | 
0 | 
0 | 
| T130 | 
10363 | 
27 | 
0 | 
0 | 
| T148 | 
13878 | 
34 | 
0 | 
0 | 
| T154 | 
7664 | 
6 | 
0 | 
0 | 
| T155 | 
35366 | 
161 | 
0 | 
0 | 
| T156 | 
89955 | 
209 | 
0 | 
0 | 
| T157 | 
124620 | 
763 | 
0 | 
0 | 
cmd_info_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
5602 | 
0 | 
0 | 
| T115 | 
11162 | 
59 | 
0 | 
0 | 
| T116 | 
13862 | 
116 | 
0 | 
0 | 
| T119 | 
33128 | 
154 | 
0 | 
0 | 
| T122 | 
37825 | 
332 | 
0 | 
0 | 
| T130 | 
10363 | 
58 | 
0 | 
0 | 
| T148 | 
13878 | 
37 | 
0 | 
0 | 
| T154 | 
7664 | 
16 | 
0 | 
0 | 
| T155 | 
35366 | 
134 | 
0 | 
0 | 
| T156 | 
89955 | 
184 | 
0 | 
0 | 
| T157 | 
124620 | 
790 | 
0 | 
0 | 
cmd_info_20_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
4911 | 
0 | 
0 | 
| T115 | 
11162 | 
72 | 
0 | 
0 | 
| T116 | 
13862 | 
62 | 
0 | 
0 | 
| T119 | 
33128 | 
87 | 
0 | 
0 | 
| T122 | 
37825 | 
294 | 
0 | 
0 | 
| T130 | 
10363 | 
14 | 
0 | 
0 | 
| T148 | 
13878 | 
23 | 
0 | 
0 | 
| T154 | 
7664 | 
18 | 
0 | 
0 | 
| T155 | 
35366 | 
127 | 
0 | 
0 | 
| T156 | 
89955 | 
233 | 
0 | 
0 | 
| T157 | 
124620 | 
793 | 
0 | 
0 | 
cmd_info_21_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
5582 | 
0 | 
0 | 
| T115 | 
11162 | 
10 | 
0 | 
0 | 
| T116 | 
13862 | 
112 | 
0 | 
0 | 
| T119 | 
33128 | 
145 | 
0 | 
0 | 
| T122 | 
37825 | 
265 | 
0 | 
0 | 
| T130 | 
10363 | 
97 | 
0 | 
0 | 
| T148 | 
13878 | 
47 | 
0 | 
0 | 
| T154 | 
7664 | 
1 | 
0 | 
0 | 
| T155 | 
35366 | 
159 | 
0 | 
0 | 
| T156 | 
89955 | 
234 | 
0 | 
0 | 
| T157 | 
124620 | 
795 | 
0 | 
0 | 
cmd_info_22_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
5270 | 
0 | 
0 | 
| T115 | 
11162 | 
72 | 
0 | 
0 | 
| T116 | 
13862 | 
11 | 
0 | 
0 | 
| T119 | 
33128 | 
140 | 
0 | 
0 | 
| T122 | 
37825 | 
255 | 
0 | 
0 | 
| T130 | 
10363 | 
52 | 
0 | 
0 | 
| T148 | 
13878 | 
58 | 
0 | 
0 | 
| T154 | 
7664 | 
39 | 
0 | 
0 | 
| T155 | 
35366 | 
191 | 
0 | 
0 | 
| T156 | 
89955 | 
246 | 
0 | 
0 | 
| T157 | 
124620 | 
796 | 
0 | 
0 | 
cmd_info_23_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
5074 | 
0 | 
0 | 
| T115 | 
11162 | 
71 | 
0 | 
0 | 
| T116 | 
13862 | 
23 | 
0 | 
0 | 
| T119 | 
33128 | 
143 | 
0 | 
0 | 
| T122 | 
37825 | 
278 | 
0 | 
0 | 
| T130 | 
10363 | 
27 | 
0 | 
0 | 
| T148 | 
13878 | 
43 | 
0 | 
0 | 
| T154 | 
7664 | 
21 | 
0 | 
0 | 
| T155 | 
35366 | 
181 | 
0 | 
0 | 
| T156 | 
89955 | 
212 | 
0 | 
0 | 
| T157 | 
124620 | 
823 | 
0 | 
0 | 
cmd_info_2_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
5710 | 
0 | 
0 | 
| T115 | 
11162 | 
49 | 
0 | 
0 | 
| T116 | 
13862 | 
129 | 
0 | 
0 | 
| T119 | 
33128 | 
192 | 
0 | 
0 | 
| T122 | 
37825 | 
218 | 
0 | 
0 | 
| T130 | 
10363 | 
9 | 
0 | 
0 | 
| T148 | 
13878 | 
56 | 
0 | 
0 | 
| T154 | 
7664 | 
10 | 
0 | 
0 | 
| T155 | 
35366 | 
157 | 
0 | 
0 | 
| T156 | 
89955 | 
243 | 
0 | 
0 | 
| T157 | 
124620 | 
792 | 
0 | 
0 | 
cmd_info_3_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
5364 | 
0 | 
0 | 
| T115 | 
11162 | 
64 | 
0 | 
0 | 
| T116 | 
13862 | 
59 | 
0 | 
0 | 
| T119 | 
33128 | 
122 | 
0 | 
0 | 
| T122 | 
37825 | 
234 | 
0 | 
0 | 
| T130 | 
10363 | 
27 | 
0 | 
0 | 
| T148 | 
13878 | 
39 | 
0 | 
0 | 
| T154 | 
7664 | 
20 | 
0 | 
0 | 
| T155 | 
35366 | 
132 | 
0 | 
0 | 
| T156 | 
89955 | 
225 | 
0 | 
0 | 
| T157 | 
124620 | 
742 | 
0 | 
0 | 
cmd_info_4_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
5459 | 
0 | 
0 | 
| T115 | 
11162 | 
8 | 
0 | 
0 | 
| T116 | 
13862 | 
46 | 
0 | 
0 | 
| T119 | 
33128 | 
169 | 
0 | 
0 | 
| T122 | 
37825 | 
290 | 
0 | 
0 | 
| T130 | 
10363 | 
69 | 
0 | 
0 | 
| T148 | 
13878 | 
17 | 
0 | 
0 | 
| T154 | 
7664 | 
4 | 
0 | 
0 | 
| T155 | 
35366 | 
124 | 
0 | 
0 | 
| T156 | 
89955 | 
200 | 
0 | 
0 | 
| T157 | 
124620 | 
776 | 
0 | 
0 | 
cmd_info_5_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
5227 | 
0 | 
0 | 
| T115 | 
11162 | 
65 | 
0 | 
0 | 
| T116 | 
13862 | 
124 | 
0 | 
0 | 
| T119 | 
33128 | 
146 | 
0 | 
0 | 
| T122 | 
37825 | 
287 | 
0 | 
0 | 
| T130 | 
10363 | 
17 | 
0 | 
0 | 
| T148 | 
13878 | 
45 | 
0 | 
0 | 
| T154 | 
7664 | 
23 | 
0 | 
0 | 
| T155 | 
35366 | 
149 | 
0 | 
0 | 
| T156 | 
89955 | 
254 | 
0 | 
0 | 
| T157 | 
124620 | 
770 | 
0 | 
0 | 
cmd_info_6_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
5693 | 
0 | 
0 | 
| T115 | 
11162 | 
59 | 
0 | 
0 | 
| T116 | 
13862 | 
75 | 
0 | 
0 | 
| T119 | 
33128 | 
93 | 
0 | 
0 | 
| T122 | 
37825 | 
259 | 
0 | 
0 | 
| T130 | 
10363 | 
33 | 
0 | 
0 | 
| T148 | 
13878 | 
65 | 
0 | 
0 | 
| T154 | 
7664 | 
8 | 
0 | 
0 | 
| T155 | 
35366 | 
124 | 
0 | 
0 | 
| T156 | 
89955 | 
174 | 
0 | 
0 | 
| T157 | 
124620 | 
858 | 
0 | 
0 | 
cmd_info_7_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
5474 | 
0 | 
0 | 
| T115 | 
11162 | 
133 | 
0 | 
0 | 
| T116 | 
13862 | 
67 | 
0 | 
0 | 
| T119 | 
33128 | 
148 | 
0 | 
0 | 
| T122 | 
37825 | 
158 | 
0 | 
0 | 
| T130 | 
10363 | 
24 | 
0 | 
0 | 
| T148 | 
13878 | 
31 | 
0 | 
0 | 
| T154 | 
7664 | 
5 | 
0 | 
0 | 
| T155 | 
35366 | 
143 | 
0 | 
0 | 
| T156 | 
89955 | 
245 | 
0 | 
0 | 
| T157 | 
124620 | 
763 | 
0 | 
0 | 
cmd_info_8_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
5162 | 
0 | 
0 | 
| T115 | 
11162 | 
58 | 
0 | 
0 | 
| T116 | 
13862 | 
18 | 
0 | 
0 | 
| T119 | 
33128 | 
141 | 
0 | 
0 | 
| T122 | 
37825 | 
341 | 
0 | 
0 | 
| T130 | 
10363 | 
57 | 
0 | 
0 | 
| T148 | 
13878 | 
45 | 
0 | 
0 | 
| T154 | 
7664 | 
33 | 
0 | 
0 | 
| T155 | 
35366 | 
163 | 
0 | 
0 | 
| T156 | 
89955 | 
206 | 
0 | 
0 | 
| T157 | 
124620 | 
738 | 
0 | 
0 | 
cmd_info_9_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
5232 | 
0 | 
0 | 
| T115 | 
11162 | 
118 | 
0 | 
0 | 
| T116 | 
13862 | 
135 | 
0 | 
0 | 
| T119 | 
33128 | 
187 | 
0 | 
0 | 
| T122 | 
37825 | 
330 | 
0 | 
0 | 
| T130 | 
10363 | 
1 | 
0 | 
0 | 
| T148 | 
13878 | 
46 | 
0 | 
0 | 
| T154 | 
7664 | 
7 | 
0 | 
0 | 
| T155 | 
35366 | 
149 | 
0 | 
0 | 
| T156 | 
89955 | 
194 | 
0 | 
0 | 
| T157 | 
124620 | 
748 | 
0 | 
0 | 
cmd_info_en4b_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
2729 | 
0 | 
0 | 
| T115 | 
11162 | 
11 | 
0 | 
0 | 
| T116 | 
13862 | 
35 | 
0 | 
0 | 
| T119 | 
33128 | 
25 | 
0 | 
0 | 
| T122 | 
37825 | 
39 | 
0 | 
0 | 
| T130 | 
10363 | 
20 | 
0 | 
0 | 
| T148 | 
13878 | 
62 | 
0 | 
0 | 
| T154 | 
7664 | 
38 | 
0 | 
0 | 
| T155 | 
35366 | 
168 | 
0 | 
0 | 
| T156 | 
89955 | 
176 | 
0 | 
0 | 
| T157 | 
124620 | 
730 | 
0 | 
0 | 
cmd_info_ex4b_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
2860 | 
0 | 
0 | 
| T115 | 
11162 | 
23 | 
0 | 
0 | 
| T116 | 
13862 | 
31 | 
0 | 
0 | 
| T119 | 
33128 | 
19 | 
0 | 
0 | 
| T122 | 
37825 | 
60 | 
0 | 
0 | 
| T130 | 
10363 | 
2 | 
0 | 
0 | 
| T148 | 
13878 | 
40 | 
0 | 
0 | 
| T154 | 
7664 | 
28 | 
0 | 
0 | 
| T155 | 
35366 | 
127 | 
0 | 
0 | 
| T156 | 
89955 | 
201 | 
0 | 
0 | 
| T157 | 
124620 | 
803 | 
0 | 
0 | 
cmd_info_wrdi_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
2718 | 
0 | 
0 | 
| T115 | 
11162 | 
15 | 
0 | 
0 | 
| T116 | 
13862 | 
7 | 
0 | 
0 | 
| T119 | 
33128 | 
25 | 
0 | 
0 | 
| T122 | 
37825 | 
47 | 
0 | 
0 | 
| T148 | 
13878 | 
89 | 
0 | 
0 | 
| T154 | 
7664 | 
19 | 
0 | 
0 | 
| T155 | 
35366 | 
134 | 
0 | 
0 | 
| T156 | 
89955 | 
212 | 
0 | 
0 | 
| T157 | 
124620 | 
780 | 
0 | 
0 | 
| T158 | 
8943 | 
20 | 
0 | 
0 | 
cmd_info_wren_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
2740 | 
0 | 
0 | 
| T115 | 
11162 | 
20 | 
0 | 
0 | 
| T116 | 
13862 | 
27 | 
0 | 
0 | 
| T119 | 
33128 | 
29 | 
0 | 
0 | 
| T122 | 
37825 | 
67 | 
0 | 
0 | 
| T130 | 
10363 | 
1 | 
0 | 
0 | 
| T148 | 
13878 | 
52 | 
0 | 
0 | 
| T154 | 
7664 | 
31 | 
0 | 
0 | 
| T155 | 
35366 | 
149 | 
0 | 
0 | 
| T156 | 
89955 | 
225 | 
0 | 
0 | 
| T157 | 
124620 | 
790 | 
0 | 
0 | 
intercept_en_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
3195 | 
0 | 
0 | 
| T115 | 
11162 | 
22 | 
0 | 
0 | 
| T116 | 
13862 | 
52 | 
0 | 
0 | 
| T119 | 
33128 | 
52 | 
0 | 
0 | 
| T122 | 
37825 | 
115 | 
0 | 
0 | 
| T130 | 
10363 | 
16 | 
0 | 
0 | 
| T148 | 
13878 | 
28 | 
0 | 
0 | 
| T154 | 
7664 | 
11 | 
0 | 
0 | 
| T155 | 
35366 | 
191 | 
0 | 
0 | 
| T156 | 
89955 | 
238 | 
0 | 
0 | 
| T157 | 
124620 | 
785 | 
0 | 
0 | 
intr_enable_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
4733 | 
0 | 
0 | 
| T21 | 
774209 | 
70 | 
0 | 
0 | 
| T22 | 
3083 | 
0 | 
0 | 
0 | 
| T36 | 
0 | 
35 | 
0 | 
0 | 
| T63 | 
18707 | 
0 | 
0 | 
0 | 
| T96 | 
2649 | 
0 | 
0 | 
0 | 
| T149 | 
94554 | 
0 | 
0 | 
0 | 
| T150 | 
81106 | 
0 | 
0 | 
0 | 
| T159 | 
0 | 
22 | 
0 | 
0 | 
| T160 | 
0 | 
11 | 
0 | 
0 | 
| T161 | 
0 | 
18 | 
0 | 
0 | 
| T162 | 
0 | 
21 | 
0 | 
0 | 
| T163 | 
0 | 
32 | 
0 | 
0 | 
| T164 | 
0 | 
46 | 
0 | 
0 | 
| T165 | 
0 | 
23 | 
0 | 
0 | 
| T166 | 
0 | 
32 | 
0 | 
0 | 
| T167 | 
759 | 
0 | 
0 | 
0 | 
| T168 | 
1536 | 
0 | 
0 | 
0 | 
| T169 | 
6664 | 
0 | 
0 | 
0 | 
| T170 | 
57682 | 
0 | 
0 | 
0 | 
jedec_cc_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
2838 | 
0 | 
0 | 
| T115 | 
11162 | 
22 | 
0 | 
0 | 
| T116 | 
13862 | 
28 | 
0 | 
0 | 
| T119 | 
33128 | 
25 | 
0 | 
0 | 
| T122 | 
37825 | 
58 | 
0 | 
0 | 
| T130 | 
10363 | 
6 | 
0 | 
0 | 
| T148 | 
13878 | 
51 | 
0 | 
0 | 
| T154 | 
7664 | 
39 | 
0 | 
0 | 
| T155 | 
35366 | 
111 | 
0 | 
0 | 
| T156 | 
89955 | 
211 | 
0 | 
0 | 
| T157 | 
124620 | 
769 | 
0 | 
0 | 
jedec_id_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
2677 | 
0 | 
0 | 
| T115 | 
11162 | 
17 | 
0 | 
0 | 
| T116 | 
13862 | 
23 | 
0 | 
0 | 
| T119 | 
33128 | 
25 | 
0 | 
0 | 
| T122 | 
37825 | 
39 | 
0 | 
0 | 
| T130 | 
10363 | 
14 | 
0 | 
0 | 
| T148 | 
13878 | 
21 | 
0 | 
0 | 
| T154 | 
7664 | 
10 | 
0 | 
0 | 
| T155 | 
35366 | 
182 | 
0 | 
0 | 
| T156 | 
89955 | 
243 | 
0 | 
0 | 
| T157 | 
124620 | 
815 | 
0 | 
0 | 
mailbox_addr_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
2611 | 
0 | 
0 | 
| T115 | 
11162 | 
25 | 
0 | 
0 | 
| T116 | 
13862 | 
14 | 
0 | 
0 | 
| T119 | 
33128 | 
44 | 
0 | 
0 | 
| T122 | 
37825 | 
49 | 
0 | 
0 | 
| T130 | 
10363 | 
6 | 
0 | 
0 | 
| T148 | 
13878 | 
64 | 
0 | 
0 | 
| T154 | 
7664 | 
12 | 
0 | 
0 | 
| T155 | 
35366 | 
146 | 
0 | 
0 | 
| T156 | 
89955 | 
214 | 
0 | 
0 | 
| T157 | 
124620 | 
817 | 
0 | 
0 | 
payload_swap_data_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
2657 | 
0 | 
0 | 
| T115 | 
11162 | 
19 | 
0 | 
0 | 
| T116 | 
13862 | 
21 | 
0 | 
0 | 
| T119 | 
33128 | 
6 | 
0 | 
0 | 
| T122 | 
37825 | 
30 | 
0 | 
0 | 
| T130 | 
10363 | 
11 | 
0 | 
0 | 
| T148 | 
13878 | 
71 | 
0 | 
0 | 
| T154 | 
7664 | 
25 | 
0 | 
0 | 
| T155 | 
35366 | 
119 | 
0 | 
0 | 
| T156 | 
89955 | 
216 | 
0 | 
0 | 
| T157 | 
124620 | 
856 | 
0 | 
0 | 
payload_swap_mask_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
2735 | 
0 | 
0 | 
| T115 | 
11162 | 
14 | 
0 | 
0 | 
| T116 | 
13862 | 
13 | 
0 | 
0 | 
| T119 | 
33128 | 
7 | 
0 | 
0 | 
| T122 | 
37825 | 
48 | 
0 | 
0 | 
| T130 | 
10363 | 
1 | 
0 | 
0 | 
| T148 | 
13878 | 
44 | 
0 | 
0 | 
| T154 | 
7664 | 
33 | 
0 | 
0 | 
| T155 | 
35366 | 
160 | 
0 | 
0 | 
| T156 | 
89955 | 
232 | 
0 | 
0 | 
| T157 | 
124620 | 
782 | 
0 | 
0 | 
read_threshold_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
2507 | 
0 | 
0 | 
| T115 | 
11162 | 
17 | 
0 | 
0 | 
| T116 | 
13862 | 
21 | 
0 | 
0 | 
| T119 | 
33128 | 
23 | 
0 | 
0 | 
| T122 | 
37825 | 
52 | 
0 | 
0 | 
| T148 | 
13878 | 
39 | 
0 | 
0 | 
| T154 | 
7664 | 
18 | 
0 | 
0 | 
| T155 | 
35366 | 
151 | 
0 | 
0 | 
| T156 | 
89955 | 
234 | 
0 | 
0 | 
| T157 | 
124620 | 
734 | 
0 | 
0 | 
| T158 | 
8943 | 
8 | 
0 | 
0 | 
tpm_access_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
3340 | 
0 | 
0 | 
| T115 | 
11162 | 
32 | 
0 | 
0 | 
| T116 | 
13862 | 
44 | 
0 | 
0 | 
| T119 | 
33128 | 
49 | 
0 | 
0 | 
| T122 | 
37825 | 
86 | 
0 | 
0 | 
| T130 | 
10363 | 
5 | 
0 | 
0 | 
| T148 | 
13878 | 
38 | 
0 | 
0 | 
| T154 | 
7664 | 
24 | 
0 | 
0 | 
| T155 | 
35366 | 
163 | 
0 | 
0 | 
| T156 | 
89955 | 
221 | 
0 | 
0 | 
| T157 | 
124620 | 
811 | 
0 | 
0 | 
tpm_access_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
2539 | 
0 | 
0 | 
| T115 | 
11162 | 
12 | 
0 | 
0 | 
| T116 | 
13862 | 
22 | 
0 | 
0 | 
| T119 | 
33128 | 
13 | 
0 | 
0 | 
| T122 | 
37825 | 
50 | 
0 | 
0 | 
| T130 | 
10363 | 
5 | 
0 | 
0 | 
| T148 | 
13878 | 
42 | 
0 | 
0 | 
| T154 | 
7664 | 
22 | 
0 | 
0 | 
| T155 | 
35366 | 
162 | 
0 | 
0 | 
| T156 | 
89955 | 
241 | 
0 | 
0 | 
| T157 | 
124620 | 
817 | 
0 | 
0 | 
tpm_cfg_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
3334 | 
0 | 
0 | 
| T115 | 
11162 | 
29 | 
0 | 
0 | 
| T116 | 
13862 | 
20 | 
0 | 
0 | 
| T119 | 
33128 | 
89 | 
0 | 
0 | 
| T122 | 
37825 | 
110 | 
0 | 
0 | 
| T130 | 
10363 | 
5 | 
0 | 
0 | 
| T148 | 
13878 | 
13 | 
0 | 
0 | 
| T154 | 
7664 | 
20 | 
0 | 
0 | 
| T155 | 
35366 | 
115 | 
0 | 
0 | 
| T156 | 
89955 | 
228 | 
0 | 
0 | 
| T157 | 
124620 | 
819 | 
0 | 
0 | 
tpm_did_vid_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
2926 | 
0 | 
0 | 
| T115 | 
11162 | 
19 | 
0 | 
0 | 
| T116 | 
13862 | 
43 | 
0 | 
0 | 
| T119 | 
33128 | 
35 | 
0 | 
0 | 
| T122 | 
37825 | 
54 | 
0 | 
0 | 
| T130 | 
10363 | 
8 | 
0 | 
0 | 
| T148 | 
13878 | 
89 | 
0 | 
0 | 
| T154 | 
7664 | 
13 | 
0 | 
0 | 
| T155 | 
35366 | 
166 | 
0 | 
0 | 
| T156 | 
89955 | 
232 | 
0 | 
0 | 
| T157 | 
124620 | 
815 | 
0 | 
0 | 
tpm_int_enable_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
2611 | 
0 | 
0 | 
| T115 | 
11162 | 
13 | 
0 | 
0 | 
| T116 | 
13862 | 
15 | 
0 | 
0 | 
| T119 | 
33128 | 
27 | 
0 | 
0 | 
| T122 | 
37825 | 
33 | 
0 | 
0 | 
| T130 | 
10363 | 
7 | 
0 | 
0 | 
| T148 | 
13878 | 
31 | 
0 | 
0 | 
| T154 | 
7664 | 
48 | 
0 | 
0 | 
| T155 | 
35366 | 
120 | 
0 | 
0 | 
| T156 | 
89955 | 
207 | 
0 | 
0 | 
| T157 | 
124620 | 
812 | 
0 | 
0 | 
tpm_int_status_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
2493 | 
0 | 
0 | 
| T115 | 
11162 | 
4 | 
0 | 
0 | 
| T116 | 
13862 | 
13 | 
0 | 
0 | 
| T119 | 
33128 | 
17 | 
0 | 
0 | 
| T122 | 
37825 | 
26 | 
0 | 
0 | 
| T148 | 
13878 | 
68 | 
0 | 
0 | 
| T154 | 
7664 | 
38 | 
0 | 
0 | 
| T155 | 
35366 | 
139 | 
0 | 
0 | 
| T156 | 
89955 | 
229 | 
0 | 
0 | 
| T157 | 
124620 | 
822 | 
0 | 
0 | 
| T158 | 
8943 | 
9 | 
0 | 
0 | 
tpm_int_vector_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
2465 | 
0 | 
0 | 
| T115 | 
11162 | 
18 | 
0 | 
0 | 
| T116 | 
13862 | 
14 | 
0 | 
0 | 
| T119 | 
33128 | 
16 | 
0 | 
0 | 
| T122 | 
37825 | 
52 | 
0 | 
0 | 
| T130 | 
10363 | 
7 | 
0 | 
0 | 
| T148 | 
13878 | 
41 | 
0 | 
0 | 
| T154 | 
7664 | 
7 | 
0 | 
0 | 
| T155 | 
35366 | 
188 | 
0 | 
0 | 
| T156 | 
89955 | 
243 | 
0 | 
0 | 
| T157 | 
124620 | 
785 | 
0 | 
0 | 
tpm_intf_capability_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
2568 | 
0 | 
0 | 
| T115 | 
11162 | 
12 | 
0 | 
0 | 
| T116 | 
13862 | 
18 | 
0 | 
0 | 
| T119 | 
33128 | 
14 | 
0 | 
0 | 
| T122 | 
37825 | 
31 | 
0 | 
0 | 
| T130 | 
10363 | 
10 | 
0 | 
0 | 
| T148 | 
13878 | 
23 | 
0 | 
0 | 
| T154 | 
7664 | 
38 | 
0 | 
0 | 
| T155 | 
35366 | 
175 | 
0 | 
0 | 
| T156 | 
89955 | 
234 | 
0 | 
0 | 
| T157 | 
124620 | 
801 | 
0 | 
0 | 
tpm_rid_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
2568 | 
0 | 
0 | 
| T115 | 
11162 | 
18 | 
0 | 
0 | 
| T116 | 
13862 | 
28 | 
0 | 
0 | 
| T119 | 
33128 | 
8 | 
0 | 
0 | 
| T122 | 
37825 | 
42 | 
0 | 
0 | 
| T130 | 
10363 | 
9 | 
0 | 
0 | 
| T148 | 
13878 | 
67 | 
0 | 
0 | 
| T154 | 
7664 | 
17 | 
0 | 
0 | 
| T155 | 
35366 | 
141 | 
0 | 
0 | 
| T156 | 
89955 | 
213 | 
0 | 
0 | 
| T157 | 
124620 | 
805 | 
0 | 
0 | 
tpm_sts_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
437635185 | 
2520 | 
0 | 
0 | 
| T115 | 
11162 | 
10 | 
0 | 
0 | 
| T116 | 
13862 | 
6 | 
0 | 
0 | 
| T119 | 
33128 | 
25 | 
0 | 
0 | 
| T122 | 
37825 | 
36 | 
0 | 
0 | 
| T130 | 
10363 | 
8 | 
0 | 
0 | 
| T148 | 
13878 | 
28 | 
0 | 
0 | 
| T154 | 
7664 | 
3 | 
0 | 
0 | 
| T155 | 
35366 | 
206 | 
0 | 
0 | 
| T156 | 
89955 | 
250 | 
0 | 
0 | 
| T157 | 
124620 | 
742 | 
0 | 
0 |