Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4491017	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4818575

1

T1

1

T2

1

T3

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	5190535	1			T1	43		T2	1		T3	2
values[0x0]	2059593	1			T3	6		T4	8		T5	14
values[0x1]	2059464	1			T3	3		T4	5		T5	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3162176	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

6147416

1

T1

15

T2

1

T3

9

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	34130	1			T5	2		T8	8		T9	49
valid_sources[0x01]	33680	1			T8	11		T9	19		T10	3
valid_sources[0x02]	33106	1			T8	9		T9	54		T10	10
valid_sources[0x03]	36588	1			T5	1		T8	15		T9	9
valid_sources[0x04]	41428	1			T5	2		T8	11		T9	24
valid_sources[0x05]	35483	1			T5	4		T8	11		T9	79
valid_sources[0x06]	36028	1			T5	2		T8	14		T9	32
valid_sources[0x07]	36506	1			T5	1		T8	5		T9	43
valid_sources[0x08]	35138	1			T8	9		T9	8		T10	2
valid_sources[0x09]	39954	1			T5	3		T8	12		T9	10
valid_sources[0x0a]	37952	1			T5	4		T8	16		T9	38
valid_sources[0x0b]	34222	1			T8	8		T9	41		T24	6
valid_sources[0x0c]	30310	1			T8	9		T9	53		T11	17
valid_sources[0x0d]	37481	1			T8	11		T9	20		T10	3
valid_sources[0x0e]	35084	1			T5	2		T8	16		T9	46
valid_sources[0x0f]	39453	1			T8	7		T9	44		T24	4
valid_sources[0x10]	36735	1			T5	1		T8	13		T9	42
valid_sources[0x11]	35359	1			T5	3		T8	9		T9	18
valid_sources[0x12]	34260	1			T8	10		T9	9		T10	1
valid_sources[0x13]	37278	1			T8	12		T9	38		T10	4
valid_sources[0x14]	36704	1			T5	1		T8	14		T9	18
valid_sources[0x15]	40542	1			T8	7		T9	10		T10	1
valid_sources[0x16]	34652	1			T8	13		T9	44		T24	7
valid_sources[0x17]	35767	1			T5	2		T8	1		T9	47
valid_sources[0x18]	35636	1			T8	10		T9	33		T10	1
valid_sources[0x19]	35546	1			T8	16		T9	76		T24	10
valid_sources[0x1a]	35690	1			T8	7		T9	9		T10	8
valid_sources[0x1b]	36671	1			T5	2		T8	9		T9	18
valid_sources[0x1c]	34407	1			T5	4		T8	5		T9	16
valid_sources[0x1d]	55433	1			T5	2		T8	8		T9	46
valid_sources[0x1e]	38593	1			T5	2		T8	7		T9	12
valid_sources[0x1f]	40351	1			T1	4		T8	7		T9	19
valid_sources[0x20]	36831	1			T5	2		T8	8		T9	19
valid_sources[0x21]	37221	1			T8	8		T9	41		T10	4
valid_sources[0x22]	37602	1			T5	1		T8	16		T9	7
valid_sources[0x23]	34785	1			T8	7		T9	22		T10	6
valid_sources[0x24]	35697	1			T5	2		T8	11		T9	52
valid_sources[0x25]	34686	1			T8	8		T9	17		T10	4
valid_sources[0x26]	33791	1			T5	3		T8	8		T9	18
valid_sources[0x27]	35373	1			T5	2		T8	10		T9	22
valid_sources[0x28]	36844	1			T8	12		T9	30		T10	9
valid_sources[0x29]	35214	1			T8	6		T9	74		T10	12
valid_sources[0x2a]	34922	1			T5	2		T8	12		T9	40
valid_sources[0x2b]	37673	1			T5	1		T7	365		T8	9
valid_sources[0x2c]	34885	1			T8	8		T9	18		T24	1
valid_sources[0x2d]	35267	1			T8	14		T9	16		T10	9
valid_sources[0x2e]	35461	1			T5	1		T8	7		T9	34
valid_sources[0x2f]	33237	1			T5	1		T8	7		T9	36
valid_sources[0x30]	38686	1			T8	5		T9	52		T10	8
valid_sources[0x31]	33864	1			T5	1		T8	11		T9	45
valid_sources[0x32]	34344	1			T5	1		T8	9		T9	54
valid_sources[0x33]	38473	1			T5	2		T8	6		T9	17
valid_sources[0x34]	34542	1			T8	12		T9	18		T10	1
valid_sources[0x35]	35972	1			T8	11		T9	51		T10	2
valid_sources[0x36]	33812	1			T8	6		T9	17		T10	11
valid_sources[0x37]	35977	1			T1	2		T8	12		T9	36
valid_sources[0x38]	35134	1			T8	8		T9	30		T10	5
valid_sources[0x39]	32810	1			T5	2		T8	11		T9	11
valid_sources[0x3a]	37419	1			T5	2		T8	7		T9	47
valid_sources[0x3b]	34623	1			T5	1		T8	5		T9	36
valid_sources[0x3c]	33938	1			T5	2		T8	7		T9	29
valid_sources[0x3d]	38740	1			T5	1		T8	8		T9	14
valid_sources[0x3e]	34282	1			T1	6		T8	12		T9	17
valid_sources[0x3f]	36651	1			T8	6		T9	36		T10	14
valid_sources[0x40]	36286	1			T5	3		T8	8		T9	52
valid_sources[0x41]	34385	1			T8	7		T9	27		T11	16
valid_sources[0x42]	38042	1			T8	13		T9	6		T10	8
valid_sources[0x43]	36719	1			T5	1		T8	3		T9	22
valid_sources[0x44]	40366	1			T5	1		T8	8		T9	1
valid_sources[0x45]	42950	1			T5	2		T8	7		T9	33
valid_sources[0x46]	36048	1			T8	9		T9	3		T10	1
valid_sources[0x47]	37004	1			T5	1		T8	17		T9	27
valid_sources[0x48]	36626	1			T8	9		T9	36		T10	3
valid_sources[0x49]	36286	1			T5	2		T8	9		T9	58
valid_sources[0x4a]	32577	1			T8	13		T9	11		T10	4
valid_sources[0x4b]	33621	1			T5	2		T8	11		T9	37
valid_sources[0x4c]	36827	1			T5	3		T8	13		T9	29
valid_sources[0x4d]	36825	1			T5	1		T8	11		T9	26
valid_sources[0x4e]	33612	1			T5	2		T8	16		T9	26
valid_sources[0x4f]	41275	1			T5	3		T8	11		T9	43
valid_sources[0x50]	33921	1			T8	12		T9	52		T10	2
valid_sources[0x51]	36264	1			T5	1		T8	3		T9	2
valid_sources[0x52]	35875	1			T5	3		T8	12		T9	20
valid_sources[0x53]	32884	1			T5	1		T8	11		T9	50
valid_sources[0x54]	35470	1			T5	1		T8	15		T9	26
valid_sources[0x55]	35075	1			T5	2		T8	9		T9	30
valid_sources[0x56]	36922	1			T5	2		T8	12		T9	68
valid_sources[0x57]	34243	1			T8	16		T9	8		T10	2
valid_sources[0x58]	33034	1			T5	4		T8	10		T9	17
valid_sources[0x59]	35553	1			T5	1		T8	16		T9	40
valid_sources[0x5a]	35612	1			T5	1		T8	4		T9	37
valid_sources[0x5b]	34151	1			T8	8		T9	46		T10	4
valid_sources[0x5c]	37246	1			T5	1		T8	6		T9	49
valid_sources[0x5d]	34853	1			T5	2		T8	8		T9	23
valid_sources[0x5e]	36550	1			T8	12		T9	26		T10	1
valid_sources[0x5f]	35962	1			T5	1		T8	9		T9	43
valid_sources[0x60]	36156	1			T5	1		T8	8		T9	34
valid_sources[0x61]	44355	1			T5	1		T8	6		T9	46
valid_sources[0x62]	45477	1			T5	2		T8	10		T9	27
valid_sources[0x63]	34045	1			T5	1		T8	12		T9	29
valid_sources[0x64]	34988	1			T5	4		T8	16		T9	33
valid_sources[0x65]	36116	1			T8	5		T9	22		T10	3
valid_sources[0x66]	40784	1			T8	16		T9	22		T10	6
valid_sources[0x67]	34525	1			T8	8		T9	46		T10	3
valid_sources[0x68]	35219	1			T5	2		T8	7		T9	29
valid_sources[0x69]	38028	1			T5	1		T8	9		T9	26
valid_sources[0x6a]	33857	1			T8	12		T9	12		T10	6
valid_sources[0x6b]	35246	1			T5	3		T8	10		T9	25
valid_sources[0x6c]	48784	1			T5	3		T8	10		T9	42
valid_sources[0x6d]	38269	1			T5	1		T8	8		T9	9
valid_sources[0x6e]	33377	1			T5	1		T8	4		T9	56
valid_sources[0x6f]	35211	1			T5	1		T8	7		T9	29
valid_sources[0x70]	34661	1			T8	7		T9	40		T10	8
valid_sources[0x71]	34556	1			T5	3		T8	5		T9	42
valid_sources[0x72]	37062	1			T5	1		T8	8		T9	27
valid_sources[0x73]	36495	1			T5	2		T8	10		T9	5
valid_sources[0x74]	36225	1			T5	1		T8	9		T9	29
valid_sources[0x75]	34438	1			T5	1		T8	22		T9	23
valid_sources[0x76]	32608	1			T5	2		T8	3		T9	20
valid_sources[0x77]	33934	1			T3	11		T5	2		T8	9
valid_sources[0x78]	35002	1			T5	1		T8	7		T9	69
valid_sources[0x79]	38006	1			T8	11		T9	34		T10	2
valid_sources[0x7a]	35373	1			T5	1		T8	9		T9	54
valid_sources[0x7b]	35367	1			T8	11		T9	51		T24	1
valid_sources[0x7c]	36186	1			T5	1		T8	9		T9	16
valid_sources[0x7d]	34504	1			T8	11		T9	14		T10	11
valid_sources[0x7e]	50910	1			T5	1		T8	7		T9	3
valid_sources[0x7f]	34976	1			T8	9		T9	43		T10	6
valid_sources[0x80]	44894	1			T1	3		T8	8		T9	30

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1115030

1

T1

1

T2

1

T5

11

values[0x0]

all_enables

biggest_size

1866351

1

T3

6

T4

7

T5

3

values[0x1]

all_enables

biggest_size

1837194

1

T3

2

T4

3

T5

3