Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

4517628

1

T1

42

T3

3

T4

4

full_word

4820132

1

T1

1

T2

1

T3

8

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	9337390	1			T1	43		T2	1		T3	11
auto[TlIntgErrCmd]	130	1			T104	3		T107	2		T108	6
auto[TlIntgErrData]	116	1			T104	4		T107	4		T108	9
auto[TlIntgErrBoth]	124	1			T104	3		T107	4		T108	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5196630

1

T1

43

T2

1

T3

2

auto[1]

4141130

1

T3

9

T4

13

T5

22

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	4081021	1			T1	42		T3	2		T4	1
auto[TlIntgErrNone]	partial	auto[1]	436268	1			T3	1		T4	3		T5	16
auto[TlIntgErrNone]	full_word	auto[0]	1115456	1			T1	1		T2	1		T5	11
auto[TlIntgErrNone]	full_word	auto[1]	3704645	1			T3	8		T4	10		T5	6
auto[TlIntgErrCmd]	partial	auto[0]	45	1			T104	1		T108	2		T122	6
auto[TlIntgErrCmd]	partial	auto[1]	77	1			T104	1		T107	1		T108	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T107	1		T195	1		T196	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T104	1		T197	1		T198	1
auto[TlIntgErrData]	partial	auto[0]	44	1			T104	1		T107	1		T108	5
auto[TlIntgErrData]	partial	auto[1]	58	1			T104	2		T107	3		T108	4
auto[TlIntgErrData]	full_word	auto[0]	9	1			T104	1		T122	1		T195	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T199	1		T195	1		T197	1
auto[TlIntgErrBoth]	partial	auto[0]	47	1			T104	1		T108	2		T122	2
auto[TlIntgErrBoth]	partial	auto[1]	68	1			T104	2		T107	4		T108	3
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T195	1		T200	1		T198	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T199	1		T197	2		T201	1