Unified Coverage Report :: Module :: spi_tpm

Module : spi_tpm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.79	99.29	91.20		91.67	96.77	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_tpm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm	95.79	99.29	91.20		91.67	96.77	100.00

---

Module Instance : tb.dut.u_spi_tpm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.79	99.29	91.20		91.67	96.77	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.87	99.28	85.25		91.67	95.68	92.45

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arbiter	87.79	100.00	76.47			92.86	81.82
u_cmdaddr_buffer	92.67	100.00	76.92			93.75	100.00
u_csb_sync_rst	100.00	100.00	100.00			100.00
u_hw_reg_slice	100.00	100.00					100.00
u_rdfifo_ready	100.00	100.00				100.00
u_sram_fifo	89.23	95.00	78.57			83.33	100.00
u_tpm_rd_buffer	89.74	100.00	69.23			100.00
u_tpm_wr_buffer	96.15	100.00	84.62			100.00	100.00
u_wrfifo_busy_sync	100.00	100.00				100.00
u_wrfifo_release_reqack	87.50	100.00	50.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : spi_tpm

	Line No.	Total	Covered	Percent
TOTAL		282	280	99.29
CONT_ASSIGN	335	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	374	1	1	100.00
CONT_ASSIGN	492	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	521	1	1	100.00
ALWAYS	525	8	8	100.00
ALWAYS	542	3	3	100.00
ALWAYS	555	4	4	100.00
CONT_ASSIGN	564	1	1	100.00
CONT_ASSIGN	566	1	1	100.00
CONT_ASSIGN	591	1	1	100.00
ALWAYS	594	3	3	100.00
ALWAYS	602	4	4	100.00
ALWAYS	610	3	3	100.00
ALWAYS	620	6	6	100.00
CONT_ASSIGN	637	1	1	100.00
CONT_ASSIGN	644	1	1	100.00
ALWAYS	648	4	4	100.00
CONT_ASSIGN	655	1	1	100.00
ALWAYS	658	4	4	100.00
CONT_ASSIGN	665	1	1	100.00
CONT_ASSIGN	667	1	1	100.00
CONT_ASSIGN	680	1	1	100.00
ALWAYS	683	6	6	100.00
CONT_ASSIGN	706	1	1	100.00
ALWAYS	709	6	6	100.00
ALWAYS	721	4	4	100.00
ALWAYS	743	3	3	100.00
ALWAYS	751	3	3	100.00
ALWAYS	763	6	6	100.00
ALWAYS	780	6	6	100.00
ALWAYS	796	3	3	100.00
ALWAYS	802	6	6	100.00
ALWAYS	813	4	4	100.00
ALWAYS	823	4	4	100.00
ALWAYS	832	4	4	100.00
CONT_ASSIGN	839	1	1	100.00
CONT_ASSIGN	840	1	1	100.00
ALWAYS	852	6	6	100.00
ALWAYS	863	6	6	100.00
ALWAYS	873	3	3	100.00
ALWAYS	893	7	7	100.00
ALWAYS	935	15	15	100.00
ALWAYS	1012	3	3	100.00
CONT_ASSIGN	1021	1	1	100.00
ALWAYS	1024	3	3	100.00
CONT_ASSIGN	1044	1	1	100.00
CONT_ASSIGN	1045	1	1	100.00
CONT_ASSIGN	1049	1	1	100.00
ALWAYS	1052	3	3	100.00
ALWAYS	1064	4	4	100.00
CONT_ASSIGN	1073	1	1	100.00
ALWAYS	1095	3	3	100.00
ALWAYS	1123	72	71	98.61
CONT_ASSIGN	1373	1	1	100.00
CONT_ASSIGN	1375	1	1	100.00
ALWAYS	1382	6	6	100.00
ALWAYS	1394	8	8	100.00
ALWAYS	1409	6	6	100.00
CONT_ASSIGN	1425	1	1	100.00
CONT_ASSIGN	1428	1	0	0.00
CONT_ASSIGN	1459	1	1	100.00
CONT_ASSIGN	1465	1	1	100.00
ALWAYS	1470	6	6	100.00
ALWAYS	1480	4	4	100.00
CONT_ASSIGN	1489	1	1	100.00
CONT_ASSIGN	1490	1	1	100.00
CONT_ASSIGN	1522	1	1	100.00
CONT_ASSIGN	1556	1	1	100.00

Click here to see the source line report.

---

Cond Coverage for Module : spi_tpm

	Total	Covered	Percent
Conditions	216	197	91.20
Logical	216	197	91.20
Non-Logical	0	0
Event	0	0

 LINE       564
 EXPRESSION ((cmdaddr_bitcnt == 5'b0) && (sck_st_q == StIdle))
             ------------1-----------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T7
1	0	Covered	T4,T5,T7
1	1	Covered	T1,T2,T3

 LINE       564
 SUB-EXPRESSION (cmdaddr_bitcnt == 5'b0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       564
 SUB-EXPRESSION (sck_st_q == StIdle)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       566
 EXPRESSION (cmdaddr_bitcnt == 5'h1d)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T7

 LINE       591
 EXPRESSION (cmdaddr_bitcnt == 5'h1f)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T7

 LINE       644
 EXPRESSION (isck_p2s_sent && (isck_data_sel == SelHwReg))
             ------1------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T26
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T7,T26

 LINE       644
 SUB-EXPRESSION (isck_data_sel == SelHwReg)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T26

 LINE       655
 EXPRESSION (wrdata_bitcnt == 3'h7)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T27,T29

 LINE       711
 EXPRESSION (sck_cmdaddr_wvalid && (cmd_type == Write))
             ---------1--------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T27,T29
1	1	Covered	T5,T27,T29

 LINE       711
 SUB-EXPRESSION (cmd_type == Write)
                ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T7
1	Covered	T4,T5,T6

 LINE       744
 EXPRESSION (check_locality && (sys_clk_tpm_cfg.tpm_reg_chk_dis || (addr[23:16] == TpmAddr)))
             -------1------    ------------------------------2------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T7
1	0	Covered	T29,T31,T44
1	1	Covered	T4,T5,T7

 LINE       744
 SUB-EXPRESSION (sys_clk_tpm_cfg.tpm_reg_chk_dis || (addr[23:16] == TpmAddr))
                 ---------------1---------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T7
1	0	Covered	T27,T29,T31

 LINE       744
 SUB-EXPRESSION (addr[23:16] == TpmAddr)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T7

 LINE       766
 EXPRESSION (((!sys_clk_tpm_cfg.tpm_mode)) && check_hw_reg && (cmd_type == Read) && is_tpm_reg_q && ((!invalid_locality)) && ((!sys_clk_tpm_cfg.hw_reg_dis)))
             --------------1--------------    ------2-----    ---------3--------    ------4-----    ----------5----------    ---------------6---------------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	1	1	1	1	1	Covered	T5,T27,T29
1	0	1	1	1	1	Covered	T4,T7,T26
1	1	0	1	1	1	Covered	T31,T43,T50
1	1	1	0	1	1	Covered	T31,T50,T51
1	1	1	1	0	1	Covered	T7,T28,T30
1	1	1	1	1	0	Covered	T31,T43,T50
1	1	1	1	1	1	Covered	T4,T7,T26

 LINE       766
 SUB-EXPRESSION (cmd_type == Read)
                ---------1--------

-1-	Status	Tests
0	Covered	T4,T5,T7
1	Covered	T4,T5,T7

 LINE       784
 EXPRESSION (TpmReturnByHwAddr[i][11:2] == addr[11:2])
            ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       805
 EXPRESSION (check_locality && is_tpm_reg_d)
             -------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T7
1	0	Covered	T29,T31,T44
1	1	Covered	T4,T5,T7

 LINE       807
 EXPRESSION ((addr[15:12] < 4'(spi_device_reg_pkg::NumLocality)) ? 1'b0 : 1'b1)
             -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T5,T7,T28
1	Covered	T4,T5,T7

 LINE       834
 EXPRESSION ((isck_p2s_sent && sck_rddata_shift_en) || (sck_wrfifo_wvalid && wrdata_shift_en))
             -------------------1------------------    -------------------2------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T7
0	1	Covered	T5,T27,T29
1	0	Covered	T5,T27,T29

 LINE       834
 SUB-EXPRESSION (isck_p2s_sent && sck_rddata_shift_en)
                 ------1------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T5,T27,T29
1	0	Covered	T4,T5,T7
1	1	Covered	T5,T27,T29

 LINE       834
 SUB-EXPRESSION (sck_wrfifo_wvalid && wrdata_shift_en)
                 --------1--------    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T5,T27,T29
1	0	Not Covered
1	1	Covered	T5,T27,T29

 LINE       840
 EXPRESSION (xfer_bytes_q == xfer_size)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       856
 EXPRESSION (sys_rdfifo_wvalid_i & sys_rdfifo_wready_o)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T5,T27,T29

 LINE       867
 EXPRESSION (sys_cmdaddr_rvalid_o & sys_cmdaddr_rready_i)
             ----------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T27,T29
1	1	Covered	T5,T27,T29

 LINE       940
 EXPRESSION (((!invalid_locality)) && (4'(i) == locality))
             ----------1----------    ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       940
 SUB-EXPRESSION (4'(i) == locality)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       965
 EXPRESSION (((!invalid_locality)) && sys_active_locality[locality[2:0]])
             ----------1----------    -----------------2----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T7,T26
1	1	Covered	T4,T7,T26

 LINE       1021
 EXPRESSION (isck_p2s_valid && (isck_p2s_bitcnt == '0))
             -------1------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T7
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

 LINE       1021
 SUB-EXPRESSION (isck_p2s_bitcnt == '0)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T7

 LINE       1049
 EXPRESSION (isck_p2s_sent && (isck_data_sel == SelRdFifo))
             ------1------    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T27,T29
1	0	Covered	T4,T5,T7
1	1	Covered	T5,T27,T29

 LINE       1049
 SUB-EXPRESSION (isck_data_sel == SelRdFifo)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T27,T29

 LINE       1073
 EXPRESSION (((&sck_rdfifo_idx)) && (isck_data_sel == SelRdFifo) && sck_p2s_valid && (isck_p2s_bitcnt == 3'b1))
             ---------1---------    --------------2-------------    ------3------    ------------4------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T5,T27,T29
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Covered	T5,T27,T29
1	1	1	1	Covered	T5,T27,T29

 LINE       1073
 SUB-EXPRESSION (isck_data_sel == SelRdFifo)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T27,T29

 LINE       1073
 SUB-EXPRESSION (isck_p2s_bitcnt == 3'b1)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T7

 LINE       1146
 EXPRESSION (cmdaddr_bitcnt == 5'h07)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T7

 LINE       1174
 EXPRESSION (cmdaddr_bitcnt == 5'h1b)
            ------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T7
1	Covered	T4,T5,T7

 LINE       1179
 EXPRESSION ((cmdaddr_bitcnt == 5'h1f) && (cmd_type == Read))
             ------------1------------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T7
1	0	Covered	T5,T27,T29
1	1	Covered	T4,T5,T7

 LINE       1179
 SUB-EXPRESSION (cmdaddr_bitcnt == 5'h1f)
                ------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T7
1	Covered	T4,T5,T7

 LINE       1179
 SUB-EXPRESSION (cmd_type == Read)
                ---------1--------

-1-	Status	Tests
0	Covered	T5,T27,T29
1	Covered	T4,T5,T7

 LINE       1180
 EXPRESSION (((!is_tpm_reg_q)) || sys_clk_tpm_cfg.tpm_mode)
             --------1--------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T7,T26
0	1	Covered	T5,T27,T29
1	0	Covered	T31,T43,T50

 LINE       1188
 EXPRESSION (sck_cmdaddr_wdepth == '0)
            -------------1------------

-1-	Status	Tests
0	Covered	T29,T31,T42
1	Covered	T5,T27,T29

 LINE       1195
 EXPRESSION (invalid_locality && sys_clk_tpm_cfg.invalid_locality)
             --------1-------    ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T43,T50
1	0	Covered	T31,T43,T50
1	1	Covered	T7,T28,T30

 LINE       1206
 EXPRESSION (sck_cmdaddr_wdepth == '0)
            -------------1------------

-1-	Status	Tests
0	Covered	T31,T43,T50
1	Covered	T31,T43,T50

 LINE       1212
 EXPRESSION ((cmdaddr_bitcnt == 5'h1f) && (cmd_type == Write))
             ------------1------------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T5,T27,T29
1	0	Covered	T4,T5,T7
1	1	Covered	T5,T27,T29

 LINE       1212
 SUB-EXPRESSION (cmdaddr_bitcnt == 5'h1f)
                ------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T7
1	Covered	T4,T5,T7

 LINE       1212
 SUB-EXPRESSION (cmd_type == Write)
                ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T7
1	Covered	T5,T27,T29

 LINE       1213
 EXPRESSION (((!sck_wrfifo_busy)) && ((~|sck_cmdaddr_wdepth)))
             ----------1---------    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T29,T42,T65
1	0	Covered	T42,T51,T64
1	1	Covered	T5,T27,T29

 LINE       1229
 EXPRESSION ((cmd_type == Read) && ((!sck_rdfifo_cmd_pending)) && ((~|sck_cmdaddr_wdepth)))
             ---------1--------    -------------2-------------    ------------3-----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T29,T31,T42
1	0	1	Covered	T5,T27,T29
1	1	0	Covered	T29,T31,T42
1	1	1	Covered	T29,T31,T42

 LINE       1229
 SUB-EXPRESSION (cmd_type == Read)
                ---------1--------

-1-	Status	Tests
0	Covered	T29,T31,T42
1	Covered	T5,T27,T29

 LINE       1234
 EXPRESSION (isck_p2s_sent && (((cmd_type == Read) && enough_payload_in_rdfifo) || ((cmd_type == Write) && ((!sck_wrfifo_busy)) && ((~|sck_cmdaddr_wdepth)))))
             ------1------    ---------------------------------------------------------------2---------------------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T27,T29
1	0	Covered	T5,T27,T29
1	1	Covered	T5,T27,T29

 LINE       1234
 SUB-EXPRESSION (((cmd_type == Read) && enough_payload_in_rdfifo) || ((cmd_type == Write) && ((!sck_wrfifo_busy)) && ((~|sck_cmdaddr_wdepth))))
                 ------------------------1-----------------------    ------------------------------------2------------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T27,T29
0	1	Covered	T29,T31,T42
1	0	Covered	T5,T27,T29

 LINE       1234
 SUB-EXPRESSION ((cmd_type == Read) && enough_payload_in_rdfifo)
                 ---------1--------    ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T27,T29
1	1	Covered	T5,T27,T29

 LINE       1234
 SUB-EXPRESSION (cmd_type == Read)
                ---------1--------

-1-	Status	Tests
0	Covered	T29,T31,T42
1	Covered	T5,T27,T29

 LINE       1234
 SUB-EXPRESSION ((cmd_type == Write) && ((!sck_wrfifo_busy)) && ((~|sck_cmdaddr_wdepth)))
                 ---------1---------    ----------2---------    ------------3-----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T27,T29
1	0	1	Covered	T29,T31,T42
1	1	0	Covered	T31,T42,T51
1	1	1	Covered	T29,T31,T42

 LINE       1234
 SUB-EXPRESSION (cmd_type == Write)
                ---------1---------

-1-	Status	Tests
0	Covered	T5,T27,T29
1	Covered	T29,T31,T42

 LINE       1247
 EXPRESSION ((cmd_type == Read) && is_hw_reg)
             ---------1--------    ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T27,T29
1	1	Covered	T4,T7,T26

 LINE       1247
 SUB-EXPRESSION (cmd_type == Read)
                ---------1--------

-1-	Status	Tests
0	Covered	T5,T27,T29
1	Covered	T4,T5,T7

 LINE       1249
 EXPRESSION (cmd_type == Read)
            ---------1--------

-1-	Status	Tests
0	Covered	T5,T27,T29
1	Covered	T5,T27,T29

 LINE       1251
 EXPRESSION (cmd_type == Write)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T5,T27,T29

 LINE       1263
 EXPRESSION (isck_p2s_sent && xfer_size_met)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T27,T29
1	0	Covered	T5,T27,T29
1	1	Covered	T5,T27,T29

 LINE       1274
 EXPRESSION (isck_p2s_sent && xfer_size_met)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T7,T28,T30
1	0	Covered	T4,T7,T26
1	1	Covered	T7,T28,T30

 LINE       1283
 EXPRESSION (sck_wrfifo_wvalid && xfer_size_met)
             --------1--------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T27,T29
1	0	Covered	T5,T27,T29
1	1	Covered	T5,T27,T29

 LINE       1292
 EXPRESSION (cmd_type == Read)
            ---------1--------

-1-	Status	Tests
0	Not Covered
1	Covered	T7,T28,T30

 LINE       1299
 EXPRESSION (cmd_type == Read)
            ---------1--------

-1-	Status	Tests
0	Covered	T5,T27,T29
1	Covered	T5,T7,T27

 LINE       1386
 EXPRESSION (sys_cmdaddr.rnw & sys_cmdaddr_rvalid_o & sys_cmdaddr_rready_i)
             -------1-------   ----------2---------   ----------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T27,T29
1	0	1	Not Covered
1	1	0	Covered	T5,T27,T29
1	1	1	Covered	T5,T27,T29

 LINE       1396
 EXPRESSION (cmdaddr_bitcnt == 5'h0f)
            ------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T7

 LINE       1401
 EXPRESSION (sck_cmdaddr_wvalid && (cmd_type == Read))
             ---------1--------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T7
1	0	Covered	T5,T27,T29
1	1	Covered	T5,T27,T29

 LINE       1401
 SUB-EXPRESSION (cmd_type == Read)
                ---------1--------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T7

 LINE       1403
 EXPRESSION (isck_p2s_sent && xfer_size_met && (sck_st_q == StReadFifo))
             ------1------    ------2------    ------------3-----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T27,T29
1	0	1	Covered	T5,T27,T29
1	1	0	Covered	T7,T28,T29
1	1	1	Covered	T5,T27,T29

 LINE       1403
 SUB-EXPRESSION (sck_st_q == StReadFifo)
                ------------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T27,T29

 LINE       1411
 EXPRESSION (sys_csb_deasserted_pulse & ((!sys_rdfifo_sync_clr)))
             ------------1-----------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T27,T29
1	0	Covered	T1,T4,T5
1	1	Covered	T5,T27,T29

 LINE       1418
 EXPRESSION (sys_cmdaddr_rvalid_o & sys_cmdaddr_rready_i)
             ----------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T27,T29
1	1	Covered	T5,T27,T29

 LINE       1425
 EXPRESSION (sys_csb_deasserted_pulse & ((!sys_rdfifo_sync_clr)))
             ------------1-----------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T27,T29
1	0	Covered	T1,T4,T5
1	1	Covered	T5,T27,T29

 LINE       1459
 EXPRESSION (sys_rdfifo_wvalid_i & ((!sys_rdfifo_wready_o)))
             ---------1---------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T27,T29
1	1	Not Covered

 LINE       1465
 EXPRESSION (enough_payload_in_rdfifo && ((sck_st_q == StReadFifo) || (sck_st_q == StStartByte)))
             ------------1-----------    ---------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T7
1	0	Covered	T5,T27,T29
1	1	Covered	T5,T27,T29

 LINE       1465
 SUB-EXPRESSION ((sck_st_q == StReadFifo) || (sck_st_q == StStartByte))
                 ------------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T7
1	0	Covered	T5,T27,T29

 LINE       1465
 SUB-EXPRESSION (sck_st_q == StReadFifo)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T27,T29

 LINE       1465
 SUB-EXPRESSION (sck_st_q == StStartByte)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T7

 LINE       1472
 EXPRESSION (sck_sram_req[SramRdFifo] & sck_sram_gnt[SramRdFifo])
             ------------1-----------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T5,T27,T29

 LINE       1482
 EXPRESSION (sck_sram_req[SramRdFifo] & sck_sram_gnt[SramRdFifo])
             ------------1-----------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T5,T27,T29

 LINE       1489
 EXPRESSION (rdfifo_active && ((!sck_rdfifo_req_pending)) && ((!sck_rdfifo_full)))
             ------1------    -------------2-------------    ----------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T27,T29
1	1	0	Covered	T5,T27,T29
1	1	1	Covered	T5,T27,T29

---

FSM Coverage for Module : spi_tpm

Summary for FSM :: sck_st_q

	Total	Covered	Percent
States	9	9	100.00	(Not included in score)
Transitions	12	11	91.67
Sequences	0	0

State, Transition and Sequence Details for FSM :: sck_st_q

---

states	Line No.	Covered	Tests
StAddr	1148	Covered	T4,T5,T7
StEnd	1158	Covered	T5,T7,T27
StIdle	1143	Covered	T1,T2,T3
StInvalid	1198	Covered	T7,T28,T30
StReadFifo	1250	Covered	T5,T27,T29
StReadHwReg	1248	Covered	T4,T7,T26
StStartByte	1194	Covered	T4,T5,T7
StWait	1183	Covered	T5,T27,T29
StWrite	1252	Covered	T5,T27,T29

transitions	Line No.	Covered	Tests
StAddr->StInvalid	1198	Covered	T7,T28,T30
StAddr->StStartByte	1194	Covered	T4,T5,T7
StAddr->StWait	1183	Covered	T5,T27,T29
StIdle->StAddr	1148	Covered	T4,T5,T7
StIdle->StEnd	1158	Not Covered
StReadFifo->StEnd	1264	Covered	T5,T27,T29
StReadHwReg->StEnd	1275	Covered	T7,T28,T30
StStartByte->StReadFifo	1250	Covered	T5,T27,T29
StStartByte->StReadHwReg	1248	Covered	T4,T7,T26
StStartByte->StWrite	1252	Covered	T5,T27,T29
StWait->StStartByte	1237	Covered	T5,T27,T29
StWrite->StEnd	1286	Covered	T5,T27,T29

---

Branch Coverage for Module : spi_tpm

	Line No.	Total	Covered	Percent
Branches		155	150	96.77
IF	525	3	3	100.00
IF	542	2	2	100.00
IF	555	3	3	100.00
IF	594	2	2	100.00
IF	602	3	3	100.00
IF	610	2	2	100.00
IF	620	4	4	100.00
IF	648	3	3	100.00
IF	658	3	3	100.00
IF	683	4	4	100.00
IF	709	4	4	100.00
CASE	722	3	3	100.00
IF	744	2	2	100.00
IF	751	2	2	100.00
IF	763	3	3	100.00
IF	784	2	2	100.00
IF	796	2	2	100.00
IF	802	4	4	100.00
IF	813	3	3	100.00
IF	823	3	3	100.00
IF	832	3	3	100.00
IF	852	4	4	100.00
IF	863	4	4	100.00
IF	873	2	2	100.00
CASE	895	6	5	83.33
CASE	937	11	11	100.00
IF	1012	2	2	100.00
IF	1024	2	2	100.00
IF	1052	2	2	100.00
IF	1064	3	3	100.00
IF	1095	2	2	100.00
CASE	1142	37	33	89.19
IF	1382	4	4	100.00
IF	1394	5	5	100.00
IF	1409	4	4	100.00
IF	1470	4	4	100.00
IF	1480	3	3	100.00

525            if (!sys_rst_ni) begin
               -1-  
526              sys_clk_tpm_cfg <= '{default: '0};
                 ==>
527              sys_clk_tpm_reg <= '{default: '0};
528            end else begin
529              if (sys_csb_asserted_pulse) begin
                 -2-  
530                sys_clk_tpm_cfg <= sys_tpm_cfg;
                   ==>
531                sys_clk_tpm_reg <= sys_tpm_reg;
532                for (int unsigned i = 0 ; i < NumLocality ; i++) begin
533                  sys_active_locality[i] <=
534                    sys_tpm_reg.access[AccessRegSize*i + ActiveLocalityBitPos];
535                end
536              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
0	0	Covered	T1,T2,T3

542            if (!rst_out_ni) begin
               -1-  
543              isck_data_sel <= SelWait;
                 ==>
544            end else begin
545              isck_data_sel <= sck_data_sel;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T7

555            if (!rst_ni) begin
               -1-  
556              cmdaddr_bitcnt <= 5'h 0;
                 ==>
557            end else if (cmdaddr_shift_en) begin
                        -2-              
558              cmdaddr_bitcnt <= cmdaddr_bitcnt + 5'h 1;
                 ==>
559            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T7
0	0	Covered	T4,T5,T7

594            if (!rst_out_ni) begin
               -1-  
595              isck_fifoaddr_latch <= 1'b 0;
                 ==>
596            end else begin
597              isck_fifoaddr_latch <= sck_fifoaddr_latch;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T7

602            if (!rst_ni) begin
               -1-  
603              sck_cmdaddr_wdata_q <= '0;
                 ==>
604            end else if (cmdaddr_shift_en) begin
                        -2-              
605              sck_cmdaddr_wdata_q <= sck_cmdaddr_wdata_d;
                 ==>
606            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T7
0	0	Covered	T4,T5,T7

610            if (cmdaddr_shift_en) begin
               -1-              
611              sck_cmdaddr_wdata_d = {sck_cmdaddr_wdata_q[0+:CmdAddrSize-1], mosi_i};
                 ==>
612            end else begin
613              sck_cmdaddr_wdata_d = sck_cmdaddr_wdata_q;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T7

620            if (!rst_out_ni) begin
               -1-  
621              isck_fifoaddr <= '0;
                 ==>
622            end else if (isck_fifoaddr_latch) begin
                        -2-          
623              // Shall assert when sck_st_q moves away from StAddr
624              isck_fifoaddr <= sck_cmdaddr_wdata_q[FifoRegSize-1:0];
                 ==>
625            end else if (isck_fifoaddr_inc) begin
                        -3-          
626              isck_fifoaddr <= isck_fifoaddr + 1'b 1;
                 ==>
627            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T5,T7
0	0	1	Covered	T4,T7,T26
0	0	0	Covered	T4,T5,T7

648            if (!rst_ni) begin
               -1-  
649              wrdata_bitcnt <= '0;
                 ==>
650            end else if (wrdata_shift_en) begin
                        -2-             
651              wrdata_bitcnt <= wrdata_bitcnt + 3'h 1;
                 ==>
652            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T5,T27,T29
0	0	Covered	T4,T5,T7

658            if (!rst_ni) begin
               -1-  
659              wrdata_q <= 8'h 0;
                 ==>
660            end else if (wrdata_shift_en) begin
                        -2-             
661              wrdata_q <= wrdata_d;
                 ==>
662            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T5,T27,T29
0	0	Covered	T4,T5,T7

683            if (!sys_rst_ni) begin
               -1-  
684              sys_wrfifo_release_req <= 1'b0;
                 ==>
685            end else if (sys_wrfifo_release_i) begin
                        -2-           
686              sys_wrfifo_release_req <= 1'b1;
                 ==>
687            end else if (sys_wrfifo_release_ack) begin
                        -3-           
688              sys_wrfifo_release_req <= 1'b0;
                 ==>
689            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T27,T29
0	0	1	Covered	T5,T27,T29
0	0	0	Covered	T1,T2,T3

709            if (!sys_rst_ni) begin
               -1-  
710              sck_wrfifo_busy <= 1'b0;
                 ==>
711            end else if (sck_cmdaddr_wvalid && cmd_type == Write) begin
                        -2-  
712              sck_wrfifo_busy <= 1'b1;
                 ==>
713            end else if (sck_wrfifo_release_req) begin
                        -3-           
714              sck_wrfifo_busy <= 1'b0;
                 ==>
715            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T27,T29
0	0	1	Covered	T5,T27,T29
0	0	0	Covered	T4,T5,T6

722            unique case (1'b 1)
                      -1-  
723              // locality in the TPM transaction is in addr[15:12].
724              // check_locality is asserted at the 24th beat.
725              // Look at the assertion LocalityLatchCondition_A
726              check_locality: begin
727                addr = {sck_cmdaddr_wdata_d[19:0], 4'h 0};
                   ==>
728              end
729        
730              check_hw_reg: begin
731                // In Return-by-HW Reg check stage, the lower 2 bits were not arrived.
732                // Look at the assertion HwRegCondition_A
733                addr = {sck_cmdaddr_wdata_d[21:0], 2'b 00};
                   ==>
734              end
735        
736              default: addr = 24'h 00_0000;
                 ==>

Branches:

-1-	Status	Tests
check_locality	Covered	T4,T5,T7
check_hw_reg	Covered	T4,T5,T7
default	Covered	T1,T2,T3

744            if (check_locality &&
               -1-  
745              (sys_clk_tpm_cfg.tpm_reg_chk_dis || (addr[23:16] == TpmAddr))) begin
746              is_tpm_reg_d = 1'b1;
                 ==>
747            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T7
0	Covered	T1,T2,T3

751            if (!rst_ni) begin
               -1-  
752              is_tpm_reg_q <= 1'b 0;
                 ==>
753            end else begin
754              is_tpm_reg_q <= is_tpm_reg_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T7

763            if (!rst_ni) begin
               -1-  
764              is_hw_reg      <= 1'b 0;
                 ==>
765              sck_hw_reg_idx <= RegAccess;
766            end else if (!sys_clk_tpm_cfg.tpm_mode && check_hw_reg && (cmd_type == Read)
                        -2-  
767              && is_tpm_reg_q && !invalid_locality && !sys_clk_tpm_cfg.hw_reg_dis) begin
768              // HW register is set only when the following conditions are met:
769              //
770              // 1. TPM is in FIFO mode
771              // 2. The command received is a Read command.
772              // 3. Is TPM register (starting with 0xD4_XXXX) or tpm_reg_chk_dis is set
773              // 4. Received locality is in the range of supported Locality.
774              is_hw_reg      <= is_hw_reg_d;
                 ==>
775              sck_hw_reg_idx <= sck_hw_reg_idx_d;
776            end // if check_hw_reg
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T7,T26
0	0	Covered	T4,T5,T7

784              if (TpmReturnByHwAddr[i][11:2] == addr[11:2]) begin
                 -1-  
785                is_hw_reg_d      = 1'b 1;
                   ==>
786                sck_hw_reg_idx_d = hw_reg_idx_e'(i);
787              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

796            if (!rst_out_ni) isck_hw_reg_idx <= RegAccess;
               -1-  
               ==>
797            else             isck_hw_reg_idx <= sck_hw_reg_idx;
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T7

802            if (!rst_ni) begin
               -1-  
803              locality         <= '0;
                 ==>
804              invalid_locality <= 1'b 0;
805            end else if (check_locality && is_tpm_reg_d) begin
                        -2-  
806              locality         <= addr[15:12];
807              invalid_locality <= (addr[15:12] < 4'(NumLocality)) ? 1'b 0: 1'b 1;
                                                                     -3-  
                                                                     ==>  
                                                                     ==>  
808            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	1	Covered	T4,T5,T7
0	1	0	Covered	T5,T7,T28
0	0	-	Covered	T4,T5,T7

813            if (!rst_ni) begin
               -1-  
814              cmd_type <= Write;
                 ==>
815            end else if (latch_cmd_type) begin
                        -2-  
816              // latch at the very first SCK edge
817              cmd_type <= cmd_type_e'(sck_cmdaddr_wdata_d[0]);
                 ==>
818            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T7
0	0	Covered	T4,T5,T7

823            if (!rst_ni) begin
               -1-  
824              xfer_size <= 6'h 0;
                 ==>
825            end else if (latch_xfer_size) begin
                        -2-  
826              xfer_size <= sck_cmdaddr_wdata_d[5:0];
                 ==>
827            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T7
0	0	Covered	T4,T5,T7

832            if (!rst_ni) begin
               -1-  
833              xfer_bytes_q <= '0;
                 ==>
834            end else if ((isck_p2s_sent && sck_rddata_shift_en) ||
                        -2-                                   
835              (sck_wrfifo_wvalid && wrdata_shift_en)) begin
836              xfer_bytes_q <= xfer_bytes_d;
                 ==>
837            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T5,T27,T29
0	0	Covered	T4,T5,T7

852            if (!sys_rst_ni) begin
               -1-  
853              sys_rdfifo_wdepth <= '0;
                 ==>
854            end else if (sys_csb_asserted_pulse) begin
                        -2-  
855              sys_rdfifo_wdepth <= '0;
                 ==>
856            end else if (sys_rdfifo_wvalid_i & sys_rdfifo_wready_o) begin
                        -3-                                 
857              sys_rdfifo_wdepth <= sys_rdfifo_wdepth + 1;
                 ==>
858            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T5,T27,T29
0	0	0	Covered	T1,T2,T3

863            if (!sys_rst_ni) begin
               -1-  
864              sys_xfer_size <= '1;
                 ==>
865            end else if (sys_csb_asserted_pulse) begin
                        -2-  
866              sys_xfer_size <= '1;
                 ==>
867            end else if (sys_cmdaddr_rvalid_o & sys_cmdaddr_rready_i) begin
                        -3-  
868              sys_xfer_size <= sys_cmdaddr.xfer_size_minus_one;
                 ==>
869            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T5,T27,T29
0	0	0	Covered	T1,T2,T3

873            if (!sys_rst_ni) begin
               -1-  
874              sys_enough_payload_in_rdfifo <= 1'b0;
                 ==>
875            end else begin
876              sys_enough_payload_in_rdfifo <=
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

895            unique case (isck_data_sel)
                      -1-  
896              SelWait: begin
897                isck_p2s_data = 8'h 00;
                   ==>
898              end
899        
900              SelStart: begin
901                isck_p2s_data = 8'h 01;
                   ==>
902              end
903        
904              SelInvalid: begin
905                isck_p2s_data = 8'h FF;
                   ==>
906              end
907        
908              SelHwReg: begin
909                isck_p2s_data = isck_hw_reg_byte;
                   ==>
910              end
911        
912              SelRdFifo: begin
913                isck_p2s_data = isck_sel_rdata;
                   ==>
914              end
915        
916              default: begin
917                isck_p2s_data = 8'h 00;
                   ==>

Branches:

-1-	Status	Tests
SelWait	Covered	T1,T2,T3
SelStart	Covered	T4,T5,T7
SelInvalid	Covered	T7,T28,T30
SelHwReg	Covered	T4,T7,T26
SelRdFifo	Covered	T5,T27,T29
default	Not Covered

937            unique case (isck_hw_reg_idx)
                      -1-  
938              RegAccess: begin
939                for (int unsigned i = 0 ; i < NumLocality ; i++) begin
                   ==>
940                  if (!invalid_locality && (4'(i) == locality)) begin
941                    isck_hw_reg_word = { {(32-AccessRegSize){1'b1}},
942                      sys_clk_tpm_reg.access[AccessRegSize*i+:AccessRegSize]};
943                  end
944                end
945              end
946        
947              RegIntEn: begin
948                isck_hw_reg_word = sys_clk_tpm_reg.int_enable;
                   ==>
949              end
950        
951              RegIntVect: begin
952                isck_hw_reg_word = {24'h FFFFFF, sys_clk_tpm_reg.int_vector};
                   ==>
953              end
954        
955              RegIntSts: begin
956                isck_hw_reg_word = sys_clk_tpm_reg.int_status;
                   ==>
957              end
958        
959              RegIntfCap: begin
960                isck_hw_reg_word = sys_clk_tpm_reg.intf_capacity;
                   ==>
961              end
962        
963              RegSts: begin
964                // Check locality to return FFh or correct value
965                if (!invalid_locality && sys_active_locality[locality[2:0]]) begin
                   -2-  
966                  // return data
967                  isck_hw_reg_word = sys_clk_tpm_reg.status;
                     ==>
968                end else begin
969                  isck_hw_reg_word = 32'h FFFF_FFFF;
                     ==>
970                end
971              end
972        
973              RegHashStart: begin
974                isck_hw_reg_word = 32'h FFFF_FFFF;
                   ==>
975              end
976        
977              RegId: begin
978                isck_hw_reg_word = sys_clk_tpm_reg.id;
                   ==>
979              end
980        
981              RegRid: begin
982                isck_hw_reg_word = {24'h FFFFFF, sys_clk_tpm_reg.rid};
                   ==>
983              end
984        
985              default: begin
986                isck_hw_reg_word = 32'h FFFF_FFFF;
                   ==>

Branches:

-1-	-2-	Status	Tests
RegAccess	-	Covered	T1,T2,T3
RegIntEn	-	Covered	T1,T2,T3
RegIntVect	-	Covered	T1,T2,T3
RegIntSts	-	Covered	T1,T2,T3
RegIntfCap	-	Covered	T1,T2,T3
RegSts	1	Covered	T1,T2,T3
RegSts	0	Covered	T1,T2,T3
RegHashStart	-	Covered	T1,T2,T3
RegId	-	Covered	T1,T2,T3
RegRid	-	Covered	T1,T2,T3
default	-	Covered	T1,T2,T3

1012           if (!rst_out_ni) begin
               -1-  
1013             isck_p2s_bitcnt <= 3'h 7;
                 ==>
1014           end else begin
1015             isck_p2s_bitcnt <= isck_p2s_bitcnt - 1'b 1;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T7

1024           if (!rst_out_ni) isck_p2s_valid <= 1'b 0;
               -1-  
               ==>
1025           else             isck_p2s_valid <= sck_p2s_valid;
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T7

1052           if (!rst_out_ni) begin
               -1-  
1053             isck_sel_rdata <= '0;
                 ==>
1054           end else begin
1055             isck_sel_rdata <= sck_rdfifo_rdata[NumBits*sck_rdfifo_idx+:NumBits];
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T7

1064           if (!rst_ni) begin
               -1-  
1065             sck_rdfifo_idx <= '0;
                 ==>
1066           end else if (isck_rd_byte_sent) begin
                        -2-  
1067             sck_rdfifo_idx <= sck_rdfifo_idx + 1'b 1;
                 ==>
1068           end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T5,T27,T29
0	0	Covered	T4,T5,T7

1095           if (!rst_ni) begin
               -1-  
1096             sck_st_q <= StIdle;
                 ==>
1097           end else begin
1098             sck_st_q <= sck_st_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T7

1142           unique case (sck_st_q)
                      -1-  
1143             StIdle: begin
1144               cmdaddr_shift_en = 1'b 1;
1145       
1146               if (cmdaddr_bitcnt == 5'h 7) begin
                   -2-  
1147                 if (sys_clk_tpm_en) begin
                     -3-  
1148                   sck_st_d = StAddr;
                       ==>
1149       
1150                   latch_xfer_size = 1'b 1;
1151                 end else begin
1152                   // Stop processing and move to End state.
1153                   // sys_clk_tpm_cfg.tpm_en cannot be compared right after reset.  Due
1154                   // to the absent of the SCK, the configuration cannot be
1155                   // synchronized into SCK domain at the first 3 clock cycle.
1156                   // So, the enable signal is checked when the state is about to
1157                   // move to StAddr.
1158                   sck_st_d = StEnd;
                       ==>
1159                 end
1160               end // cmdaddr_bitcnt == 5'h 7
                   MISSING_ELSE
                   ==>
1161             end // StIdle
1162       
1163             StAddr: begin
1164               // NOTE: The coding style in this state is ugly. How can we improve?
1165               cmdaddr_shift_en = 1'b 1;
1166       
1167               if (cmdaddr_bitcnt >= 5'h 18) begin
                   -4-  
1168                 // Send Wait byte [18h:1Fh]
1169                 sck_p2s_valid = 1'b 1;
                     ==>
1170                 sck_data_sel  = SelWait;
1171               end
                   MISSING_ELSE
                   ==>
1172       
1173               // Latch locality
1174               if (cmdaddr_bitcnt == 5'h 1B) begin
                   -5-  
1175                 check_locality = 1'b 1;
                     ==>
1176               end
                   MISSING_ELSE
                   ==>
1177       
1178               // Next state: if is_tpm_reg 1 && !cfg_hw_reg_dis
1179               if (cmdaddr_bitcnt == 5'h 1F && cmd_type == Read) begin
                   -6-  
1180                 if (!is_tpm_reg_q || sys_clk_tpm_cfg.tpm_mode) begin
                     -7-  
1181                   // If out of TPM register (not staring with 0xD4_XXXX) or
1182                   // TPM mode is CRB, always processed by SW
1183                   sck_st_d = StWait;
1184       
1185                   // Only write the command if the FIFO is empty, else back-to-back
1186                   // commands may cause ambiguity about which command is getting
1187                   // a response.
1188                   if (sck_cmdaddr_wdepth == '0) begin
                       -8-  
1189                     sck_cmdaddr_wvalid = 1'b 1;
                         ==>
1190                   end
                       MISSING_ELSE
                       ==>
1191                 end else if (is_hw_reg) begin
                              -9-  
1192                   // If read command and HW REG, then return by HW
1193                   // is_hw_reg contains (is_tpm_reg_q && (locality < NumLocality))
1194                   sck_st_d = StStartByte;
                       ==>
1195                 end else if (invalid_locality && sys_clk_tpm_cfg.invalid_locality) begin
                              -10-  
1196                   // The read request is out of supported Localities.
1197                   // Return FFh
1198                   sck_st_d = StInvalid;
                       ==>
1199                 end else begin
1200                   // Other read command sends to Wait, till SW response
1201                   sck_st_d = StWait;
1202       
1203                   // Only write the command if the FIFO is empty, else back-to-back
1204                   // commands may cause ambiguity about which command is getting
1205                   // a response.
1206                   if (sck_cmdaddr_wdepth == '0) begin
                       -11-  
1207                     sck_cmdaddr_wvalid = 1'b 1;
                         ==>
1208                   end
                       MISSING_ELSE
                       ==>
1209                 end
1210               end // cmdaddr_bitcnt == 5'h 1F
                   MISSING_ELSE
                   ==>
1211       
1212               if (cmdaddr_bitcnt == 5'h 1F && cmd_type == Write) begin
                   -12-  
1213                 if (!sck_wrfifo_busy && ~|sck_cmdaddr_wdepth) begin
                     -13-            
1214                   // Write command and FIFO is empty. Ready to push
1215                   sck_st_d = StStartByte;
                       ==>
1216                 end else begin
1217                   // FIFO is not empty. Move to StWait and waits for the empty write
1218                   // fifo.
1219                   sck_st_d = StWait;
                       ==>
1220                 end
1221               end // cmd_type == Write
                   MISSING_ELSE
                   ==>
1222             end // StAddr
1223       
1224             StWait: begin
1225               sck_p2s_valid = 1'b 1;
1226               sck_data_sel = SelWait;
1227       
1228               // Write the Read command if it hasn't been yet.
1229               if ((cmd_type == Read) && !sck_rdfifo_cmd_pending && ~|sck_cmdaddr_wdepth) begin
                   -14-                                  
1230                 sck_cmdaddr_wvalid = 1'b1;
                     ==>
1231               end
                   MISSING_ELSE
                   ==>
1232       
1233               // at every LSB of a byte, check the next state condition
1234               if (isck_p2s_sent &&
                   -15-  
1235                 (((cmd_type == Read) && enough_payload_in_rdfifo) ||
1236                 ((cmd_type == Write) && !sck_wrfifo_busy && ~|sck_cmdaddr_wdepth))) begin
1237                 sck_st_d = StStartByte;
                     ==>
1238               end
                   MISSING_ELSE
                   ==>
1239             end // StWait
1240       
1241             StStartByte: begin
1242               sck_p2s_valid = 1'b 1;
1243               sck_data_sel  = SelStart;
1244       
1245               if (isck_p2s_sent) begin
                   -16-  
1246                 // Must move to next state as StartByte is a byte
1247                 if ((cmd_type == Read) && is_hw_reg) begin
                     -17-  
1248                   sck_st_d = StReadHwReg;
                       ==>
1249                 end else if (cmd_type == Read) begin
                              -18-  
1250                   sck_st_d = StReadFifo;
                       ==>
1251                 end else if (cmd_type == Write) begin
                              -19-  
1252                   sck_st_d = StWrite;
                       ==>
1253                 end
                     MISSING_ELSE
                     ==>
1254               end
                   MISSING_ELSE
                   ==>
1255             end // StStartByte
1256       
1257             StReadFifo: begin
1258               sck_rddata_shift_en = 1'b 1;
1259       
1260               sck_p2s_valid = 1'b 1;
1261               sck_data_sel  = SelRdFifo;
1262       
1263               if (isck_p2s_sent && xfer_size_met) begin
                   -20-  
1264                 sck_st_d = StEnd;
                     ==>
1265               end
                   MISSING_ELSE
                   ==>
1266             end // StReadFifo
1267       
1268             StReadHwReg: begin
1269               sck_p2s_valid = 1'b 1;
1270               sck_data_sel  = SelHwReg;
1271       
1272               // HW Reg slice? using index
1273       
1274               if (isck_p2s_sent && xfer_size_met) begin
                   -21-  
1275                 sck_st_d = StEnd;
                     ==>
1276               end
                   MISSING_ELSE
                   ==>
1277             end // StReadHwReg
1278       
1279             StWrite: begin
1280               wrdata_shift_en = 1'b 1;
1281               // Processed by the logic. Does not have to do
1282       
1283               if (sck_wrfifo_wvalid && xfer_size_met) begin
                   -22-           
1284                 // With complete command, upload for SW to process
1285                 sck_cmdaddr_wvalid = 1'b 1;
                     ==>
1286                 sck_st_d = StEnd;
1287               end
                   MISSING_ELSE
                   ==>
1288             end // StWrite
1289       
1290             StInvalid: begin // TERMINAL_STATE
1291               // Send FFh
1292               if (cmd_type == Read) begin
                   -23-  
1293                 sck_p2s_valid = 1'b 1;
                     ==>
1294                 sck_data_sel  = SelInvalid;
1295               end
                   MISSING_ELSE
                   ==>
1296             end // StInvalid
1297       
1298             StEnd: begin // TERMINAL_STATE
1299               if (cmd_type == Read) begin
                   -24-  
1300                 sck_p2s_valid = 1'b 1;
                     ==>
1301                 sck_data_sel  = SelWait; // drive 0x00
1302               end
                   MISSING_ELSE
                   ==>
1303             end // StEnd
1304       
1305             default: begin
1306               sck_st_d = StIdle;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	Status	Tests
StIdle	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T7
StIdle	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StIdle	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StAddr	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T7
StAddr	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T7
StAddr	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T7
StAddr	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T7
StAddr	-	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T27,T29
StAddr	-	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T29,T31,T42
StAddr	-	-	-	-	1	0	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T26
StAddr	-	-	-	-	1	0	-	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T28,T30
StAddr	-	-	-	-	1	0	-	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T31,T43,T50
StAddr	-	-	-	-	1	0	-	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T31,T43,T50
StAddr	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T7
StAddr	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T27,T29
StAddr	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T29,T31,T42
StAddr	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T7
StWait	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T29,T31,T42
StWait	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T5,T27,T29
StWait	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T5,T27,T29
StWait	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T5,T27,T29
StStartByte	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	Covered	T4,T7,T26
StStartByte	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	1	-	-	-	-	-	-	Covered	T5,T27,T29
StStartByte	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	0	1	-	-	-	-	-	Covered	T5,T27,T29
StStartByte	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	0	0	-	-	-	-	-	Not Covered
StStartByte	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T4,T5,T7
StReadFifo	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T5,T27,T29
StReadFifo	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T5,T27,T29
StReadHwReg	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T7,T28,T30
StReadHwReg	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	Covered	T4,T7,T26
StWrite	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T5,T27,T29
StWrite	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T5,T27,T29
StInvalid	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T7,T28,T30
StInvalid	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Not Covered
StEnd	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T5,T7,T27
StEnd	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T5,T27,T29
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

1382           if (!sys_rst_ni) begin
               -1-  
1383             sys_rdfifo_sync_clr <= 1'b1;
                 ==>
1384           end else if (sys_csb_deasserted_pulse) begin
                        -2-  
1385             sys_rdfifo_sync_clr <= 1'b1;
                 ==>
1386           end else if (sys_cmdaddr.rnw & sys_cmdaddr_rvalid_o & sys_cmdaddr_rready_i) begin
                        -3-  
1387             sys_rdfifo_sync_clr <= 1'b0;
                 ==>
1388           end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T4,T5
0	0	1	Covered	T5,T27,T29
0	0	0	Covered	T1,T2,T3

1394           if (!sys_rst_ni) begin
               -1-  
1395             sck_rdfifo_cmd_pending <= 1'b0;
                 ==>
1396           end else if (cmdaddr_bitcnt == 5'h0f) begin
                        -2-  
1397             // Clearing the command pending bit here should give at least the 16 SPI
1398             // cycles for the sys_clk domain to sample the event, timed by
1399             // sys_tpm_rst_ni falling edge (after a 2FF sync).
1400             sck_rdfifo_cmd_pending <= 1'b0;
                 ==>
1401           end else if (sck_cmdaddr_wvalid && (cmd_type == Read)) begin
                        -3-  
1402             sck_rdfifo_cmd_pending <= 1'b1;
                 ==>
1403           end else if (isck_p2s_sent && xfer_size_met && (sck_st_q == StReadFifo)) begin
                        -4-                                                          
1404             sck_rdfifo_cmd_pending <= 1'b0;
                 ==>
1405           end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T4,T5,T7
0	0	1	-	Covered	T5,T27,T29
0	0	0	1	Covered	T5,T27,T29
0	0	0	0	Covered	T4,T5,T6

1409           if (!sys_rst_ni) begin
               -1-  
1410             sys_rdfifo_aborted_o <= 1'b0;
                 ==>
1411           end else if (sys_csb_deasserted_pulse & !sys_rdfifo_sync_clr) begin
                        -2-                                       
1412             // Sample the command pending bit on the CSB de-assertion edge, which
1413             // has a safe timing as long as sys_clk_i is fast enough to handle the
1414             // CSB CDC + this flop in the 16 SPI cycles. sck_rdfifo_cmd_pending will
1415             // be held steady for at least that long, including however long since the
1416             // last SPI clock edge of the *previous* command.
1417             sys_rdfifo_aborted_o <= sck_rdfifo_cmd_pending;
                 ==>
1418           end else if (sys_cmdaddr_rvalid_o & sys_cmdaddr_rready_i) begin
                        -3-  
1419             sys_rdfifo_aborted_o <= 1'b0;
                 ==>
1420           end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T27,T29
0	0	1	Covered	T5,T27,T29
0	0	0	Covered	T1,T2,T3

1470           if (!rst_ni) begin
               -1-  
1471             sck_rdfifo_req_pending <= 1'b0;
                 ==>
1472           end else if (sck_sram_req[SramRdFifo] & sck_sram_gnt[SramRdFifo]) begin
                        -2-                                                   
1473             sck_rdfifo_req_pending <= 1'b1;
                 ==>
1474           end else if (sck_sram_rvalid[SramRdFifo]) begin
                        -3-                           
1475             sck_rdfifo_req_pending <= 1'b0;
                 ==>
1476           end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T27,T29
0	0	1	Covered	T5,T27,T29
0	0	0	Covered	T4,T5,T7

1480           if (!rst_ni) begin
               -1-  
1481             sck_rdfifo_offset <= '0;
                 ==>
1482           end else if (sck_sram_req[SramRdFifo] & sck_sram_gnt[SramRdFifo]) begin
                        -2-                                                   
1483             sck_rdfifo_offset <= sck_rdfifo_offset + 1;
                 ==>
1484           end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T5,T27,T29
0	0	Covered	T4,T5,T7

---

Assert Coverage for Module : spi_tpm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CmdAddrAvailable_A	157354583	54752	0	0
CmdAddrBitCntInAddrSt_A	157354583	569032	0	0
CmdAddrInfo_A	157354583	56162	0	0
CmdPowerof2_A	954	954	0	0
DataFifoLessThan64_A	954	954	0	0
DataSelKnown_A	157355524	26921896	0	0
HwRegCondition2_a	157354583	9885	0	0
HwRegCondition_A	157354583	71129	0	0
HwRegIdxKnown_A	157355524	26921896	0	0
LocalityLatchCondition_A	157354583	71129	0	0
RdFifoDepthPoT_A	954	954	0	0
RdFifoNumBytesPoT_A	954	954	0	0
RdPowerof2_A	954	954	0	0
SckFifoAddrLatchCondition_A	157354583	71129	0	0
TpmRegSizeMatch_A	954	954	0	0
WrDepthSpec_A	954	954	0	0
WrFifoAvailable_A	157354583	471548	0	0

CmdAddrAvailable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157354583	54752	0	0
T5	961	8	0	0
T6	28992	0	0	0
T7	30692	0	0	0
T8	52748	0	0	0
T9	22464	0	0	0
T10	57680	0	0	0
T11	12656	0	0	0
T12	148174	0	0	0
T13	105604	0	0	0
T16	149029	0	0	0
T27	0	4	0	0
T29	0	304	0	0
T31	0	403	0	0
T42	0	328	0	0
T43	0	191	0	0
T44	0	13	0	0
T46	0	475	0	0
T65	0	215	0	0
T66	0	9	0	0

CmdAddrBitCntInAddrSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157354583	569032	0	0
T4	288	32	0	0
T5	961	64	0	0
T6	28992	0	0	0
T7	30692	1056	0	0
T8	52748	0	0	0
T9	22464	0	0	0
T10	57680	0	0	0
T11	12656	0	0	0
T12	148174	0	0	0
T13	105604	0	0	0
T26	0	72	0	0
T27	0	32	0	0
T28	0	2384	0	0
T29	0	2432	0	0
T30	0	456	0	0
T31	0	3992	0	0
T32	0	40	0	0

CmdAddrInfo_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157354583	56162	0	0
T4	288	4	0	0
T5	961	8	0	0
T6	28992	0	0	0
T7	30692	132	0	0
T8	52748	0	0	0
T9	22464	0	0	0
T10	57680	0	0	0
T11	12656	0	0	0
T12	148174	0	0	0
T13	105604	0	0	0
T26	0	9	0	0
T27	0	4	0	0
T28	0	298	0	0
T29	0	238	0	0
T30	0	57	0	0
T31	0	415	0	0
T32	0	5	0	0

CmdPowerof2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

DataFifoLessThan64_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

DataSelKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157355524	26921896	0	0
T4	289	288	0	0
T5	962	736	0	0
T6	28993	0	0	0
T7	30693	28168	0	0
T8	52749	0	0	0
T9	22465	0	0	0
T10	57681	0	0	0
T11	12657	0	0	0
T12	148175	0	0	0
T24	1	0	0	0
T26	0	648	0	0
T27	0	1360	0	0
T28	0	77840	0	0
T29	0	91776	0	0
T30	0	9160	0	0
T31	0	130920	0	0
T32	0	360	0	0

HwRegCondition2_a

Name	Attempts	Real Successes	Failures	Incomplete
Total	157354583	9885	0	0
T4	288	4	0	0
T5	961	0	0	0
T6	28992	0	0	0
T7	30692	91	0	0
T8	52748	0	0	0
T9	22464	0	0	0
T10	57680	0	0	0
T11	12656	0	0	0
T12	148174	0	0	0
T13	105604	0	0	0
T26	0	9	0	0
T28	0	200	0	0
T30	0	39	0	0
T31	0	37	0	0
T32	0	5	0	0
T92	0	14	0	0
T93	0	55	0	0
T94	0	6	0	0

HwRegCondition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157354583	71129	0	0
T4	288	4	0	0
T5	961	8	0	0
T6	28992	0	0	0
T7	30692	132	0	0
T8	52748	0	0	0
T9	22464	0	0	0
T10	57680	0	0	0
T11	12656	0	0	0
T12	148174	0	0	0
T13	105604	0	0	0
T26	0	9	0	0
T27	0	4	0	0
T28	0	298	0	0
T29	0	304	0	0
T30	0	57	0	0
T31	0	499	0	0
T32	0	5	0	0

HwRegIdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157355524	26921896	0	0
T4	289	288	0	0
T5	962	736	0	0
T6	28993	0	0	0
T7	30693	28168	0	0
T8	52749	0	0	0
T9	22465	0	0	0
T10	57681	0	0	0
T11	12657	0	0	0
T12	148175	0	0	0
T24	1	0	0	0
T26	0	648	0	0
T27	0	1360	0	0
T28	0	77840	0	0
T29	0	91776	0	0
T30	0	9160	0	0
T31	0	130920	0	0
T32	0	360	0	0

LocalityLatchCondition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157354583	71129	0	0
T4	288	4	0	0
T5	961	8	0	0
T6	28992	0	0	0
T7	30692	132	0	0
T8	52748	0	0	0
T9	22464	0	0	0
T10	57680	0	0	0
T11	12656	0	0	0
T12	148174	0	0	0
T13	105604	0	0	0
T26	0	9	0	0
T27	0	4	0	0
T28	0	298	0	0
T29	0	304	0	0
T30	0	57	0	0
T31	0	499	0	0
T32	0	5	0	0

RdFifoDepthPoT_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

RdFifoNumBytesPoT_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

RdPowerof2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

SckFifoAddrLatchCondition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157354583	71129	0	0
T4	288	4	0	0
T5	961	8	0	0
T6	28992	0	0	0
T7	30692	132	0	0
T8	52748	0	0	0
T9	22464	0	0	0
T10	57680	0	0	0
T11	12656	0	0	0
T12	148174	0	0	0
T13	105604	0	0	0
T26	0	9	0	0
T27	0	4	0	0
T28	0	298	0	0
T29	0	304	0	0
T30	0	57	0	0
T31	0	499	0	0
T32	0	5	0	0

TpmRegSizeMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

WrDepthSpec_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

WrFifoAvailable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157354583	471548	0	0
T5	961	30	0	0
T6	28992	0	0	0
T7	30692	0	0	0
T8	52748	0	0	0
T9	22464	0	0	0
T10	57680	0	0	0
T11	12656	0	0	0
T12	148174	0	0	0
T13	105604	0	0	0
T16	149029	0	0	0
T27	0	68	0	0
T29	0	2265	0	0
T31	0	4240	0	0
T42	0	2433	0	0
T43	0	1784	0	0
T44	0	76	0	0
T46	0	4140	0	0
T65	0	2016	0	0
T66	0	194	0	0