Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	533886812	3116845	0	0
DataKnown_AKnownEnable	533886812	533756750	0	0
DepthKnown_A	533886812	533756750	0	0
RvalidKnown_A	533886812	533756750	0	0
WreadyKnown_A	533886812	533756750	0	0
gen_passthru_fifo.paramCheckPass	1129	1129	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533886812	3116845	0	0
T6	10597	1664	0	0
T7	225723	0	0	0
T8	60532	1663	0	0
T9	160440	1663	0	0
T10	36643	1663	0	0
T11	42990	832	0	0
T12	892576	1663	0	0
T13	109862	3213	0	0
T14	8128	0	0	0
T16	0	1664	0	0
T17	0	1663	0	0
T24	3043	1663	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	533886812	533756750	0	0
T1	1424	1345	0	0
T2	1778	1696	0	0
T3	2044	1977	0	0
T4	1668	1579	0	0
T5	5732	5639	0	0
T6	10597	10538	0	0
T7	225723	225667	0	0
T8	60532	60438	0	0
T9	160440	160342	0	0
T10	36643	36578	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533886812	533756750	0	0
T1	1424	1345	0	0
T2	1778	1696	0	0
T3	2044	1977	0	0
T4	1668	1579	0	0
T5	5732	5639	0	0
T6	10597	10538	0	0
T7	225723	225667	0	0
T8	60532	60438	0	0
T9	160440	160342	0	0
T10	36643	36578	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533886812	533756750	0	0
T1	1424	1345	0	0
T2	1778	1696	0	0
T3	2044	1977	0	0
T4	1668	1579	0	0
T5	5732	5639	0	0
T6	10597	10538	0	0
T7	225723	225667	0	0
T8	60532	60438	0	0
T9	160440	160342	0	0
T10	36643	36578	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533886812	533756750	0	0
T1	1424	1345	0	0
T2	1778	1696	0	0
T3	2044	1977	0	0
T4	1668	1579	0	0
T5	5732	5639	0	0
T6	10597	10538	0	0
T7	225723	225667	0	0
T8	60532	60438	0	0
T9	160440	160342	0	0
T10	36643	36578	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1129	1129	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	533886812	3400734	0	0
DataKnown_AKnownEnable	533886812	533756750	0	0
DepthKnown_A	533886812	533756750	0	0
RvalidKnown_A	533886812	533756750	0	0
WreadyKnown_A	533886812	533756750	0	0
gen_passthru_fifo.paramCheckPass	1129	1129	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533886812	3400734	0	0
T6	10597	833	0	0
T7	225723	0	0	0
T8	60532	832	0	0
T9	160440	832	0	0
T10	36643	832	0	0
T11	42990	832	0	0
T12	892576	832	0	0
T13	109862	1617	0	0
T14	8128	0	0	0
T16	0	5430	0	0
T17	0	832	0	0
T24	3043	832	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	533886812	533756750	0	0
T1	1424	1345	0	0
T2	1778	1696	0	0
T3	2044	1977	0	0
T4	1668	1579	0	0
T5	5732	5639	0	0
T6	10597	10538	0	0
T7	225723	225667	0	0
T8	60532	60438	0	0
T9	160440	160342	0	0
T10	36643	36578	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533886812	533756750	0	0
T1	1424	1345	0	0
T2	1778	1696	0	0
T3	2044	1977	0	0
T4	1668	1579	0	0
T5	5732	5639	0	0
T6	10597	10538	0	0
T7	225723	225667	0	0
T8	60532	60438	0	0
T9	160440	160342	0	0
T10	36643	36578	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533886812	533756750	0	0
T1	1424	1345	0	0
T2	1778	1696	0	0
T3	2044	1977	0	0
T4	1668	1579	0	0
T5	5732	5639	0	0
T6	10597	10538	0	0
T7	225723	225667	0	0
T8	60532	60438	0	0
T9	160440	160342	0	0
T10	36643	36578	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533886812	533756750	0	0
T1	1424	1345	0	0
T2	1778	1696	0	0
T3	2044	1977	0	0
T4	1668	1579	0	0
T5	5732	5639	0	0
T6	10597	10538	0	0
T7	225723	225667	0	0
T8	60532	60438	0	0
T9	160440	160342	0	0
T10	36643	36578	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1129	1129	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	533886812	210619	0	0
DataKnown_AKnownEnable	533886812	533756750	0	0
DepthKnown_A	533886812	533756750	0	0
RvalidKnown_A	533886812	533756750	0	0
WreadyKnown_A	533886812	533756750	0	0
gen_passthru_fifo.paramCheckPass	1129	1129	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533886812	210619	0	0
T5	5732	8	0	0
T6	10597	0	0	0
T7	225723	0	0	0
T8	60532	0	0	0
T9	160440	0	0	0
T10	36643	128	0	0
T11	42990	0	0	0
T12	892576	0	0	0
T13	109862	0	0	0
T24	3043	0	0	0
T27	0	17	0	0
T29	0	593	0	0
T31	0	1094	0	0
T41	0	384	0	0
T42	0	623	0	0
T44	0	20	0	0
T45	0	160	0	0
T46	0	1072	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	533886812	533756750	0	0
T1	1424	1345	0	0
T2	1778	1696	0	0
T3	2044	1977	0	0
T4	1668	1579	0	0
T5	5732	5639	0	0
T6	10597	10538	0	0
T7	225723	225667	0	0
T8	60532	60438	0	0
T9	160440	160342	0	0
T10	36643	36578	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533886812	533756750	0	0
T1	1424	1345	0	0
T2	1778	1696	0	0
T3	2044	1977	0	0
T4	1668	1579	0	0
T5	5732	5639	0	0
T6	10597	10538	0	0
T7	225723	225667	0	0
T8	60532	60438	0	0
T9	160440	160342	0	0
T10	36643	36578	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533886812	533756750	0	0
T1	1424	1345	0	0
T2	1778	1696	0	0
T3	2044	1977	0	0
T4	1668	1579	0	0
T5	5732	5639	0	0
T6	10597	10538	0	0
T7	225723	225667	0	0
T8	60532	60438	0	0
T9	160440	160342	0	0
T10	36643	36578	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533886812	533756750	0	0
T1	1424	1345	0	0
T2	1778	1696	0	0
T3	2044	1977	0	0
T4	1668	1579	0	0
T5	5732	5639	0	0
T6	10597	10538	0	0
T7	225723	225667	0	0
T8	60532	60438	0	0
T9	160440	160342	0	0
T10	36643	36578	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1129	1129	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	533886812	492657	0	0
DataKnown_AKnownEnable	533886812	533756750	0	0
DepthKnown_A	533886812	533756750	0	0
RvalidKnown_A	533886812	533756750	0	0
WreadyKnown_A	533886812	533756750	0	0
gen_passthru_fifo.paramCheckPass	1129	1129	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533886812	492657	0	0
T5	5732	8	0	0
T6	10597	0	0	0
T7	225723	0	0	0
T8	60532	0	0	0
T9	160440	0	0	0
T10	36643	128	0	0
T11	42990	0	0	0
T12	892576	0	0	0
T13	109862	0	0	0
T24	3043	0	0	0
T27	0	17	0	0
T29	0	593	0	0
T31	0	1094	0	0
T41	0	1218	0	0
T42	0	2808	0	0
T44	0	20	0	0
T45	0	160	0	0
T46	0	1072	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	533886812	533756750	0	0
T1	1424	1345	0	0
T2	1778	1696	0	0
T3	2044	1977	0	0
T4	1668	1579	0	0
T5	5732	5639	0	0
T6	10597	10538	0	0
T7	225723	225667	0	0
T8	60532	60438	0	0
T9	160440	160342	0	0
T10	36643	36578	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533886812	533756750	0	0
T1	1424	1345	0	0
T2	1778	1696	0	0
T3	2044	1977	0	0
T4	1668	1579	0	0
T5	5732	5639	0	0
T6	10597	10538	0	0
T7	225723	225667	0	0
T8	60532	60438	0	0
T9	160440	160342	0	0
T10	36643	36578	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533886812	533756750	0	0
T1	1424	1345	0	0
T2	1778	1696	0	0
T3	2044	1977	0	0
T4	1668	1579	0	0
T5	5732	5639	0	0
T6	10597	10538	0	0
T7	225723	225667	0	0
T8	60532	60438	0	0
T9	160440	160342	0	0
T10	36643	36578	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533886812	533756750	0	0
T1	1424	1345	0	0
T2	1778	1696	0	0
T3	2044	1977	0	0
T4	1668	1579	0	0
T5	5732	5639	0	0
T6	10597	10538	0	0
T7	225723	225667	0	0
T8	60532	60438	0	0
T9	160440	160342	0	0
T10	36643	36578	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1129	1129	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	533886812	7564164	0	0
DataKnown_AKnownEnable	533886812	533756750	0	0
DepthKnown_A	533886812	533756750	0	0
RvalidKnown_A	533886812	533756750	0	0
WreadyKnown_A	533886812	533756750	0	0
gen_passthru_fifo.paramCheckPass	1129	1129	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533886812	7564164	0	0
T1	1424	43	0	0
T2	1778	1	0	0
T3	2044	11	0	0
T4	1668	14	0	0
T5	5732	266	0	0
T6	10597	50	0	0
T7	225723	365	0	0
T8	60532	1600	0	0
T9	160440	7019	0	0
T10	36643	128	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	533886812	533756750	0	0
T1	1424	1345	0	0
T2	1778	1696	0	0
T3	2044	1977	0	0
T4	1668	1579	0	0
T5	5732	5639	0	0
T6	10597	10538	0	0
T7	225723	225667	0	0
T8	60532	60438	0	0
T9	160440	160342	0	0
T10	36643	36578	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533886812	533756750	0	0
T1	1424	1345	0	0
T2	1778	1696	0	0
T3	2044	1977	0	0
T4	1668	1579	0	0
T5	5732	5639	0	0
T6	10597	10538	0	0
T7	225723	225667	0	0
T8	60532	60438	0	0
T9	160440	160342	0	0
T10	36643	36578	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533886812	533756750	0	0
T1	1424	1345	0	0
T2	1778	1696	0	0
T3	2044	1977	0	0
T4	1668	1579	0	0
T5	5732	5639	0	0
T6	10597	10538	0	0
T7	225723	225667	0	0
T8	60532	60438	0	0
T9	160440	160342	0	0
T10	36643	36578	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533886812	533756750	0	0
T1	1424	1345	0	0
T2	1778	1696	0	0
T3	2044	1977	0	0
T4	1668	1579	0	0
T5	5732	5639	0	0
T6	10597	10538	0	0
T7	225723	225667	0	0
T8	60532	60438	0	0
T9	160440	160342	0	0
T10	36643	36578	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1129	1129	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	533886812	16836023	0	0
DataKnown_AKnownEnable	533886812	533756750	0	0
DepthKnown_A	533886812	533756750	0	0
RvalidKnown_A	533886812	533756750	0	0
WreadyKnown_A	533886812	533756750	0	0
gen_passthru_fifo.paramCheckPass	1129	1129	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533886812	16836023	0	0
T1	1424	43	0	0
T2	1778	1	0	0
T3	2044	11	0	0
T4	1668	14	0	0
T5	5732	266	0	0
T6	10597	230	0	0
T7	225723	365	0	0
T8	60532	1600	0	0
T9	160440	7018	0	0
T10	36643	125	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	533886812	533756750	0	0
T1	1424	1345	0	0
T2	1778	1696	0	0
T3	2044	1977	0	0
T4	1668	1579	0	0
T5	5732	5639	0	0
T6	10597	10538	0	0
T7	225723	225667	0	0
T8	60532	60438	0	0
T9	160440	160342	0	0
T10	36643	36578	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533886812	533756750	0	0
T1	1424	1345	0	0
T2	1778	1696	0	0
T3	2044	1977	0	0
T4	1668	1579	0	0
T5	5732	5639	0	0
T6	10597	10538	0	0
T7	225723	225667	0	0
T8	60532	60438	0	0
T9	160440	160342	0	0
T10	36643	36578	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533886812	533756750	0	0
T1	1424	1345	0	0
T2	1778	1696	0	0
T3	2044	1977	0	0
T4	1668	1579	0	0
T5	5732	5639	0	0
T6	10597	10538	0	0
T7	225723	225667	0	0
T8	60532	60438	0	0
T9	160440	160342	0	0
T10	36643	36578	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533886812	533756750	0	0
T1	1424	1345	0	0
T2	1778	1696	0	0
T3	2044	1977	0	0
T4	1668	1579	0	0
T5	5732	5639	0	0
T6	10597	10538	0	0
T7	225723	225667	0	0
T8	60532	60438	0	0
T9	160440	160342	0	0
T10	36643	36578	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1129	1129	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0