Unified Coverage Report :: Module :: prim_rst_sync

Module : prim_rst_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.00	50.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_tpm_csb_rst_sync	50.00	50.00

---

Module Instance : tb.dut.u_tpm_csb_rst_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.00	50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
70.83	88.89	44.44			100.00	50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
g_scan_mux.u_scan_mux	64.81	100.00	44.44				50.00
u_sync	100.00	100.00				100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_rst_sync

	Line No.	Total	Covered	Percent
TOTAL		2	1	50.00
CONT_ASSIGN	35	1	1	100.00
CONT_ASSIGN	36	1	0	0.00

34                        end else begin : g_rst_direct
35         1/1              assign async_rst_n = d_i;
           Tests:       T1 T2 T3 
36         0/1     ==>      assign scan_rst    = scan_rst_ni;