Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3401847	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3917764

1

T2

1

T4

6

T5

33

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4087694	1			T1	59		T2	65		T3	1
values[0x0]	1615635	1			T4	2		T5	15		T6	432
values[0x1]	1616282	1			T4	5		T5	14		T6	443

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2414600	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4905011

1

T1

18

T2

20

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28476	1			T1	2		T6	1		T10	4
valid_sources[0x01]	25914	1			T10	4		T11	20		T15	1
valid_sources[0x02]	27035	1			T6	8		T10	7		T11	58
valid_sources[0x03]	29412	1			T1	1		T6	4		T10	7
valid_sources[0x04]	27058	1			T6	11		T8	9		T10	1
valid_sources[0x05]	27280	1			T6	3		T11	46		T14	2
valid_sources[0x06]	28291	1			T10	5		T11	53		T14	1
valid_sources[0x07]	25201	1			T6	8		T10	3		T11	57
valid_sources[0x08]	27551	1			T1	1		T8	2		T10	6
valid_sources[0x09]	24807	1			T1	1		T2	2		T11	62
valid_sources[0x0a]	23710	1			T10	5		T11	29		T14	7
valid_sources[0x0b]	30906	1			T6	2		T10	1		T11	24
valid_sources[0x0c]	26921	1			T6	2		T10	3		T11	105
valid_sources[0x0d]	28798	1			T1	1		T8	2		T10	4
valid_sources[0x0e]	27138	1			T2	1		T6	5		T10	3
valid_sources[0x0f]	26175	1			T10	1		T11	21		T14	4
valid_sources[0x10]	24955	1			T6	3		T11	47		T14	1
valid_sources[0x11]	29272	1			T1	1		T6	5		T8	1
valid_sources[0x12]	27276	1			T2	2		T10	2		T11	41
valid_sources[0x13]	28513	1			T6	2		T8	5		T10	1
valid_sources[0x14]	28919	1			T1	2		T10	7		T11	44
valid_sources[0x15]	27393	1			T6	2		T10	4		T11	77
valid_sources[0x16]	28621	1			T8	1		T10	4		T11	52
valid_sources[0x17]	24270	1			T1	1		T11	47		T15	1
valid_sources[0x18]	27400	1			T1	1		T6	2		T10	8
valid_sources[0x19]	30210	1			T1	2		T6	4		T10	2
valid_sources[0x1a]	25101	1			T1	1		T10	4		T11	13
valid_sources[0x1b]	25728	1			T6	6		T10	9		T11	18
valid_sources[0x1c]	27869	1			T2	1		T6	6		T8	1
valid_sources[0x1d]	24672	1			T6	2		T10	6		T11	11
valid_sources[0x1e]	27290	1			T10	10		T11	49		T14	1
valid_sources[0x1f]	29363	1			T6	3		T10	3		T11	42
valid_sources[0x20]	27004	1			T1	1		T6	5		T10	5
valid_sources[0x21]	27940	1			T2	1		T6	5		T10	11
valid_sources[0x22]	27245	1			T2	1		T6	1		T10	8
valid_sources[0x23]	26886	1			T2	2		T11	56		T15	3
valid_sources[0x24]	26913	1			T10	5		T11	24		T14	1
valid_sources[0x25]	27292	1			T10	3		T11	33		T15	15
valid_sources[0x26]	29649	1			T6	9		T10	3		T11	34
valid_sources[0x27]	26406	1			T6	1		T10	7		T11	14
valid_sources[0x28]	25798	1			T10	2		T11	44		T14	6
valid_sources[0x29]	26946	1			T6	2		T10	8		T11	27
valid_sources[0x2a]	29759	1			T6	5		T8	1		T10	1
valid_sources[0x2b]	24627	1			T1	1		T10	5		T11	33
valid_sources[0x2c]	31285	1			T2	1		T10	6		T11	40
valid_sources[0x2d]	26686	1			T6	1		T10	1		T11	13
valid_sources[0x2e]	27261	1			T6	1		T10	6		T11	12
valid_sources[0x2f]	28570	1			T1	1		T11	63		T14	16
valid_sources[0x30]	27674	1			T6	6		T10	5		T11	17
valid_sources[0x31]	27353	1			T6	11		T8	1		T11	20
valid_sources[0x32]	24832	1			T2	1		T10	7		T11	84
valid_sources[0x33]	36480	1			T6	10		T11	41		T15	2
valid_sources[0x34]	30675	1			T6	1		T10	4		T11	87
valid_sources[0x35]	27873	1			T10	5		T11	37		T16	1
valid_sources[0x36]	27777	1			T2	1		T6	5		T8	2
valid_sources[0x37]	28402	1			T6	9		T10	4		T11	41
valid_sources[0x38]	25874	1			T6	6		T8	2		T11	17
valid_sources[0x39]	31697	1			T1	2		T11	58		T16	2
valid_sources[0x3a]	29171	1			T6	6		T10	1		T11	50
valid_sources[0x3b]	73430	1			T2	1		T8	7		T10	2
valid_sources[0x3c]	27193	1			T6	10		T10	3		T11	43
valid_sources[0x3d]	27867	1			T2	1		T6	1		T10	3
valid_sources[0x3e]	26709	1			T2	1		T6	2		T10	8
valid_sources[0x3f]	23950	1			T1	1		T6	1		T10	6
valid_sources[0x40]	27543	1			T6	5		T11	34		T17	3
valid_sources[0x41]	30758	1			T10	6		T11	36		T15	6
valid_sources[0x42]	35639	1			T6	4		T10	5		T11	53
valid_sources[0x43]	25931	1			T10	3		T11	58		T15	8
valid_sources[0x44]	25245	1			T6	2		T8	4		T10	2
valid_sources[0x45]	27573	1			T11	72		T14	15		T17	5
valid_sources[0x46]	27381	1			T6	6		T10	6		T11	81
valid_sources[0x47]	26522	1			T1	1		T2	1		T10	9
valid_sources[0x48]	29043	1			T6	2		T11	28		T16	4
valid_sources[0x49]	26327	1			T2	1		T11	82		T14	1
valid_sources[0x4a]	27940	1			T6	12		T11	4		T16	5
valid_sources[0x4b]	27134	1			T2	1		T6	7		T10	2
valid_sources[0x4c]	29251	1			T6	1		T11	21		T14	7
valid_sources[0x4d]	31611	1			T2	2		T6	1		T8	4
valid_sources[0x4e]	27066	1			T6	7		T11	22		T16	4
valid_sources[0x4f]	27323	1			T4	1		T6	11		T10	1
valid_sources[0x50]	24593	1			T6	3		T8	3		T11	28
valid_sources[0x51]	26428	1			T6	7		T10	1		T11	44
valid_sources[0x52]	26514	1			T2	1		T6	3		T10	5
valid_sources[0x53]	25022	1			T1	1		T6	5		T11	10
valid_sources[0x54]	28654	1			T6	1		T11	30		T14	5
valid_sources[0x55]	25924	1			T2	1		T6	1		T11	38
valid_sources[0x56]	33627	1			T8	6		T10	3		T11	38
valid_sources[0x57]	29049	1			T10	3		T11	18		T14	1
valid_sources[0x58]	26378	1			T6	12		T10	7		T11	63
valid_sources[0x59]	40047	1			T6	1		T8	2		T10	3
valid_sources[0x5a]	25325	1			T2	1		T6	23		T8	2
valid_sources[0x5b]	24784	1			T6	5		T10	4		T11	21
valid_sources[0x5c]	25468	1			T6	7		T10	2		T11	55
valid_sources[0x5d]	27002	1			T1	1		T6	4		T10	4
valid_sources[0x5e]	27690	1			T6	4		T8	5		T11	32
valid_sources[0x5f]	25736	1			T6	2		T7	11		T10	4
valid_sources[0x60]	25498	1			T10	7		T11	62		T14	3
valid_sources[0x61]	24266	1			T6	3		T10	8		T11	70
valid_sources[0x62]	32974	1			T6	6		T11	35		T14	3
valid_sources[0x63]	27124	1			T1	1		T10	5		T11	36
valid_sources[0x64]	26652	1			T2	3		T6	2		T10	4
valid_sources[0x65]	26571	1			T6	4		T11	39		T16	1
valid_sources[0x66]	25769	1			T2	3		T4	1		T6	1
valid_sources[0x67]	27724	1			T6	9		T10	1		T11	36
valid_sources[0x68]	27084	1			T11	14		T16	1		T17	3
valid_sources[0x69]	29852	1			T10	2		T11	106		T15	3
valid_sources[0x6a]	30643	1			T2	2		T10	8		T11	22
valid_sources[0x6b]	25295	1			T6	1		T8	2		T10	2
valid_sources[0x6c]	26474	1			T10	8		T11	59		T14	5
valid_sources[0x6d]	26564	1			T6	3		T10	4		T11	85
valid_sources[0x6e]	24447	1			T6	2		T8	16		T10	1
valid_sources[0x6f]	26447	1			T6	3		T10	2		T11	55
valid_sources[0x70]	26882	1			T8	4		T10	2		T11	37
valid_sources[0x71]	28022	1			T6	4		T11	46		T14	3
valid_sources[0x72]	24994	1			T2	1		T6	8		T8	2
valid_sources[0x73]	27952	1			T2	1		T6	1		T10	1
valid_sources[0x74]	26754	1			T2	1		T10	3		T11	19
valid_sources[0x75]	32540	1			T10	2		T11	81		T16	6
valid_sources[0x76]	25529	1			T1	1		T10	1		T11	69
valid_sources[0x77]	25033	1			T6	2		T10	3		T11	46
valid_sources[0x78]	24256	1			T10	3		T11	45		T14	15
valid_sources[0x79]	26427	1			T6	6		T10	4		T11	74
valid_sources[0x7a]	29506	1			T6	2		T10	5		T11	43
valid_sources[0x7b]	25245	1			T1	1		T6	16		T10	6
valid_sources[0x7c]	28864	1			T10	5		T11	48		T14	5
valid_sources[0x7d]	28203	1			T6	8		T11	34		T14	4
valid_sources[0x7e]	26957	1			T10	3		T11	69		T14	5
valid_sources[0x7f]	28684	1			T10	3		T11	52		T15	18
valid_sources[0x80]	26913	1			T6	2		T8	2		T10	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

988619

1

T2

1

T4

1

T5

26

values[0x0]

all_enables

biggest_size

1475708

1

T4

1

T5

4

T6

431

values[0x1]

all_enables

biggest_size

1453437

1

T4

4

T5

3

T6

442