Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3425528

1

T1

59

T2

64

T3

1

full_word

3919098

1

T2

1

T4

6

T5

33

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7344156	1			T1	59		T2	65		T3	1
auto[TlIntgErrCmd]	160	1			T108	7		T141	9		T143	16
auto[TlIntgErrData]	159	1			T108	8		T141	8		T143	9
auto[TlIntgErrBoth]	151	1			T108	15		T141	13		T143	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4093260

1

T1

59

T2

65

T3

1

auto[1]

3251366

1

T4

7

T5

29

T6

875

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3104022	1			T1	59		T2	64		T3	1
auto[TlIntgErrNone]	partial	auto[1]	321085	1			T4	2		T5	22		T6	2
auto[TlIntgErrNone]	full_word	auto[0]	989020	1			T2	1		T4	1		T5	26
auto[TlIntgErrNone]	full_word	auto[1]	2930029	1			T4	5		T5	7		T6	873
auto[TlIntgErrCmd]	partial	auto[0]	69	1			T108	2		T141	6		T143	7
auto[TlIntgErrCmd]	partial	auto[1]	79	1			T108	5		T141	2		T143	7
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T141	1		T351	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	10	1			T143	2		T351	2		T352	1
auto[TlIntgErrData]	partial	auto[0]	69	1			T108	4		T141	2		T143	4
auto[TlIntgErrData]	partial	auto[1]	72	1			T108	4		T141	5		T143	4
auto[TlIntgErrData]	full_word	auto[0]	10	1			T141	1		T143	1		T351	4
auto[TlIntgErrData]	full_word	auto[1]	8	1			T351	1		T195	1		T353	1
auto[TlIntgErrBoth]	partial	auto[0]	59	1			T108	7		T141	8		T143	2
auto[TlIntgErrBoth]	partial	auto[1]	73	1			T108	4		T141	2		T143	2
auto[TlIntgErrBoth]	full_word	auto[0]	9	1			T108	1		T141	1		T351	1
auto[TlIntgErrBoth]	full_word	auto[1]	10	1			T108	3		T141	2		T143	1