Module Definition
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Module : prim_generic_ram_1r1w
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_mem


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_mem


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_ram_1r1w
Line No.TotalCoveredPercent
TOTAL1111100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
ALWAYS6644100.00
ALWAYS7722100.00


44                        logic unused_cfg;
45         1/1            assign unused_cfg = ^cfg_i;
           Tests:       T3 
46                      
47                        // Width of internal write mask. Note *_wmask_i input into the module is always assumed
48                        // to be the full bit mask.
49                        localparam int MaskWidth = Width / DataBitsPerMask;
50                      
51                        logic [Width-1:0]     mem [Depth];
52                        logic [MaskWidth-1:0] a_wmask;
53                        for (genvar k = 0; k < MaskWidth; k++) begin : gen_wmask
54         4/4              assign a_wmask[k] = &a_wmask_i[k*DataBitsPerMask +: DataBitsPerMask];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
55                      
56                          // Ensure that all mask bits within a group have the same value for a write
57                          `ASSERT(MaskCheckPortA_A, a_req_i |->
58                              a_wmask_i[k*DataBitsPerMask +: DataBitsPerMask] inside {{DataBitsPerMask{1'b1}}, '0},
59                              clk_a_i, '0)
60                        end
61                      
62                        // Xilinx FPGA specific Two-port RAM coding style
63                        // using always instead of always_ff to avoid 'ICPD  - illegal combination of drivers' error
64                        // thrown due to 'mem' being driven by two always processes below
65                        always @(posedge clk_a_i) begin
66         1/1              if (a_req_i) begin
           Tests:       T1 T2 T3 
67         1/1                for (int i=0; i < MaskWidth; i = i + 1) begin
           Tests:       T5 T6 T10 
68         1/1                  if (a_wmask[i]) begin
           Tests:       T5 T6 T10 
69         1/1                    mem[a_addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
           Tests:       T5 T6 T10 
70                                  a_wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
71                              end
                        MISSING_ELSE
72                            end
73                          end
                        MISSING_ELSE
74                        end
75                      
76                        always @(posedge clk_b_i) begin
77         1/1              if (b_req_i) begin
           Tests:       T1 T2 T3 
78         1/1                b_rdata_o <= mem[b_addr_i];
           Tests:       T5 T11 T16 
79                          end
                        MISSING_ELSE
Branch Coverage for Module : prim_generic_ram_1r1w
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 66 2 2 100.00
IF 77 2 2 100.00 



66             if (a_req_i) begin
               -1-  
67               for (int i=0; i < MaskWidth; i = i + 1) begin
                 ==>
68                 if (a_wmask[i]) begin
69                   mem[a_addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
70                     a_wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
71                 end
72               end
73             end
               MISSING_ELSE
               ==>

Branches:
-1-StatusTests
1 Covered T5,T6,T10
0 Covered T1,T2,T3 



77             if (b_req_i) begin
               -1-  
78               b_rdata_o <= mem[b_addr_i];
                 ==>
79             end
               MISSING_ELSE
               ==>

Branches:
-1-StatusTests
1 Covered T5,T11,T16
0 Covered T1,T2,T3

Assert Coverage for Module : prim_generic_ram_1r1w
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_wmask[0].MaskCheckPortA_A 532178461 2934176 0 0
gen_wmask[1].MaskCheckPortA_A 532178461 2934176 0 0
gen_wmask[2].MaskCheckPortA_A 532178461 2934176 0 0
gen_wmask[3].MaskCheckPortA_A 532178461 2934176 0 0


gen_wmask[0].MaskCheckPortA_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 532178461 2934176 0 0
T5 3674 89 0 0
T6 3140 832 0 0
T7 1592 0 0 0
T8 2920 0 0 0
T9 5263 0 0 0
T10 8247 832 0 0
T11 276782 832 0 0
T12 1188 0 0 0
T13 7945 0 0 0
T14 3049 832 0 0
T15 46144 832 0 0
T16 13220 832 0 0
T17 2505 160 0 0
T18 34256 832 0 0
T19 92431 0 0 0
T21 26463 1344 0 0
T28 0 93 0 0
T30 0 1584 0 0
T31 0 6 0 0
T41 0 2708 0 0
T42 0 233 0 0
T43 0 83 0 0
T44 0 259 0 0
T56 0 6 0 0

gen_wmask[1].MaskCheckPortA_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 532178461 2934176 0 0
T5 3674 89 0 0
T6 3140 832 0 0
T7 1592 0 0 0
T8 2920 0 0 0
T9 5263 0 0 0
T10 8247 832 0 0
T11 276782 832 0 0
T12 1188 0 0 0
T13 7945 0 0 0
T14 3049 832 0 0
T15 46144 832 0 0
T16 13220 832 0 0
T17 2505 160 0 0
T18 34256 832 0 0
T19 92431 0 0 0
T21 26463 1344 0 0
T28 0 93 0 0
T30 0 1584 0 0
T31 0 6 0 0
T41 0 2708 0 0
T42 0 233 0 0
T43 0 83 0 0
T44 0 259 0 0
T56 0 6 0 0

gen_wmask[2].MaskCheckPortA_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 532178461 2934176 0 0
T5 3674 89 0 0
T6 3140 832 0 0
T7 1592 0 0 0
T8 2920 0 0 0
T9 5263 0 0 0
T10 8247 832 0 0
T11 276782 832 0 0
T12 1188 0 0 0
T13 7945 0 0 0
T14 3049 832 0 0
T15 46144 832 0 0
T16 13220 832 0 0
T17 2505 160 0 0
T18 34256 832 0 0
T19 92431 0 0 0
T21 26463 1344 0 0
T28 0 93 0 0
T30 0 1584 0 0
T31 0 6 0 0
T41 0 2708 0 0
T42 0 233 0 0
T43 0 83 0 0
T44 0 259 0 0
T56 0 6 0 0

gen_wmask[3].MaskCheckPortA_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 532178461 2934176 0 0
T5 3674 89 0 0
T6 3140 832 0 0
T7 1592 0 0 0
T8 2920 0 0 0
T9 5263 0 0 0
T10 8247 832 0 0
T11 276782 832 0 0
T12 1188 0 0 0
T13 7945 0 0 0
T14 3049 832 0 0
T15 46144 832 0 0
T16 13220 832 0 0
T17 2505 160 0 0
T18 34256 832 0 0
T19 92431 0 0 0
T21 26463 1344 0 0
T28 0 93 0 0
T30 0 1584 0 0
T31 0 6 0 0
T41 0 2708 0 0
T42 0 233 0 0
T43 0 83 0 0
T44 0 259 0 0
T56 0 6 0 0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL1111100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
ALWAYS6644100.00
ALWAYS7722100.00


44                        logic unused_cfg;
45         1/1            assign unused_cfg = ^cfg_i;
           Tests:       T3 
46                      
47                        // Width of internal write mask. Note *_wmask_i input into the module is always assumed
48                        // to be the full bit mask.
49                        localparam int MaskWidth = Width / DataBitsPerMask;
50                      
51                        logic [Width-1:0]     mem [Depth];
52                        logic [MaskWidth-1:0] a_wmask;
53                        for (genvar k = 0; k < MaskWidth; k++) begin : gen_wmask
54         4/4              assign a_wmask[k] = &a_wmask_i[k*DataBitsPerMask +: DataBitsPerMask];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
55                      
56                          // Ensure that all mask bits within a group have the same value for a write
57                          `ASSERT(MaskCheckPortA_A, a_req_i |->
58                              a_wmask_i[k*DataBitsPerMask +: DataBitsPerMask] inside {{DataBitsPerMask{1'b1}}, '0},
59                              clk_a_i, '0)
60                        end
61                      
62                        // Xilinx FPGA specific Two-port RAM coding style
63                        // using always instead of always_ff to avoid 'ICPD  - illegal combination of drivers' error
64                        // thrown due to 'mem' being driven by two always processes below
65                        always @(posedge clk_a_i) begin
66         1/1              if (a_req_i) begin
           Tests:       T1 T2 T3 
67         1/1                for (int i=0; i < MaskWidth; i = i + 1) begin
           Tests:       T5 T6 T10 
68         1/1                  if (a_wmask[i]) begin
           Tests:       T5 T6 T10 
69         1/1                    mem[a_addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
           Tests:       T5 T6 T10 
70                                  a_wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
71                              end
                   ==>  MISSING_ELSE
72                            end
73                          end
                        MISSING_ELSE
74                        end
75                      
76                        always @(posedge clk_b_i) begin
77         1/1              if (b_req_i) begin
           Tests:       T4 T5 T11 
78         1/1                b_rdata_o <= mem[b_addr_i];
           Tests:       T5 T11 T16 
79                          end
                        MISSING_ELSE
Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 66 2 2 100.00
IF 77 2 2 100.00 



66             if (a_req_i) begin
               -1-  
67               for (int i=0; i < MaskWidth; i = i + 1) begin
                 ==>
68                 if (a_wmask[i]) begin
69                   mem[a_addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
70                     a_wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
71                 end
72               end
73             end
               MISSING_ELSE
               ==>

Branches:
-1-StatusTests
1 Covered T5,T6,T10
0 Covered T1,T2,T3 



77             if (b_req_i) begin
               -1-  
78               b_rdata_o <= mem[b_addr_i];
                 ==>
79             end
               MISSING_ELSE
               ==>

Branches:
-1-StatusTests
1 Covered T5,T11,T16
0 Covered T4,T5,T11

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_wmask[0].MaskCheckPortA_A 402015770 1902839 0 0
gen_wmask[1].MaskCheckPortA_A 402015770 1902839 0 0
gen_wmask[2].MaskCheckPortA_A 402015770 1902839 0 0
gen_wmask[3].MaskCheckPortA_A 402015770 1902839 0 0


gen_wmask[0].MaskCheckPortA_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 402015770 1902839 0 0
T5 2810 1 0 0
T6 3140 832 0 0
T7 1592 0 0 0
T8 2920 0 0 0
T9 5263 0 0 0
T10 8247 832 0 0
T11 208016 832 0 0
T12 1188 0 0 0
T13 7081 0 0 0
T14 3033 832 0 0
T15 0 832 0 0
T16 0 832 0 0
T17 0 22 0 0
T18 0 832 0 0
T21 0 1344 0 0

gen_wmask[1].MaskCheckPortA_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 402015770 1902839 0 0
T5 2810 1 0 0
T6 3140 832 0 0
T7 1592 0 0 0
T8 2920 0 0 0
T9 5263 0 0 0
T10 8247 832 0 0
T11 208016 832 0 0
T12 1188 0 0 0
T13 7081 0 0 0
T14 3033 832 0 0
T15 0 832 0 0
T16 0 832 0 0
T17 0 22 0 0
T18 0 832 0 0
T21 0 1344 0 0

gen_wmask[2].MaskCheckPortA_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 402015770 1902839 0 0
T5 2810 1 0 0
T6 3140 832 0 0
T7 1592 0 0 0
T8 2920 0 0 0
T9 5263 0 0 0
T10 8247 832 0 0
T11 208016 832 0 0
T12 1188 0 0 0
T13 7081 0 0 0
T14 3033 832 0 0
T15 0 832 0 0
T16 0 832 0 0
T17 0 22 0 0
T18 0 832 0 0
T21 0 1344 0 0

gen_wmask[3].MaskCheckPortA_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 402015770 1902839 0 0
T5 2810 1 0 0
T6 3140 832 0 0
T7 1592 0 0 0
T8 2920 0 0 0
T9 5263 0 0 0
T10 8247 832 0 0
T11 208016 832 0 0
T12 1188 0 0 0
T13 7081 0 0 0
T14 3033 832 0 0
T15 0 832 0 0
T16 0 832 0 0
T17 0 22 0 0
T18 0 832 0 0
T21 0 1344 0 0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL1111100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
ALWAYS6644100.00
ALWAYS7722100.00


44                        logic unused_cfg;
45         1/1            assign unused_cfg = ^cfg_i;
           Tests:       T3 
46                      
47                        // Width of internal write mask. Note *_wmask_i input into the module is always assumed
48                        // to be the full bit mask.
49                        localparam int MaskWidth = Width / DataBitsPerMask;
50                      
51                        logic [Width-1:0]     mem [Depth];
52                        logic [MaskWidth-1:0] a_wmask;
53                        for (genvar k = 0; k < MaskWidth; k++) begin : gen_wmask
54         4/4              assign a_wmask[k] = &a_wmask_i[k*DataBitsPerMask +: DataBitsPerMask];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
55                      
56                          // Ensure that all mask bits within a group have the same value for a write
57                          `ASSERT(MaskCheckPortA_A, a_req_i |->
58                              a_wmask_i[k*DataBitsPerMask +: DataBitsPerMask] inside {{DataBitsPerMask{1'b1}}, '0},
59                              clk_a_i, '0)
60                        end
61                      
62                        // Xilinx FPGA specific Two-port RAM coding style
63                        // using always instead of always_ff to avoid 'ICPD  - illegal combination of drivers' error
64                        // thrown due to 'mem' being driven by two always processes below
65                        always @(posedge clk_a_i) begin
66         1/1              if (a_req_i) begin
           Tests:       T4 T5 T11 
67         1/1                for (int i=0; i < MaskWidth; i = i + 1) begin
           Tests:       T5 T17 T28 
68         1/1                  if (a_wmask[i]) begin
           Tests:       T5 T17 T28 
69         1/1                    mem[a_addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
           Tests:       T5 T17 T28 
70                                  a_wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
71                              end
                        MISSING_ELSE
72                            end
73                          end
                        MISSING_ELSE
74                        end
75                      
76                        always @(posedge clk_b_i) begin
77         1/1              if (b_req_i) begin
           Tests:       T1 T2 T3 
78         1/1                b_rdata_o <= mem[b_addr_i];
           Tests:       T5 T17 T28 
79                          end
                        MISSING_ELSE
Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 66 2 2 100.00
IF 77 2 2 100.00 



66             if (a_req_i) begin
               -1-  
67               for (int i=0; i < MaskWidth; i = i + 1) begin
                 ==>
68                 if (a_wmask[i]) begin
69                   mem[a_addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
70                     a_wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
71                 end
72               end
73             end
               MISSING_ELSE
               ==>

Branches:
-1-StatusTests
1 Covered T5,T17,T28
0 Covered T4,T5,T11 



77             if (b_req_i) begin
               -1-  
78               b_rdata_o <= mem[b_addr_i];
                 ==>
79             end
               MISSING_ELSE
               ==>

Branches:
-1-StatusTests
1 Covered T5,T17,T28
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_wmask[0].MaskCheckPortA_A 130162691 1031337 0 0
gen_wmask[1].MaskCheckPortA_A 130162691 1031337 0 0
gen_wmask[2].MaskCheckPortA_A 130162691 1031337 0 0
gen_wmask[3].MaskCheckPortA_A 130162691 1031337 0 0


gen_wmask[0].MaskCheckPortA_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 130162691 1031337 0 0
T5 864 88 0 0
T11 68766 0 0 0
T13 864 0 0 0
T14 16 0 0 0
T15 46144 0 0 0
T16 13220 0 0 0
T17 2505 138 0 0
T18 34256 0 0 0
T19 92431 0 0 0
T21 26463 0 0 0
T28 0 93 0 0
T30 0 1584 0 0
T31 0 6 0 0
T41 0 2708 0 0
T42 0 233 0 0
T43 0 83 0 0
T44 0 259 0 0
T56 0 6 0 0

gen_wmask[1].MaskCheckPortA_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 130162691 1031337 0 0
T5 864 88 0 0
T11 68766 0 0 0
T13 864 0 0 0
T14 16 0 0 0
T15 46144 0 0 0
T16 13220 0 0 0
T17 2505 138 0 0
T18 34256 0 0 0
T19 92431 0 0 0
T21 26463 0 0 0
T28 0 93 0 0
T30 0 1584 0 0
T31 0 6 0 0
T41 0 2708 0 0
T42 0 233 0 0
T43 0 83 0 0
T44 0 259 0 0
T56 0 6 0 0

gen_wmask[2].MaskCheckPortA_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 130162691 1031337 0 0
T5 864 88 0 0
T11 68766 0 0 0
T13 864 0 0 0
T14 16 0 0 0
T15 46144 0 0 0
T16 13220 0 0 0
T17 2505 138 0 0
T18 34256 0 0 0
T19 92431 0 0 0
T21 26463 0 0 0
T28 0 93 0 0
T30 0 1584 0 0
T31 0 6 0 0
T41 0 2708 0 0
T42 0 233 0 0
T43 0 83 0 0
T44 0 259 0 0
T56 0 6 0 0

gen_wmask[3].MaskCheckPortA_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 130162691 1031337 0 0
T5 864 88 0 0
T11 68766 0 0 0
T13 864 0 0 0
T14 16 0 0 0
T15 46144 0 0 0
T16 13220 0 0 0
T17 2505 138 0 0
T18 34256 0 0 0
T19 92431 0 0 0
T21 26463 0 0 0
T28 0 93 0 0
T30 0 1584 0 0
T31 0 6 0 0
T41 0 2708 0 0
T42 0 233 0 0
T43 0 83 0 0
T44 0 259 0 0
T56 0 6 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%