Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403968582	2601182	0	0
DataKnown_AKnownEnable	403968582	403832926	0	0
DepthKnown_A	403968582	403832926	0	0
RvalidKnown_A	403968582	403832926	0	0
WreadyKnown_A	403968582	403832926	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403968582	2601182	0	0
T6	3140	1663	0	0
T7	1592	0	0	0
T8	2920	0	0	0
T9	5263	0	0	0
T10	8247	832	0	0
T11	208016	832	0	0
T12	1188	0	0	0
T13	7081	0	0	0
T14	3033	1666	0	0
T15	14765	1663	0	0
T16	0	832	0	0
T18	0	832	0	0
T21	0	1854	0	0
T22	0	832	0	0
T23	0	832	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	403968582	403832926	0	0
T1	966	911	0	0
T2	1766	1672	0	0
T3	1423	1354	0	0
T4	2734	2674	0	0
T5	2810	2713	0	0
T6	3140	3049	0	0
T7	1592	1508	0	0
T8	2920	2705	0	0
T9	5263	3651	0	0
T10	8247	8193	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403968582	403832926	0	0
T1	966	911	0	0
T2	1766	1672	0	0
T3	1423	1354	0	0
T4	2734	2674	0	0
T5	2810	2713	0	0
T6	3140	3049	0	0
T7	1592	1508	0	0
T8	2920	2705	0	0
T9	5263	3651	0	0
T10	8247	8193	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403968582	403832926	0	0
T1	966	911	0	0
T2	1766	1672	0	0
T3	1423	1354	0	0
T4	2734	2674	0	0
T5	2810	2713	0	0
T6	3140	3049	0	0
T7	1592	1508	0	0
T8	2920	2705	0	0
T9	5263	3651	0	0
T10	8247	8193	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403968582	403832926	0	0
T1	966	911	0	0
T2	1766	1672	0	0
T3	1423	1354	0	0
T4	2734	2674	0	0
T5	2810	2713	0	0
T6	3140	3049	0	0
T7	1592	1508	0	0
T8	2920	2705	0	0
T9	5263	3651	0	0
T10	8247	8193	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403968582	2904610	0	0
DataKnown_AKnownEnable	403968582	403832926	0	0
DepthKnown_A	403968582	403832926	0	0
RvalidKnown_A	403968582	403832926	0	0
WreadyKnown_A	403968582	403832926	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403968582	2904610	0	0
T6	3140	832	0	0
T7	1592	0	0	0
T8	2920	0	0	0
T9	5263	0	0	0
T10	8247	832	0	0
T11	208016	832	0	0
T12	1188	0	0	0
T13	7081	0	0	0
T14	3033	835	0	0
T15	14765	832	0	0
T16	0	832	0	0
T18	0	832	0	0
T21	0	4332	0	0
T22	0	832	0	0
T23	0	3734	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	403968582	403832926	0	0
T1	966	911	0	0
T2	1766	1672	0	0
T3	1423	1354	0	0
T4	2734	2674	0	0
T5	2810	2713	0	0
T6	3140	3049	0	0
T7	1592	1508	0	0
T8	2920	2705	0	0
T9	5263	3651	0	0
T10	8247	8193	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403968582	403832926	0	0
T1	966	911	0	0
T2	1766	1672	0	0
T3	1423	1354	0	0
T4	2734	2674	0	0
T5	2810	2713	0	0
T6	3140	3049	0	0
T7	1592	1508	0	0
T8	2920	2705	0	0
T9	5263	3651	0	0
T10	8247	8193	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403968582	403832926	0	0
T1	966	911	0	0
T2	1766	1672	0	0
T3	1423	1354	0	0
T4	2734	2674	0	0
T5	2810	2713	0	0
T6	3140	3049	0	0
T7	1592	1508	0	0
T8	2920	2705	0	0
T9	5263	3651	0	0
T10	8247	8193	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403968582	403832926	0	0
T1	966	911	0	0
T2	1766	1672	0	0
T3	1423	1354	0	0
T4	2734	2674	0	0
T5	2810	2713	0	0
T6	3140	3049	0	0
T7	1592	1508	0	0
T8	2920	2705	0	0
T9	5263	3651	0	0
T10	8247	8193	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403968582	165901	0	0
DataKnown_AKnownEnable	403968582	403832926	0	0
DepthKnown_A	403968582	403832926	0	0
RvalidKnown_A	403968582	403832926	0	0
WreadyKnown_A	403968582	403832926	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403968582	165901	0	0
T5	2810	23	0	0
T6	3140	0	0	0
T7	1592	0	0	0
T8	2920	0	0	0
T9	5263	0	0	0
T10	8247	0	0	0
T11	208016	0	0	0
T12	1188	0	0	0
T13	7081	0	0	0
T14	3033	0	0	0
T17	0	36	0	0
T28	0	24	0	0
T30	0	412	0	0
T31	0	2	0	0
T41	0	704	0	0
T42	0	60	0	0
T43	0	22	0	0
T44	0	64	0	0
T45	0	562	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	403968582	403832926	0	0
T1	966	911	0	0
T2	1766	1672	0	0
T3	1423	1354	0	0
T4	2734	2674	0	0
T5	2810	2713	0	0
T6	3140	3049	0	0
T7	1592	1508	0	0
T8	2920	2705	0	0
T9	5263	3651	0	0
T10	8247	8193	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403968582	403832926	0	0
T1	966	911	0	0
T2	1766	1672	0	0
T3	1423	1354	0	0
T4	2734	2674	0	0
T5	2810	2713	0	0
T6	3140	3049	0	0
T7	1592	1508	0	0
T8	2920	2705	0	0
T9	5263	3651	0	0
T10	8247	8193	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403968582	403832926	0	0
T1	966	911	0	0
T2	1766	1672	0	0
T3	1423	1354	0	0
T4	2734	2674	0	0
T5	2810	2713	0	0
T6	3140	3049	0	0
T7	1592	1508	0	0
T8	2920	2705	0	0
T9	5263	3651	0	0
T10	8247	8193	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403968582	403832926	0	0
T1	966	911	0	0
T2	1766	1672	0	0
T3	1423	1354	0	0
T4	2734	2674	0	0
T5	2810	2713	0	0
T6	3140	3049	0	0
T7	1592	1508	0	0
T8	2920	2705	0	0
T9	5263	3651	0	0
T10	8247	8193	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403968582	374250	0	0
DataKnown_AKnownEnable	403968582	403832926	0	0
DepthKnown_A	403968582	403832926	0	0
RvalidKnown_A	403968582	403832926	0	0
WreadyKnown_A	403968582	403832926	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403968582	374250	0	0
T5	2810	23	0	0
T6	3140	0	0	0
T7	1592	0	0	0
T8	2920	0	0	0
T9	5263	0	0	0
T10	8247	0	0	0
T11	208016	0	0	0
T12	1188	0	0	0
T13	7081	0	0	0
T14	3033	0	0	0
T17	0	175	0	0
T28	0	99	0	0
T30	0	412	0	0
T31	0	4	0	0
T41	0	704	0	0
T42	0	290	0	0
T43	0	22	0	0
T44	0	195	0	0
T45	0	1556	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	403968582	403832926	0	0
T1	966	911	0	0
T2	1766	1672	0	0
T3	1423	1354	0	0
T4	2734	2674	0	0
T5	2810	2713	0	0
T6	3140	3049	0	0
T7	1592	1508	0	0
T8	2920	2705	0	0
T9	5263	3651	0	0
T10	8247	8193	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403968582	403832926	0	0
T1	966	911	0	0
T2	1766	1672	0	0
T3	1423	1354	0	0
T4	2734	2674	0	0
T5	2810	2713	0	0
T6	3140	3049	0	0
T7	1592	1508	0	0
T8	2920	2705	0	0
T9	5263	3651	0	0
T10	8247	8193	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403968582	403832926	0	0
T1	966	911	0	0
T2	1766	1672	0	0
T3	1423	1354	0	0
T4	2734	2674	0	0
T5	2810	2713	0	0
T6	3140	3049	0	0
T7	1592	1508	0	0
T8	2920	2705	0	0
T9	5263	3651	0	0
T10	8247	8193	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403968582	403832926	0	0
T1	966	911	0	0
T2	1766	1672	0	0
T3	1423	1354	0	0
T4	2734	2674	0	0
T5	2810	2713	0	0
T6	3140	3049	0	0
T7	1592	1508	0	0
T8	2920	2705	0	0
T9	5263	3651	0	0
T10	8247	8193	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403968582	5819141	0	0
DataKnown_AKnownEnable	403968582	403832926	0	0
DepthKnown_A	403968582	403832926	0	0
RvalidKnown_A	403968582	403832926	0	0
WreadyKnown_A	403968582	403832926	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403968582	5819141	0	0
T1	966	59	0	0
T2	1766	65	0	0
T3	1423	1	0	0
T4	2734	8	0	0
T5	2810	267	0	0
T6	3140	45	0	0
T7	1592	11	0	0
T8	2920	169	0	0
T9	5263	1	0	0
T10	8247	55	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	403968582	403832926	0	0
T1	966	911	0	0
T2	1766	1672	0	0
T3	1423	1354	0	0
T4	2734	2674	0	0
T5	2810	2713	0	0
T6	3140	3049	0	0
T7	1592	1508	0	0
T8	2920	2705	0	0
T9	5263	3651	0	0
T10	8247	8193	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403968582	403832926	0	0
T1	966	911	0	0
T2	1766	1672	0	0
T3	1423	1354	0	0
T4	2734	2674	0	0
T5	2810	2713	0	0
T6	3140	3049	0	0
T7	1592	1508	0	0
T8	2920	2705	0	0
T9	5263	3651	0	0
T10	8247	8193	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403968582	403832926	0	0
T1	966	911	0	0
T2	1766	1672	0	0
T3	1423	1354	0	0
T4	2734	2674	0	0
T5	2810	2713	0	0
T6	3140	3049	0	0
T7	1592	1508	0	0
T8	2920	2705	0	0
T9	5263	3651	0	0
T10	8247	8193	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403968582	403832926	0	0
T1	966	911	0	0
T2	1766	1672	0	0
T3	1423	1354	0	0
T4	2734	2674	0	0
T5	2810	2713	0	0
T6	3140	3049	0	0
T7	1592	1508	0	0
T8	2920	2705	0	0
T9	5263	3651	0	0
T10	8247	8193	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403968582	11554087	0	0
DataKnown_AKnownEnable	403968582	403832926	0	0
DepthKnown_A	403968582	403832926	0	0
RvalidKnown_A	403968582	403832926	0	0
WreadyKnown_A	403968582	403832926	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403968582	11554087	0	0
T1	966	59	0	0
T2	1766	298	0	0
T3	1423	1	0	0
T4	2734	8	0	0
T5	2810	267	0	0
T6	3140	45	0	0
T7	1592	39	0	0
T8	2920	169	0	0
T9	5263	1	0	0
T10	8247	53	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	403968582	403832926	0	0
T1	966	911	0	0
T2	1766	1672	0	0
T3	1423	1354	0	0
T4	2734	2674	0	0
T5	2810	2713	0	0
T6	3140	3049	0	0
T7	1592	1508	0	0
T8	2920	2705	0	0
T9	5263	3651	0	0
T10	8247	8193	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403968582	403832926	0	0
T1	966	911	0	0
T2	1766	1672	0	0
T3	1423	1354	0	0
T4	2734	2674	0	0
T5	2810	2713	0	0
T6	3140	3049	0	0
T7	1592	1508	0	0
T8	2920	2705	0	0
T9	5263	3651	0	0
T10	8247	8193	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403968582	403832926	0	0
T1	966	911	0	0
T2	1766	1672	0	0
T3	1423	1354	0	0
T4	2734	2674	0	0
T5	2810	2713	0	0
T6	3140	3049	0	0
T7	1592	1508	0	0
T8	2920	2705	0	0
T9	5263	3651	0	0
T10	8247	8193	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403968582	403832926	0	0
T1	966	911	0	0
T2	1766	1672	0	0
T3	1423	1354	0	0
T4	2734	2674	0	0
T5	2810	2713	0	0
T6	3140	3049	0	0
T7	1592	1508	0	0
T8	2920	2705	0	0
T9	5263	3651	0	0
T10	8247	8193	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0