Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3484413	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4178622

1

T2

1

T3

30

T4

23

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4129342	1			T1	51		T2	1		T3	1
values[0x0]	1764269	1			T3	22		T4	10		T5	446
values[0x1]	1769424	1			T3	15		T4	11		T5	431

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2466501	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5196534

1

T1

16

T2

1

T3

30

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27379	1			T1	1		T8	12		T10	4
valid_sources[0x01]	28453	1			T4	2		T8	10		T10	4
valid_sources[0x02]	27683	1			T5	4		T8	9		T10	3
valid_sources[0x03]	32557	1			T8	9		T9	33		T10	1
valid_sources[0x04]	28963	1			T5	12		T7	533		T8	16
valid_sources[0x05]	27990	1			T8	7		T10	1		T11	19
valid_sources[0x06]	30848	1			T8	3		T9	8		T10	3
valid_sources[0x07]	30377	1			T1	1		T8	7		T10	9
valid_sources[0x08]	28470	1			T5	6		T8	11		T9	1
valid_sources[0x09]	30187	1			T4	2		T8	8		T9	37
valid_sources[0x0a]	29810	1			T5	14		T8	16		T11	28
valid_sources[0x0b]	28391	1			T8	18		T10	6		T11	24
valid_sources[0x0c]	29644	1			T5	12		T8	6		T10	7
valid_sources[0x0d]	33825	1			T5	1		T8	15		T9	4
valid_sources[0x0e]	29909	1			T8	8		T10	2		T11	17
valid_sources[0x0f]	28251	1			T8	15		T10	2		T11	21
valid_sources[0x10]	41021	1			T8	15		T9	3		T10	2
valid_sources[0x11]	27805	1			T5	8		T8	17		T10	4
valid_sources[0x12]	28920	1			T4	1		T5	37		T8	14
valid_sources[0x13]	31541	1			T1	1		T3	5		T5	12
valid_sources[0x14]	28632	1			T4	1		T5	14		T8	19
valid_sources[0x15]	30364	1			T5	9		T8	14		T9	6
valid_sources[0x16]	29351	1			T1	1		T5	14		T8	16
valid_sources[0x17]	32424	1			T8	6		T10	3		T11	26
valid_sources[0x18]	31780	1			T4	4		T5	4		T8	9
valid_sources[0x19]	29769	1			T8	9		T10	3		T11	28
valid_sources[0x1a]	33546	1			T1	1		T4	3		T8	15
valid_sources[0x1b]	32440	1			T8	20		T10	2		T11	27
valid_sources[0x1c]	28150	1			T4	3		T8	6		T10	4
valid_sources[0x1d]	28460	1			T5	7		T8	10		T9	37
valid_sources[0x1e]	28300	1			T8	9		T9	7		T10	7
valid_sources[0x1f]	33994	1			T8	8		T10	1		T11	24
valid_sources[0x20]	27474	1			T8	12		T9	7		T10	6
valid_sources[0x21]	30035	1			T4	1		T8	11		T10	3
valid_sources[0x22]	28133	1			T1	1		T8	13		T10	10
valid_sources[0x23]	28688	1			T4	3		T5	15		T8	7
valid_sources[0x24]	29790	1			T8	8		T10	4		T11	34
valid_sources[0x25]	27438	1			T8	18		T9	11		T10	3
valid_sources[0x26]	26455	1			T8	15		T9	13		T10	1
valid_sources[0x27]	29918	1			T8	8		T9	3		T10	4
valid_sources[0x28]	31570	1			T5	6		T8	9		T9	41
valid_sources[0x29]	29368	1			T5	38		T8	15		T9	3
valid_sources[0x2a]	29736	1			T8	13		T10	4		T11	26
valid_sources[0x2b]	27886	1			T8	10		T9	8		T10	5
valid_sources[0x2c]	32722	1			T8	10		T10	2		T11	26
valid_sources[0x2d]	34305	1			T1	1		T5	5		T8	11
valid_sources[0x2e]	30070	1			T4	2		T8	18		T10	3
valid_sources[0x2f]	29419	1			T1	1		T8	9		T10	4
valid_sources[0x30]	28690	1			T1	1		T4	3		T8	9
valid_sources[0x31]	30750	1			T1	1		T8	13		T10	3
valid_sources[0x32]	28758	1			T8	9		T11	24		T13	29
valid_sources[0x33]	25888	1			T8	13		T10	3		T11	33
valid_sources[0x34]	29622	1			T8	13		T9	23		T10	3
valid_sources[0x35]	27753	1			T8	10		T10	4		T11	17
valid_sources[0x36]	29991	1			T8	9		T9	10		T10	3
valid_sources[0x37]	30431	1			T8	11		T10	6		T11	28
valid_sources[0x38]	28530	1			T8	13		T10	5		T11	32
valid_sources[0x39]	31706	1			T8	12		T10	1		T11	31
valid_sources[0x3a]	31936	1			T5	26		T8	10		T10	5
valid_sources[0x3b]	29656	1			T1	2		T4	1		T5	17
valid_sources[0x3c]	28981	1			T8	12		T9	2		T10	4
valid_sources[0x3d]	28643	1			T8	11		T10	1		T11	18
valid_sources[0x3e]	30793	1			T1	1		T4	2		T8	14
valid_sources[0x3f]	30030	1			T8	13		T10	7		T11	31
valid_sources[0x40]	28648	1			T1	2		T5	2		T8	12
valid_sources[0x41]	30569	1			T8	14		T10	2		T11	25
valid_sources[0x42]	28467	1			T8	12		T10	3		T11	26
valid_sources[0x43]	31071	1			T1	2		T8	9		T10	2
valid_sources[0x44]	36411	1			T1	1		T8	15		T10	6
valid_sources[0x45]	28926	1			T1	1		T8	13		T10	8
valid_sources[0x46]	29823	1			T8	12		T9	21		T10	2
valid_sources[0x47]	28191	1			T8	12		T11	29		T13	24
valid_sources[0x48]	27845	1			T5	17		T8	15		T10	5
valid_sources[0x49]	34465	1			T4	1		T8	16		T10	5
valid_sources[0x4a]	29463	1			T1	1		T4	4		T5	16
valid_sources[0x4b]	30191	1			T4	3		T5	9		T8	18
valid_sources[0x4c]	29277	1			T8	8		T9	22		T10	4
valid_sources[0x4d]	26802	1			T8	16		T10	6		T11	25
valid_sources[0x4e]	26084	1			T4	1		T8	14		T10	2
valid_sources[0x4f]	31968	1			T8	9		T10	5		T11	22
valid_sources[0x50]	29657	1			T8	13		T10	5		T11	22
valid_sources[0x51]	29333	1			T8	13		T10	4		T11	29
valid_sources[0x52]	28312	1			T4	1		T8	14		T10	8
valid_sources[0x53]	28851	1			T1	1		T5	3		T8	10
valid_sources[0x54]	28574	1			T8	12		T10	3		T11	24
valid_sources[0x55]	30570	1			T1	3		T8	14		T10	3
valid_sources[0x56]	27460	1			T4	3		T8	18		T9	4
valid_sources[0x57]	28090	1			T5	21		T8	11		T9	25
valid_sources[0x58]	29810	1			T2	1		T4	3		T8	13
valid_sources[0x59]	28066	1			T4	4		T8	11		T10	5
valid_sources[0x5a]	29125	1			T8	7		T10	2		T11	29
valid_sources[0x5b]	29697	1			T4	5		T5	3		T8	10
valid_sources[0x5c]	28440	1			T1	1		T8	12		T10	4
valid_sources[0x5d]	29277	1			T4	1		T8	10		T10	4
valid_sources[0x5e]	29046	1			T8	15		T9	6		T10	5
valid_sources[0x5f]	31657	1			T8	17		T10	3		T11	33
valid_sources[0x60]	32174	1			T5	14		T8	14		T10	6
valid_sources[0x61]	29284	1			T8	9		T10	6		T11	20
valid_sources[0x62]	27336	1			T8	14		T9	3		T10	4
valid_sources[0x63]	29437	1			T5	4		T8	10		T10	8
valid_sources[0x64]	27698	1			T8	23		T10	1		T11	29
valid_sources[0x65]	30719	1			T4	2		T8	14		T9	25
valid_sources[0x66]	26299	1			T4	2		T8	16		T10	6
valid_sources[0x67]	30867	1			T4	7		T8	14		T9	9
valid_sources[0x68]	28449	1			T8	7		T9	14		T10	3
valid_sources[0x69]	28500	1			T4	2		T5	7		T8	12
valid_sources[0x6a]	26823	1			T4	1		T8	13		T10	4
valid_sources[0x6b]	51100	1			T4	3		T8	5		T10	3
valid_sources[0x6c]	29344	1			T8	17		T10	2		T11	27
valid_sources[0x6d]	26664	1			T1	1		T8	15		T10	3
valid_sources[0x6e]	32729	1			T8	15		T9	44		T10	4
valid_sources[0x6f]	30378	1			T4	5		T5	14		T8	12
valid_sources[0x70]	27288	1			T8	13		T10	4		T11	20
valid_sources[0x71]	33506	1			T5	26		T8	15		T10	3
valid_sources[0x72]	26939	1			T8	10		T9	1		T10	3
valid_sources[0x73]	29909	1			T8	12		T10	11		T11	24
valid_sources[0x74]	31892	1			T5	4		T8	17		T10	2
valid_sources[0x75]	27125	1			T4	1		T5	7		T8	18
valid_sources[0x76]	29342	1			T4	1		T8	13		T10	8
valid_sources[0x77]	29913	1			T5	1		T8	17		T10	4
valid_sources[0x78]	28301	1			T8	11		T10	3		T11	43
valid_sources[0x79]	29639	1			T8	12		T10	5		T11	26
valid_sources[0x7a]	29299	1			T8	10		T10	5		T11	18
valid_sources[0x7b]	27481	1			T4	1		T8	19		T10	4
valid_sources[0x7c]	30077	1			T4	4		T8	12		T11	25
valid_sources[0x7d]	28351	1			T4	4		T8	16		T10	5
valid_sources[0x7e]	27324	1			T8	6		T10	4		T11	22
valid_sources[0x7f]	28225	1			T1	1		T4	4		T8	9
valid_sources[0x80]	27953	1			T4	3		T5	2		T8	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

970488

1

T2

1

T3

1

T4

18

values[0x0]

all_enables

biggest_size

1613898

1

T3

16

T4

3

T5

446

values[0x1]

all_enables

biggest_size

1594236

1

T3

13

T4

2

T5

431