Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3504344

1

T1

51

T3

8

T4

169

full_word

4179765

1

T2

1

T3

30

T4

23

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7683659	1			T1	51		T2	1		T3	38
auto[TlIntgErrCmd]	138	1			T103	12		T104	6		T105	3
auto[TlIntgErrData]	161	1			T103	5		T104	11		T105	9
auto[TlIntgErrBoth]	151	1			T103	13		T104	3		T105	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4133249

1

T1

51

T2

1

T3

1

auto[1]

3550860

1

T3

37

T4

21

T5

877

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3162290	1			T1	51		T4	153		T5	1
auto[TlIntgErrNone]	partial	auto[1]	341646	1			T3	8		T4	16		T6	2
auto[TlIntgErrNone]	full_word	auto[0]	970756	1			T2	1		T3	1		T4	18
auto[TlIntgErrNone]	full_word	auto[1]	3208967	1			T3	29		T4	5		T5	877
auto[TlIntgErrCmd]	partial	auto[0]	51	1			T103	4		T104	2		T105	2
auto[TlIntgErrCmd]	partial	auto[1]	74	1			T103	7		T104	4		T105	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T174	1		T110	1		T181	1
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T103	1		T110	1		T182	1
auto[TlIntgErrData]	partial	auto[0]	78	1			T103	3		T104	9		T105	4
auto[TlIntgErrData]	partial	auto[1]	67	1			T103	2		T104	1		T105	3
auto[TlIntgErrData]	full_word	auto[0]	10	1			T104	1		T105	1		T110	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T105	1		T174	1		T182	1
auto[TlIntgErrBoth]	partial	auto[0]	56	1			T103	4		T104	1		T105	2
auto[TlIntgErrBoth]	partial	auto[1]	82	1			T103	9		T104	1		T105	5
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T105	1		T183	1		T181	2
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T104	1		T110	2		T182	1