Module Definition
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Module : prim_pulse_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_flash_readbuf_watermark_pulse_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_flash_readbuf_flip_pulse_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_upload.u_payloadptr_clr_psync 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.52 95.20 84.31 97.00 90.62 95.45 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.52 95.20 84.31 97.00 90.62 95.45 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.u_upload.u_payloadptr_clr_psync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.37 100.00 86.11 100.00 95.74 100.00 u_upload


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00

Line Coverage for Module : prim_pulse_sync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00


30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T3 T4 T5 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3 
Cond Coverage for Module : prim_pulse_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT3,T4,T5
01CoveredT13,T14,T15
10CoveredT13,T14,T15
11CoveredT13,T14,T15 

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT13,T14,T15
10CoveredT13,T14,T15
11CoveredT13,T14,T15
Branch Coverage for Module : prim_pulse_sync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00 



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T3,T4,T5 



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Assert Coverage for Module : prim_pulse_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 1305036459 2874 0 0
SrcPulseCheck_M 454795986 2874 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1305036459 2874 0 0
T13 231962 7 0 0
T14 402146 12 0 0
T15 871521 5 0 0
T16 22914 0 0 0
T17 1094433 9 0 0
T23 2976 0 0 0
T24 4800 0 0 0
T25 37158 0 0 0
T26 19284 0 0 0
T27 1245114 0 0 0
T34 34121 0 0 0
T35 6626 0 0 0
T39 0 2 0 0
T40 0 6 0 0
T43 0 5 0 0
T45 0 7 0 0
T46 0 4 0 0
T72 0 6 0 0
T73 0 12 0 0
T74 0 7 0 0
T75 0 2 0 0
T78 0 7 0 0
T117 0 10 0 0
T145 0 10 0 0
T146 0 7 0 0
T147 0 7 0 0
T148 0 7 0 0
T149 0 2 0 0
T150 0 2 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 454795986 2874 0 0
T13 32266 7 0 0
T14 131746 12 0 0
T15 747936 5 0 0
T17 942348 9 0 0
T25 3906 0 0 0
T26 7560 0 0 0
T27 248712 0 0 0
T34 46734 0 0 0
T35 24768 0 0 0
T36 67272 0 0 0
T39 0 2 0 0
T40 0 6 0 0
T43 0 5 0 0
T45 0 7 0 0
T46 0 4 0 0
T49 17836 0 0 0
T58 31936 0 0 0
T72 0 6 0 0
T73 0 12 0 0
T74 0 7 0 0
T75 0 2 0 0
T78 0 7 0 0
T117 0 10 0 0
T145 0 10 0 0
T146 0 7 0 0
T147 0 7 0 0
T148 0 7 0 0
T149 0 2 0 0
T150 0 2 0 0

Line Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00


30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T3 T4 T5 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT3,T4,T5
01CoveredT13,T14,T45
10CoveredT13,T14,T45
11CoveredT13,T14,T45 

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT13,T14,T45
10CoveredT13,T14,T45
11CoveredT13,T14,T45
Branch Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00 



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T3,T4,T5 



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 435012153 175 0 0
SrcPulseCheck_M 151598662 175 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435012153 175 0 0
T13 115981 2 0 0
T14 201073 6 0 0
T15 290507 0 0 0
T16 7638 0 0 0
T17 364811 0 0 0
T23 992 0 0 0
T24 1600 0 0 0
T25 12386 0 0 0
T26 6428 0 0 0
T27 415038 0 0 0
T45 0 2 0 0
T78 0 2 0 0
T117 0 5 0 0
T145 0 5 0 0
T146 0 2 0 0
T147 0 2 0 0
T148 0 2 0 0
T150 0 2 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 151598662 175 0 0
T13 16133 2 0 0
T14 65873 6 0 0
T15 249312 0 0 0
T17 314116 0 0 0
T25 1302 0 0 0
T26 2520 0 0 0
T27 82904 0 0 0
T34 15578 0 0 0
T35 8256 0 0 0
T36 22424 0 0 0
T45 0 2 0 0
T78 0 2 0 0
T117 0 5 0 0
T145 0 5 0 0
T146 0 2 0 0
T147 0 2 0 0
T148 0 2 0 0
T150 0 2 0 0

Line Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00


30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T3 T4 T5 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT3,T4,T5
01CoveredT13,T14,T45
10CoveredT13,T14,T45
11CoveredT13,T14,T45 

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT13,T14,T45
10CoveredT13,T14,T45
11CoveredT13,T14,T45
Branch Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00 



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T3,T4,T5 



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 435012153 328 0 0
SrcPulseCheck_M 151598662 328 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435012153 328 0 0
T13 115981 5 0 0
T14 201073 6 0 0
T15 290507 0 0 0
T16 7638 0 0 0
T17 364811 0 0 0
T23 992 0 0 0
T24 1600 0 0 0
T25 12386 0 0 0
T26 6428 0 0 0
T27 415038 0 0 0
T45 0 5 0 0
T78 0 5 0 0
T117 0 5 0 0
T145 0 5 0 0
T146 0 5 0 0
T147 0 5 0 0
T148 0 5 0 0
T149 0 2 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 151598662 328 0 0
T13 16133 5 0 0
T14 65873 6 0 0
T15 249312 0 0 0
T17 314116 0 0 0
T25 1302 0 0 0
T26 2520 0 0 0
T27 82904 0 0 0
T34 15578 0 0 0
T35 8256 0 0 0
T36 22424 0 0 0
T45 0 5 0 0
T78 0 5 0 0
T117 0 5 0 0
T145 0 5 0 0
T146 0 5 0 0
T147 0 5 0 0
T148 0 5 0 0
T149 0 2 0 0

Line Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00


30                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
32         1/1                src_level <= 1'b0;
           Tests:       T1 T2 T3 
33                          end else begin
34         1/1                src_level <= src_level ^ src_pulse_i;
           Tests:       T3 T4 T5 
35                          end
36                        end
37                      
38                      
39                        // source active must come far enough such that the destination domain has time
40                        // to create a valid pulse.
41                      `ifdef INC_ASSERT
42                        //VCS coverage off
43                        // pragma coverage off
44                      
45                        // source active flag tracks whether there is an ongoing "toggle" event.
46                        // Until this toggle event is accepted by the destination domain (negative edge of
47                        // of the pulse output), the source side cannot toggle again.
48                        logic effective_rst_n;
49         unreachable    assign effective_rst_n = rst_src_ni && dst_pulse_o;
50                      
51                        logic src_active_flag_d, src_active_flag_q;
52         unreachable    assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53                      
54                        always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55         unreachable      if (!effective_rst_n) begin
56         unreachable        src_active_flag_q <= '0;
57                          end else begin
58         unreachable        src_active_flag_q <= src_active_flag_d;
59                          end
60                        end
61                      
62                        //VCS coverage on
63                        // pragma coverage on
64                      
65                        `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66                      `endif
67                      
68                        //////////////////////////////////////////////////////////
69                        // synchronize level signal to destination clock domain //
70                        //////////////////////////////////////////////////////////
71                        logic dst_level;
72                      
73                        prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74                          // source clock domain
75                          .d_i    (src_level),
76                          // destination clock domain
77                          .clk_i  (clk_dst_i),
78                          .rst_ni (rst_dst_ni),
79                          .q_o    (dst_level)
80                        );
81                      
82                        ////////////////////////////////////////
83                        // convert level signal back to pulse //
84                        ////////////////////////////////////////
85                        logic dst_level_q;
86                      
87                        // delay dst_level by 1 cycle
88                        always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89         1/1              if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
90         1/1                dst_level_q <= 1'b0;
           Tests:       T1 T2 T3 
91                          end else begin
92         1/1                dst_level_q <= dst_level;
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // edge detection
97         1/1            assign dst_pulse_o = dst_level_q ^ dst_level;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT3,T4,T5
01CoveredT15,T17,T46
10CoveredT15,T17,T46
11CoveredT15,T17,T46 

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT15,T17,T46
10CoveredT15,T17,T46
11CoveredT15,T17,T46
Branch Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00 



31             if (!rst_src_ni) begin
               -1-  
32               src_level <= 1'b0;
                 ==>
33             end else begin
34               src_level <= src_level ^ src_pulse_i;
                 ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T3,T4,T5 



89             if (!rst_dst_ni) begin
               -1-  
90               dst_level_q <= 1'b0;
                 ==>
91             end else begin
92               dst_level_q <= dst_level;
                 ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 435012153 2371 0 0
SrcPulseCheck_M 151598662 2371 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435012153 2371 0 0
T15 290507 5 0 0
T16 7638 0 0 0
T17 364811 9 0 0
T23 992 0 0 0
T24 1600 0 0 0
T25 12386 0 0 0
T26 6428 0 0 0
T27 415038 0 0 0
T34 34121 0 0 0
T35 6626 0 0 0
T39 0 2 0 0
T40 0 6 0 0
T43 0 5 0 0
T46 0 4 0 0
T72 0 6 0 0
T73 0 12 0 0
T74 0 7 0 0
T75 0 2 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 151598662 2371 0 0
T15 249312 5 0 0
T17 314116 9 0 0
T25 1302 0 0 0
T26 2520 0 0 0
T27 82904 0 0 0
T34 15578 0 0 0
T35 8256 0 0 0
T36 22424 0 0 0
T39 0 2 0 0
T40 0 6 0 0
T43 0 5 0 0
T46 0 4 0 0
T49 17836 0 0 0
T58 31936 0 0 0
T72 0 6 0 0
T73 0 12 0 0
T74 0 7 0 0
T75 0 2 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%