Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	437598150	2900484	0	0
DataKnown_AKnownEnable	437598150	437463033	0	0
DepthKnown_A	437598150	437463033	0	0
RvalidKnown_A	437598150	437463033	0	0
WreadyKnown_A	437598150	437463033	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437598150	2900484	0	0
T5	45620	832	0	0
T6	32159	832	0	0
T7	418369	0	0	0
T8	56192	1663	0	0
T9	13544	832	0	0
T10	82696	1663	0	0
T11	174372	0	0	0
T12	39977	1663	0	0
T13	115981	1663	0	0
T14	201073	4729	0	0
T15	0	3328	0	0
T17	0	6657	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	437598150	437463033	0	0
T1	1404	1308	0	0
T2	1589	1496	0	0
T3	2381	2317	0	0
T4	2169	2094	0	0
T5	45620	45537	0	0
T6	32159	32066	0	0
T7	418369	418274	0	0
T8	56192	56124	0	0
T9	13544	13477	0	0
T10	82696	82596	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437598150	437463033	0	0
T1	1404	1308	0	0
T2	1589	1496	0	0
T3	2381	2317	0	0
T4	2169	2094	0	0
T5	45620	45537	0	0
T6	32159	32066	0	0
T7	418369	418274	0	0
T8	56192	56124	0	0
T9	13544	13477	0	0
T10	82696	82596	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437598150	437463033	0	0
T1	1404	1308	0	0
T2	1589	1496	0	0
T3	2381	2317	0	0
T4	2169	2094	0	0
T5	45620	45537	0	0
T6	32159	32066	0	0
T7	418369	418274	0	0
T8	56192	56124	0	0
T9	13544	13477	0	0
T10	82696	82596	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437598150	437463033	0	0
T1	1404	1308	0	0
T2	1589	1496	0	0
T3	2381	2317	0	0
T4	2169	2094	0	0
T5	45620	45537	0	0
T6	32159	32066	0	0
T7	418369	418274	0	0
T8	56192	56124	0	0
T9	13544	13477	0	0
T10	82696	82596	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	437598150	3196004	0	0
DataKnown_AKnownEnable	437598150	437463033	0	0
DepthKnown_A	437598150	437463033	0	0
RvalidKnown_A	437598150	437463033	0	0
WreadyKnown_A	437598150	437463033	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437598150	3196004	0	0
T5	45620	832	0	0
T6	32159	832	0	0
T7	418369	0	0	0
T8	56192	832	0	0
T9	13544	2505	0	0
T10	82696	832	0	0
T11	174372	0	0	0
T12	39977	832	0	0
T13	115981	832	0	0
T14	201073	2368	0	0
T15	0	3328	0	0
T17	0	15903	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	437598150	437463033	0	0
T1	1404	1308	0	0
T2	1589	1496	0	0
T3	2381	2317	0	0
T4	2169	2094	0	0
T5	45620	45537	0	0
T6	32159	32066	0	0
T7	418369	418274	0	0
T8	56192	56124	0	0
T9	13544	13477	0	0
T10	82696	82596	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437598150	437463033	0	0
T1	1404	1308	0	0
T2	1589	1496	0	0
T3	2381	2317	0	0
T4	2169	2094	0	0
T5	45620	45537	0	0
T6	32159	32066	0	0
T7	418369	418274	0	0
T8	56192	56124	0	0
T9	13544	13477	0	0
T10	82696	82596	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437598150	437463033	0	0
T1	1404	1308	0	0
T2	1589	1496	0	0
T3	2381	2317	0	0
T4	2169	2094	0	0
T5	45620	45537	0	0
T6	32159	32066	0	0
T7	418369	418274	0	0
T8	56192	56124	0	0
T9	13544	13477	0	0
T10	82696	82596	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437598150	437463033	0	0
T1	1404	1308	0	0
T2	1589	1496	0	0
T3	2381	2317	0	0
T4	2169	2094	0	0
T5	45620	45537	0	0
T6	32159	32066	0	0
T7	418369	418274	0	0
T8	56192	56124	0	0
T9	13544	13477	0	0
T10	82696	82596	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	437598150	184444	0	0
DataKnown_AKnownEnable	437598150	437463033	0	0
DepthKnown_A	437598150	437463033	0	0
RvalidKnown_A	437598150	437463033	0	0
WreadyKnown_A	437598150	437463033	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437598150	184444	0	0
T4	2169	16	0	0
T5	45620	0	0	0
T6	32159	0	0	0
T7	418369	0	0	0
T8	56192	0	0	0
T9	13544	0	0	0
T10	82696	0	0	0
T11	174372	688	0	0
T12	39977	0	0	0
T13	115981	0	0	0
T15	0	101	0	0
T17	0	627	0	0
T26	0	46	0	0
T28	0	856	0	0
T41	0	33	0	0
T42	0	926	0	0
T43	0	612	0	0
T44	0	672	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	437598150	437463033	0	0
T1	1404	1308	0	0
T2	1589	1496	0	0
T3	2381	2317	0	0
T4	2169	2094	0	0
T5	45620	45537	0	0
T6	32159	32066	0	0
T7	418369	418274	0	0
T8	56192	56124	0	0
T9	13544	13477	0	0
T10	82696	82596	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437598150	437463033	0	0
T1	1404	1308	0	0
T2	1589	1496	0	0
T3	2381	2317	0	0
T4	2169	2094	0	0
T5	45620	45537	0	0
T6	32159	32066	0	0
T7	418369	418274	0	0
T8	56192	56124	0	0
T9	13544	13477	0	0
T10	82696	82596	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437598150	437463033	0	0
T1	1404	1308	0	0
T2	1589	1496	0	0
T3	2381	2317	0	0
T4	2169	2094	0	0
T5	45620	45537	0	0
T6	32159	32066	0	0
T7	418369	418274	0	0
T8	56192	56124	0	0
T9	13544	13477	0	0
T10	82696	82596	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437598150	437463033	0	0
T1	1404	1308	0	0
T2	1589	1496	0	0
T3	2381	2317	0	0
T4	2169	2094	0	0
T5	45620	45537	0	0
T6	32159	32066	0	0
T7	418369	418274	0	0
T8	56192	56124	0	0
T9	13544	13477	0	0
T10	82696	82596	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	437598150	407841	0	0
DataKnown_AKnownEnable	437598150	437463033	0	0
DepthKnown_A	437598150	437463033	0	0
RvalidKnown_A	437598150	437463033	0	0
WreadyKnown_A	437598150	437463033	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437598150	407841	0	0
T4	2169	16	0	0
T5	45620	0	0	0
T6	32159	0	0	0
T7	418369	0	0	0
T8	56192	0	0	0
T9	13544	0	0	0
T10	82696	0	0	0
T11	174372	688	0	0
T12	39977	0	0	0
T13	115981	0	0	0
T15	0	101	0	0
T17	0	1959	0	0
T26	0	46	0	0
T28	0	856	0	0
T41	0	33	0	0
T42	0	926	0	0
T43	0	612	0	0
T44	0	672	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	437598150	437463033	0	0
T1	1404	1308	0	0
T2	1589	1496	0	0
T3	2381	2317	0	0
T4	2169	2094	0	0
T5	45620	45537	0	0
T6	32159	32066	0	0
T7	418369	418274	0	0
T8	56192	56124	0	0
T9	13544	13477	0	0
T10	82696	82596	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437598150	437463033	0	0
T1	1404	1308	0	0
T2	1589	1496	0	0
T3	2381	2317	0	0
T4	2169	2094	0	0
T5	45620	45537	0	0
T6	32159	32066	0	0
T7	418369	418274	0	0
T8	56192	56124	0	0
T9	13544	13477	0	0
T10	82696	82596	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437598150	437463033	0	0
T1	1404	1308	0	0
T2	1589	1496	0	0
T3	2381	2317	0	0
T4	2169	2094	0	0
T5	45620	45537	0	0
T6	32159	32066	0	0
T7	418369	418274	0	0
T8	56192	56124	0	0
T9	13544	13477	0	0
T10	82696	82596	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437598150	437463033	0	0
T1	1404	1308	0	0
T2	1589	1496	0	0
T3	2381	2317	0	0
T4	2169	2094	0	0
T5	45620	45537	0	0
T6	32159	32066	0	0
T7	418369	418274	0	0
T8	56192	56124	0	0
T9	13544	13477	0	0
T10	82696	82596	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	437598150	5959159	0	0
DataKnown_AKnownEnable	437598150	437463033	0	0
DepthKnown_A	437598150	437463033	0	0
RvalidKnown_A	437598150	437463033	0	0
WreadyKnown_A	437598150	437463033	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437598150	5959159	0	0
T1	1404	51	0	0
T2	1589	1	0	0
T3	2381	38	0	0
T4	2169	176	0	0
T5	45620	48	0	0
T6	32159	53	0	0
T7	418369	533	0	0
T8	56192	2378	0	0
T9	13544	62	0	0
T10	82696	190	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	437598150	437463033	0	0
T1	1404	1308	0	0
T2	1589	1496	0	0
T3	2381	2317	0	0
T4	2169	2094	0	0
T5	45620	45537	0	0
T6	32159	32066	0	0
T7	418369	418274	0	0
T8	56192	56124	0	0
T9	13544	13477	0	0
T10	82696	82596	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437598150	437463033	0	0
T1	1404	1308	0	0
T2	1589	1496	0	0
T3	2381	2317	0	0
T4	2169	2094	0	0
T5	45620	45537	0	0
T6	32159	32066	0	0
T7	418369	418274	0	0
T8	56192	56124	0	0
T9	13544	13477	0	0
T10	82696	82596	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437598150	437463033	0	0
T1	1404	1308	0	0
T2	1589	1496	0	0
T3	2381	2317	0	0
T4	2169	2094	0	0
T5	45620	45537	0	0
T6	32159	32066	0	0
T7	418369	418274	0	0
T8	56192	56124	0	0
T9	13544	13477	0	0
T10	82696	82596	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437598150	437463033	0	0
T1	1404	1308	0	0
T2	1589	1496	0	0
T3	2381	2317	0	0
T4	2169	2094	0	0
T5	45620	45537	0	0
T6	32159	32066	0	0
T7	418369	418274	0	0
T8	56192	56124	0	0
T9	13544	13477	0	0
T10	82696	82596	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	437598150	12761693	0	0
DataKnown_AKnownEnable	437598150	437463033	0	0
DepthKnown_A	437598150	437463033	0	0
RvalidKnown_A	437598150	437463033	0	0
WreadyKnown_A	437598150	437463033	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437598150	12761693	0	0
T1	1404	51	0	0
T2	1589	1	0	0
T3	2381	38	0	0
T4	2169	176	0	0
T5	45620	48	0	0
T6	32159	53	0	0
T7	418369	533	0	0
T8	56192	2378	0	0
T9	13544	209	0	0
T10	82696	831	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	437598150	437463033	0	0
T1	1404	1308	0	0
T2	1589	1496	0	0
T3	2381	2317	0	0
T4	2169	2094	0	0
T5	45620	45537	0	0
T6	32159	32066	0	0
T7	418369	418274	0	0
T8	56192	56124	0	0
T9	13544	13477	0	0
T10	82696	82596	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437598150	437463033	0	0
T1	1404	1308	0	0
T2	1589	1496	0	0
T3	2381	2317	0	0
T4	2169	2094	0	0
T5	45620	45537	0	0
T6	32159	32066	0	0
T7	418369	418274	0	0
T8	56192	56124	0	0
T9	13544	13477	0	0
T10	82696	82596	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437598150	437463033	0	0
T1	1404	1308	0	0
T2	1589	1496	0	0
T3	2381	2317	0	0
T4	2169	2094	0	0
T5	45620	45537	0	0
T6	32159	32066	0	0
T7	418369	418274	0	0
T8	56192	56124	0	0
T9	13544	13477	0	0
T10	82696	82596	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437598150	437463033	0	0
T1	1404	1308	0	0
T2	1589	1496	0	0
T3	2381	2317	0	0
T4	2169	2094	0	0
T5	45620	45537	0	0
T6	32159	32066	0	0
T7	418369	418274	0	0
T8	56192	56124	0	0
T9	13544	13477	0	0
T10	82696	82596	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0