Line Coverage for Module :
spi_readcmd
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 136 | 131 | 96.32 |
| CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 190 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 193 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 334 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 341 | 1 | 1 | 100.00 |
| ALWAYS | 354 | 4 | 4 | 100.00 |
| ALWAYS | 370 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 379 | 1 | 1 | 100.00 |
| ALWAYS | 382 | 12 | 12 | 100.00 |
| CONT_ASSIGN | 405 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 406 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 409 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 425 | 1 | 1 | 100.00 |
| ALWAYS | 428 | 3 | 3 | 100.00 |
| ALWAYS | 436 | 7 | 7 | 100.00 |
| ALWAYS | 457 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 466 | 1 | 1 | 100.00 |
| ALWAYS | 470 | 12 | 12 | 100.00 |
| CONT_ASSIGN | 497 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 498 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 502 | 1 | 1 | 100.00 |
| ALWAYS | 514 | 8 | 8 | 100.00 |
| CONT_ASSIGN | 530 | 1 | 1 | 100.00 |
| ALWAYS | 535 | 5 | 5 | 100.00 |
| ALWAYS | 553 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 566 | 1 | 1 | 100.00 |
| ALWAYS | 576 | 3 | 3 | 100.00 |
| ALWAYS | 584 | 48 | 43 | 89.58 |
| CONT_ASSIGN | 721 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 722 | 1 | 1 | 100.00 |
183 logic unused_p2s_sent ;
184 1/1 assign unused_p2s_sent = p2s_sent_i;
Tests: T1 T2 T3
185
186 sram_err_t unused_sram_rerr;
187 1/1 assign unused_sram_rerr = sram_m2l_i.rerror;
Tests: T1 T2 T3
188
189 logic unused_cmd_info_idx;
190 1/1 assign unused_cmd_info_idx = ^cmd_info_idx_i;
Tests: T1 T2 T3
191
192 logic unused_cmd_info_members;
193 1/1 assign unused_cmd_info_members = ^{
Tests: T1 T2 T3
194 cmd_info_i.valid, // cmdparse checks the valid bit
195 cmd_info_i.addr_swap_en, // address swap feature is used in Passthrough
196 cmd_info_i.opcode, // Does not need to check opcode. (fixed slot)
197 cmd_info_i.payload_dir, // Always output mode
198 cmd_info_i.payload_swap_en, // Used in passthrough mode only
199 cmd_info_i.read_pipeline_mode,
200 cmd_info_i.upload,
201 cmd_info_i.busy
202 };
203
204 `ASSERT(ValidCmdConfig_A,
205 main_st == MainAddress |-> (cmd_info_i.addr_mode != AddrDisabled)
206 && cmd_info_i.payload_dir == PayloadOut
207 && cmd_info_i.valid)
208
209 /////////////////
210 // Definitions //
211 /////////////////
212
213 // The expected FSM sequence for each command:
214 //
215 // - Read Data: Reset -> Address -> Output
216 // - Fast Read (Single/ Dual/ Quad): Reset -> Address -> Dummy -> Output
217 // - Fast Read Dual IO/ Quad IO: Reset -> Address -> MByte -> Dummy -> Output
218 // - Read SFDP: Reset -> Address -> Output
219 typedef enum logic [3:0] {
220 // Reset: Wait until the datapath for Read command is activated by cmdparse
221 // The cmd_info is valid after the 8th posedge of SCK.
222 MainReset,
223
224 // Address
225 //
226 // In this state, the FSM stacks incoming byte from s2p up to 3B or 4B
227 // based on the config by SW. When FSM moves from Reset to this state,
228 // it sets the IO mode to Single/ Dual/ Quad depending on the incoming
229 // SPI command.
230 //
231 // In this state, when it stacks addr[2] bit, which is 3rd from last in
232 // Single IO, 2nd from the last in Dual IO, and the last in Quad IO, it
233 // triggers Fetch State Machine to fetch data from Dual Port SRAM in
234 // SPI_DEVICE.
235 //
236 // For I/O commands, the state moves to MByte state.
237 // For Fast commands, the state moves to Dummy state.
238 // For Normal Read command, the state moves to Output state directly.
239 MainAddress,
240
241 // MByte
242 //
243 // IO commands (Dual I/O, Quad I/O) has M byte following Address. It is
244 // normally used for "continuous read" operation. This logic does not
245 // support the feature, so ignoring it then moves to Dummy state.
246 MainMByte,
247
248 // Dummy: Wait until it reaches dummy cycles, then moves to Output state
249 MainDummy,
250
251 // Output
252 //
253 // After passing the dummy cycle or skipping it for Normal Read command,
254 // The state drives SPI interface to send data. This state always assumes
255 // the data is ready in the sync fifo (see instance below). The Fetch
256 // Machine always prepares the data in advance up to designated level.
257 // The prefetch does not affect the watermark that SW has configured. The
258 // event occurs only when the byte is indeed sent through SPI lines.
259 //
260 // This state machine watches the sent address and raises an event if it
261 // exceeds the level. This feature is not turned on for Mailbox address.
262 MainOutput,
263
264 // Error: Wait until CSb deasserted
265 MainError
266 } main_st_e;
267 main_st_e main_st, main_st_d;
268
269 /////////////
270 // Signals //
271 /////////////
272
273 // Address mode in cmd_info
274 addr_mode_e cmdinfo_addr_mode;
275
276 // Address shift & latch
277 logic addr_ready_in_word, addr_ready_in_halfword;
278 logic addr_latched;
279 logic addr_shift_en;
280 logic addr_latch_en;
281 logic addr_inc; // increase address by 1 byte. Used to track the current addr
282 // Address size is latched when the state machine moves to the MainAddress
283 // state based on the cmd_info.addr_mode and addr_4b_en_i
284 logic [4:0] addr_cnt_d, addr_cnt_q;
285 logic addr_cnt_set; // no need to clear the counter
286 logic addr_latched_d;
287
288 logic [31:0] addr_q, addr_d;
289
290 // Read buffer access address.
291 //
292 // This differs from addr_q. addr_q is to maintain the SRAM access.
293 // readbuf_addr is to track the Read command address which does not fall
294 // into SFDP, Mailbox.
295 logic [31:0] readbuf_addr;
296 // Read Buffer update: addr_latch_en at the last addr beat & addr_inc
297 logic readbuf_update;
298 // When FSM is about to move to Output state, FSM triggers readbuf to operate.
299 logic readbuf_start;
300
301
302 // Dummy counter
303 logic dummycnt_eq_zero;
304 logic load_dummycnt;
305 logic [2:0] dummycnt;
306
307 // IO Mode selection
308
309 // SRAM signals
310 // Compare addr_d[SramAw-1:2] and mailbox_addr_i with mailbox_mask_i. If the
311 // value falls into mailbox, set this. Even this is set, it only uses when
312 // sram address is sent.
313 logic addr_d_in_mailbox, addr_q_in_mailbox;
314
315 logic [31:0] mailbox_masked_addr_d, mailbox_masked_addr_q;
316
317 // Double buffering signals
318 logic readbuf_idx; // 0 or 1
319 logic readbuf_flip; // if this is asserted, readbuf_idx flips.
320
321 // bit count within a word
322 logic bitcnt_update;
323 logic bitcnt_dec;
324 logic [2:0] bitcnt; // count down from 7 or partial for first unaligned
325
326 // FIFO
327 logic unused_fifo_rvalid, fifo_pop;
328 spi_byte_t fifo_rdata;
329
330 logic [7:0] p2s_byte;
331 logic p2s_valid_inclk;
332
333 logic sfdp_hit;
334 1/1 assign sfdp_hit = sel_dp_i == DpReadSFDP;
Tests: T1 T2 T3
335
336 // Events: watermark, flip
337 logic read_watermark, read_flip;
338
339 // SPI Mode
340 logic spid_in_flashmode;
341 1/1 assign spid_in_flashmode = (spi_mode_i == FlashMode);
Tests: T1 T2 T3
342
343 //////////////
344 // Datapath //
345 //////////////
346
347 // Address Shifting.
348 // the data comes from S2P module, which sends valid signal with spi_byte_t.
349 // So, if the logic sees `valid` only, it can't latch the exact word address.
350 // This logic latches in byte based until the 2nd last byte. Then merging
351 // the incoming byte (premature) to organize 4B address.
352
353 always_ff @(posedge clk_i or negedge rst_ni) begin
354 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
355 1/1 addr_q <= '0;
Tests: T1 T2 T3
356 1/1 end else if (addr_latch_en) begin
Tests: T5 T6 T8
357 1/1 addr_q <= addr_d;
Tests: T5 T8 T12
358 end
MISSING_ELSE
359 end
360
361 // readbuf_addr is visible to SW after CSb is de-asserted. (last_read_addr)
362 //
363 // It indicates the last byte address the host read.
364 // To precisely represent the last byte:
365 //
366 // - the logic does not latch address field (not yet read the byte)
367 // - the logic latches `addr_q` at the last beat. But compare `addr_q` to
368 // mailbox address.
369 always_ff @(posedge clk_i or negedge sys_rst_ni) begin
370 1/1 if (!sys_rst_ni) begin
Tests: T1 T2 T3
371 1/1 readbuf_addr <= '0;
Tests: T1 T2 T3
372 1/1 end else if ((main_st == MainOutput) && (sel_dp_i == DpReadCmd)
Tests: T3 T4 T5
373 && addr_latch_en && !(mailbox_en_i && addr_q_in_mailbox)
374 && spid_in_flashmode) begin
375 1/1 readbuf_addr <= addr_q;
Tests: T13 T14 T45
376 end
MISSING_ELSE
377 end
378
379 1/1 assign readbuf_address_o = readbuf_addr;
Tests: T1 T2 T3
380
381 always_comb begin
382 1/1 addr_d = addr_q; // default value. In 3B mode, upper most byte is 0
Tests: T1 T2 T3
383 1/1 addr_latch_en = 1'b0;
Tests: T1 T2 T3
384
385 1/1 if (addr_ready_in_word) begin
Tests: T1 T2 T3
386 // Return word based address, but should not latch
387 1/1 addr_d = {addr_q[23:0], s2p_byte_i[5:0], 2'b00};
Tests: T5 T8 T12
388 1/1 end else if (addr_ready_in_halfword) begin
Tests: T1 T2 T3
389 // When addr is a cycle earlier than full addr, sram req sent in
390 // spid_readsram
391 1/1 addr_d = {addr_q[23:0], s2p_byte_i[6:0], 1'b 0};
Tests: T5 T8 T12
392 1/1 end else if (addr_shift_en && s2p_valid_i) begin
Tests: T1 T2 T3
393 // Latch
394 1/1 addr_d = {addr_q[23:0], s2p_byte_i[7:0]};
Tests: T5 T8 T12
395 1/1 addr_latch_en = 1'b 1;
Tests: T5 T8 T12
396 1/1 end else if (addr_inc) begin
Tests: T1 T2 T3
397 // Increase the address to next
398 1/1 addr_d = addr_q[31:0] + 1'b1;
Tests: T5 T8 T12
399 1/1 addr_latch_en = 1'b 1;
Tests: T5 T8 T12
400 end
MISSING_ELSE
401 end
402
403 // BEGIN: Address Count =====================================================
404 // addr_cnt is to track the current shifted bit position in the address field
405 1/1 assign addr_ready_in_word = (addr_cnt_d == 5'd 2);
Tests: T1 T2 T3
406 1/1 assign addr_ready_in_halfword = (addr_cnt_d == 5'd 1);
Tests: T1 T2 T3
407
408 // addr_latched should be a pulse to be used in spid_readsram
409 1/1 assign addr_latched_d = (addr_cnt_d == 5'd 0);
Tests: T1 T2 T3
410
411 prim_edge_detector #(
412 .Width (1),
413 .ResetValue (1'b 0),
414 .EnSync (1'b 0)
415 ) u_addr_latch_pulse (
416 .clk_i,
417 .rst_ni,
418
419 .d_i (addr_latched_d),
420 .q_sync_o ( ),
421 .q_posedge_pulse_o (addr_latched ),
422 .q_negedge_pulse_o ( )
423 );
424
425 1/1 assign cmdinfo_addr_mode = get_addr_mode(cmd_info_i.addr_mode, addr_4b_en_i);
Tests: T1 T2 T3
426
427 always_ff @(posedge clk_i or negedge rst_ni) begin
428 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
429 1/1 addr_cnt_q <= '0;
Tests: T1 T2 T3
430 end else begin
431 1/1 addr_cnt_q <= addr_cnt_d;
Tests: T5 T6 T8
432 end
433 end
434
435 always_comb begin : addr_cnt
436 1/1 addr_cnt_d = addr_cnt_q;
Tests: T1 T2 T3
437 1/1 if (addr_cnt_set) begin
Tests: T1 T2 T3
438 // Set to the addr size based on cmd_info_i
439 // If addr_mode && addr_4b_en is Addr4B, then 32, if not, 24
440 // addr_cnt_d starts from the max -1. As addr_cnt_set is asserted when
441 // FSM moves from Reset to Address. At that time of the transition, the
442 // datapath should latch the Address[31] or Address[23] too. So, it
443 // already counts one beat.
444 1/1 addr_cnt_d = (cmdinfo_addr_mode == Addr4B) ? 5'd 31 : 5'd 23;
Tests: T5 T8 T12
445
446 1/1 end else if (addr_cnt_q == '0) begin
Tests: T1 T2 T3
447 1/1 addr_cnt_d = addr_cnt_q;
Tests: T1 T2 T3
448 1/1 end else if (addr_shift_en) begin
Tests: T5 T8 T12
449 // Stacking the address, decrease the address counter
450 1/1 addr_cnt_d = addr_cnt_q - 1'b 1;
Tests: T5 T8 T12
451 end
==> MISSING_ELSE
452 end
453 // END: Address Count -----------------------------------------------------
454
455 // Dummy Counter
456 always_ff @(posedge clk_i or negedge rst_ni) begin
457 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
458 1/1 dummycnt <= '0;
Tests: T1 T2 T3
459 1/1 end else if (load_dummycnt) begin
Tests: T5 T6 T8
460 // load quad_io
461 1/1 dummycnt <= cmd_info_i.dummy_size;
Tests: T5 T8 T12
462 1/1 end else if (!dummycnt_eq_zero) begin
Tests: T5 T6 T8
463 1/1 dummycnt <= dummycnt - 1'b 1;
Tests: T5 T8 T12
464 end
MISSING_ELSE
465 end
466 1/1 assign dummycnt_eq_zero = ~|dummycnt;
Tests: T1 T2 T3
467
468 // FIFO bit count
469 always_ff @(posedge clk_i or negedge rst_ni) begin
470 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
471 1/1 bitcnt <= '0;
Tests: T1 T2 T3
472 1/1 end else if (bitcnt_update) begin
Tests: T5 T6 T8
473 1/1 unique case (cmd_info_i.payload_en)
Tests: T5 T8 T12
474 1/1 4'b 0010: bitcnt <= 3'h 7;
Tests: T5 T8 T13
475 1/1 4'b 0011: bitcnt <= 3'h 6;
Tests: T12 T13 T15
476 1/1 4'b 1111: bitcnt <= 3'h 4;
Tests: T8 T12 T13
477 default: bitcnt <= 3'h 7;
478 endcase
479 1/1 end else if (bitcnt_dec) begin
Tests: T5 T6 T8
480 1/1 unique case (cmd_info_i.payload_en)
Tests: T5 T8 T12
481 1/1 4'b 0010: bitcnt <= bitcnt - 3'h 1;
Tests: T5 T8 T13
482 1/1 4'b 0011: bitcnt <= bitcnt - 3'h 2;
Tests: T12 T13 T15
483 1/1 4'b 1111: bitcnt <= bitcnt - 3'h 4;
Tests: T8 T12 T13
484 default: bitcnt <= bitcnt - 3'h 1;
485 endcase
486 end
MISSING_ELSE
487 end
488
489 //= BEGIN: SRAM Datapath ====================================================
490 // Main FSM trigger this datapath. This logic calculates the correct address
491
492 // Address conversion
493 // Convert into masked address
494 localparam int unsigned MailboxAw = $clog2(MailboxDepth);
495 localparam logic [31:0] MailboxMask = {{30-MailboxAw{1'b1}}, {2+MailboxAw{1'b0}}};
496
497 1/1 assign mailbox_masked_addr_d = addr_d & MailboxMask;
Tests: T1 T2 T3
498 1/1 assign mailbox_masked_addr_q = addr_q & MailboxMask;
Tests: T1 T2 T3
499
500 // Only valid when logic sends SRAM request
501 1/1 assign addr_d_in_mailbox = (mailbox_masked_addr_d == mailbox_addr_i);
Tests: T1 T2 T3
502 1/1 assign addr_q_in_mailbox = (mailbox_masked_addr_q == mailbox_addr_i);
Tests: T1 T2 T3
503
504 // internal addr is the address that the logic tracks.
505 // the first address comes from host system and then the internal logic
506 // manages the address to follow.
507
508 logic sram_req;
509
510 // Check if mailbox and intercept config, then raises mailbox_assumed.
511 // The signal shall be registered in SCK in.
512 // Then, spi_device top will latch to SCK out
513 always_ff @(posedge clk_i or negedge rst_ni) begin
514 2/2 if (!rst_ni) mailbox_assumed_o <= 1'b 0;
Tests: T1 T2 T3 | T1 T2 T3
515 1/1 else if (sram_req && mailbox_en_i && cfg_intercept_en_mbx_i
Tests: T5 T6 T8
516 && addr_d_in_mailbox) begin
517 1/1 mailbox_assumed_o <= 1'b 1;
Tests: T12 T15 T17
518 1/1 end else if (mailbox_en_i && cfg_intercept_en_mbx_i
Tests: T5 T6 T8
519 && addr_d_in_mailbox && (bitcnt == 3'h 0)) begin
520 // Keep checking if the next byte falls into the mailbox region
521 1/1 mailbox_assumed_o <= 1'b 1;
Tests: T12 T15 T17
522 1/1 end else if (!addr_d_in_mailbox && (bitcnt == 3'h 0)) begin
Tests: T5 T6 T8
523 // At every byte, Check the address goes out of mailbox region.
524 1/1 mailbox_assumed_o <= 1'b 0;
Tests: T5 T6 T8
525 end
MISSING_ELSE
526 end
527 //- END: SRAM Datapath ----------------------------------------------------
528
529 //= BEGIN: FIFO to P2S datapath =============================================
530 1/1 assign p2s_byte = fifo_rdata;
Tests: T5 T8 T12
531
532 // outclk latch
533 // can't put async fifo. DC constraint should have half clk datapath
534 always_ff @(posedge clk_out_i or negedge rst_out_ni) begin
535 1/1 if (!rst_out_ni) begin
Tests: T1 T2 T3
536 1/1 p2s_valid_o <= 1'b 0;
Tests: T1 T2 T3
537 1/1 p2s_byte_o <= '0 ;
Tests: T1 T2 T3
538 end else begin
539 1/1 p2s_valid_o <= p2s_valid_inclk;
Tests: T5 T6 T8
540 1/1 p2s_byte_o <= p2s_byte;
Tests: T5 T6 T8
541 end
542 end
543 //- END: FIFO to P2S datapath ---------------------------------------------
544
545 //= BEGIN: Double Buffering =================================================
546
547 // Readbuf Index:
548 //
549 // this signal is not reset by CSb. The value should be alive throughout the
550 // CSb event. (last_access_addr too)
551
552 always_ff @(posedge clk_i or negedge sys_rst_ni) begin
553 1/1 if (!sys_rst_ni) begin
Tests: T1 T2 T3
554 1/1 readbuf_idx <= 1'b 0;
Tests: T1 T2 T3
555 1/1 end else if (readbuf_flip) begin
Tests: T3 T4 T5
556 // readbuf_flip happens when the module completes the second to the last
557 // byte of a buffer through SPI. There will be a chance that will be
558 // cancelled by de-asserting CSb. This logic does not guarantee to cover
559 // that corner case. It expects to complete a byte transfer if it sends
560 // the first beat of the byte.
561 1/1 readbuf_idx <= ~readbuf_idx;
Tests: T5 T12 T13
562 end
MISSING_ELSE
563 end
564
565 // readbuf_flip
566 1/1 assign readbuf_flip = (main_st == MainOutput && addr_q[9:0] == '1);
Tests: T1 T2 T3
567
568 //- END: Double Buffering -------------------------------------------------
569
570 ///////////////////
571 // State Machine //
572 ///////////////////
573
574 //= BEGIN: Main state machine ===============================================
575 always_ff @(posedge clk_i or negedge rst_ni) begin
576 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
577 1/1 main_st <= MainReset;
Tests: T1 T2 T3
578 end else begin
579 1/1 main_st <= main_st_d;
Tests: T5 T6 T8
580 end
581 end
582
583 always_comb begin
584 1/1 main_st_d = main_st;
Tests: T1 T2 T3
585
586 1/1 load_dummycnt = 1'b 0;
Tests: T1 T2 T3
587
588 // address control
589 1/1 addr_cnt_set = 1'b 0;
Tests: T1 T2 T3
590 1/1 addr_inc = 1'b 0;
Tests: T1 T2 T3
591 1/1 sram_req = 1'b 0;
Tests: T1 T2 T3
592 1/1 addr_shift_en = 1'b 0;
Tests: T1 T2 T3
593
594 1/1 p2s_valid_inclk = 1'b 0;
Tests: T1 T2 T3
595 1/1 fifo_pop = 1'b 0;
Tests: T1 T2 T3
596
597 1/1 bitcnt_update = 1'b 0;
Tests: T1 T2 T3
598 1/1 bitcnt_dec = 1'b 0;
Tests: T1 T2 T3
599
600 1/1 io_mode_o = SingleIO;
Tests: T1 T2 T3
601
602 1/1 readbuf_start = 1'b 0;
Tests: T1 T2 T3
603 1/1 readbuf_update = 1'b 0;
Tests: T1 T2 T3
604
605 1/1 unique case (main_st)
Tests: T1 T2 T3
606 MainReset: begin
607 1/1 if (sel_dp_i inside {DpReadCmd, DpReadSFDP}) begin
Tests: T1 T2 T3
608 // Any readcommand goes to MainAddress state to latch address
609 // 3B, 4B handles inside address
610 1/1 main_st_d = MainAddress;
Tests: T5 T8 T12
611
612 1/1 addr_cnt_set = 1'b 1;
Tests: T5 T8 T12
613 end
MISSING_ELSE
614 end
615
616 MainAddress: begin
617 1/1 addr_shift_en = 1'b 1;
Tests: T5 T8 T12
618
619 1/1 if (addr_ready_in_word) begin
Tests: T5 T8 T12
620 1/1 sram_req = 1'b 1;
Tests: T5 T8 T12
621 end
MISSING_ELSE
622
623 1/1 if (addr_latched) begin
Tests: T5 T8 T12
624 // update bitcnt. If input address is not word aligned, bitcnt
625 // could be 23, 15, or 7
626 1/1 bitcnt_update = 1'b 1;
Tests: T5 T8 T12
627
628 // Next state:
629 // MByte if mbyte enabled
630 // Dummy if mbyte = 0 and dummy_en = 1
631 // Output if mbyte = 0 and dummy_en = 0
632 1/1 unique casez ({cmd_info_i.mbyte_en, cmd_info_i.dummy_en})
Tests: T5 T8 T12
633 2'b 00: begin
634 // Moves to Output directly
635 1/1 main_st_d = MainOutput;
Tests: T13 T15 T17
636 1/1 readbuf_start = 1'b 1;
Tests: T13 T15 T17
637 1/1 readbuf_update = 1'b 1;
Tests: T13 T15 T17
638 end
639
640 2'b 01: begin
641 // Dummy Enabled
642 1/1 main_st_d = MainDummy;
Tests: T5 T8 T12
643
644 1/1 load_dummycnt = 1'b 1;
Tests: T5 T8 T12
645 end
646
647 2'b 1?: begin
648 // Regardless of Dummy
649 0/1 ==> main_st_d = MainMByte;
650 end
651
652 default: begin
653 main_st_d = MainError;
654 end
655 endcase
656 end
MISSING_ELSE
657 end
658
659 MainMByte: begin
660 0/1 ==> if (s2p_valid_i) begin
661 0/1 ==> main_st_d = MainDummy;
662
663 0/1 ==> load_dummycnt = 1'b 1;
664 end
==> MISSING_ELSE
665 end
666
667 MainDummy: begin
668 1/1 if (dummycnt_eq_zero) begin
Tests: T5 T8 T12
669 1/1 main_st_d = MainOutput;
Tests: T5 T8 T12
670 1/1 readbuf_start = 1'b 1;
Tests: T5 T8 T12
671 1/1 readbuf_update = 1'b 1;
Tests: T5 T8 T12
672 end
MISSING_ELSE
673 end
674
675 MainOutput: begin
676 1/1 bitcnt_dec = 1'b 1;
Tests: T5 T8 T12
677
678 // Note: p2s accepts the byte and latch inside at the first beat.
679 // So, it is safe to change the data at the next cycle.
680 1/1 p2s_valid_inclk = 1'b 1;
Tests: T5 T8 T12
681
682 // DeadEnd until CSb deasserted
683 // Change Mode based on the payload_en[3:0]
684 // Return data from FIFO
685 1/1 unique case (cmd_info_i.payload_en)
Tests: T5 T8 T12
686 1/1 4'b 0010: io_mode_o = SingleIO;
Tests: T5 T8 T13
687 1/1 4'b 0011: io_mode_o = DualIO;
Tests: T12 T13 T15
688 1/1 4'b 1111: io_mode_o = QuadIO;
Tests: T8 T12 T13
689 default: io_mode_o = SingleIO;
690 endcase
691
692 1/1 if (bitcnt == 3'h 0) begin
Tests: T5 T8 T12
693 // Increase addr by 1 byte
694 1/1 addr_inc = 1'b 1;
Tests: T5 T8 T12
695
696 // When address is begin updated, ask readbuf to update the state too
697 1/1 readbuf_update = 1'b 1;
Tests: T5 T8 T12
698
699 // sent all words
700 1/1 bitcnt_update = 1'b 1;
Tests: T5 T8 T12
701 1/1 fifo_pop = 1'b 1;
Tests: T5 T8 T12
702 end
MISSING_ELSE
703 end
704
705 MainError: begin
706 0/1 ==> main_st_d = MainError;
707 end
708
709 default: begin
710 main_st_d = MainReset;
711 end
712 endcase
713 end
714 //- END: Main state machine -----------------------------------------------
715
716 // Events: register
717 // watermark, flip are pulse signals. watermark pulse width is 1 SCK.
718 // flip pulse width varies inside readbuffer and changed into 1 SCK width.
719 // They are not registered (output of comb logic).
720 // As these signals goes into prim_pulse_sync, no need to register here.
721 1/1 assign sck_read_watermark_o = read_watermark;
Tests: T1 T2 T3
722 1/1 assign sck_read_flip_o = read_flip;
Tests: T1 T2 T3
Cond Coverage for Module :
spi_readcmd
| Total | Covered | Percent |
|---|
| Conditions | 66 | 66 | 100.00 |
| Logical | 66 | 66 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 334
EXPRESSION (sel_dp_i == DpReadSFDP)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T15,T17,T46 |
LINE 341
EXPRESSION (spi_mode_i == FlashMode)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 372
EXPRESSION ((main_st == MainOutput) && (sel_dp_i == DpReadCmd) && addr_latch_en && ( ! (mailbox_en_i && addr_q_in_mailbox) ) && spid_in_flashmode)
-----------1----------- -----------2----------- ------3------ --------------------4-------------------- --------5--------
| -1- | -2- | -3- | -4- | -5- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | 1 | Covered | T13,T14,T17 |
| 1 | 0 | 1 | 1 | 1 | Covered | T17,T43,T39 |
| 1 | 1 | 0 | 1 | 1 | Covered | T13,T14,T45 |
| 1 | 1 | 1 | 0 | 1 | Covered | T17,T48,T43 |
| 1 | 1 | 1 | 1 | 0 | Covered | T5,T8,T12 |
| 1 | 1 | 1 | 1 | 1 | Covered | T13,T14,T45 |
LINE 372
SUB-EXPRESSION (main_st == MainOutput)
-----------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T3,T4,T5 |
| 1 | Covered | T5,T8,T12 |
LINE 372
SUB-EXPRESSION (sel_dp_i == DpReadCmd)
-----------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T3,T4,T5 |
| 1 | Covered | T5,T8,T12 |
LINE 372
SUB-EXPRESSION ( ! (mailbox_en_i && addr_q_in_mailbox) )
-----------------1-----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T3,T4,T5 |
| 1 | Covered | T12,T15,T17 |
LINE 372
SUB-EXPRESSION (mailbox_en_i && addr_q_in_mailbox)
------1----- --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T3,T4,T7 |
| 1 | 0 | Covered | T6,T9,T10 |
| 1 | 1 | Covered | T12,T15,T17 |
LINE 392
EXPRESSION (addr_shift_en && s2p_valid_i)
------1------ -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T5,T6,T8 |
| 1 | 0 | Covered | T5,T8,T12 |
| 1 | 1 | Covered | T5,T8,T12 |
LINE 405
EXPRESSION (addr_cnt_d == 5'd2)
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T5,T8,T12 |
LINE 406
EXPRESSION (addr_cnt_d == 5'b1)
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T5,T8,T12 |
LINE 409
EXPRESSION (addr_cnt_d == 5'b0)
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 444
EXPRESSION ((cmdinfo_addr_mode == Addr4B) ? 5'd31 : 5'd23)
--------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T5,T8,T12 |
| 1 | Covered | T8,T12,T13 |
LINE 444
SUB-EXPRESSION (cmdinfo_addr_mode == Addr4B)
--------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T5,T8,T12 |
| 1 | Covered | T8,T12,T13 |
LINE 446
EXPRESSION (addr_cnt_q == '0)
---------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T5,T8,T12 |
| 1 | Covered | T1,T2,T3 |
LINE 501
EXPRESSION (mailbox_masked_addr_d == mailbox_addr_i)
--------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 502
EXPRESSION (mailbox_masked_addr_q == mailbox_addr_i)
--------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 515
EXPRESSION (sram_req && mailbox_en_i && cfg_intercept_en_mbx_i && addr_d_in_mailbox)
----1--- ------2----- -----------3---------- --------4--------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T12,T15,T17 |
| 1 | 0 | 1 | 1 | Covered | T15,T40,T53 |
| 1 | 1 | 0 | 1 | Covered | T35,T51,T43 |
| 1 | 1 | 1 | 0 | Covered | T12,T13,T15 |
| 1 | 1 | 1 | 1 | Covered | T12,T15,T17 |
LINE 518
EXPRESSION (mailbox_en_i && cfg_intercept_en_mbx_i && addr_d_in_mailbox && (bitcnt == 3'b0))
------1----- -----------2---------- --------3-------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T15,T40,T30 |
| 1 | 0 | 1 | 1 | Covered | T35,T51,T43 |
| 1 | 1 | 0 | 1 | Covered | T9,T12,T13 |
| 1 | 1 | 1 | 0 | Covered | T12,T15,T17 |
| 1 | 1 | 1 | 1 | Covered | T12,T15,T17 |
LINE 518
SUB-EXPRESSION (bitcnt == 3'b0)
--------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T5,T8,T12 |
| 1 | Covered | T5,T6,T8 |
LINE 522
EXPRESSION (((!addr_d_in_mailbox)) && (bitcnt == 3'b0))
-----------1---------- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T8,T15,T34 |
| 1 | 0 | Covered | T5,T12,T13 |
| 1 | 1 | Covered | T5,T6,T8 |
LINE 522
SUB-EXPRESSION (bitcnt == 3'b0)
--------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T5,T8,T12 |
| 1 | Covered | T5,T6,T8 |
LINE 566
EXPRESSION ((main_st == MainOutput) && (addr_q[9:0] == '1))
-----------1----------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T13,T45,T78 |
| 1 | 0 | Covered | T5,T8,T12 |
| 1 | 1 | Covered | T5,T12,T13 |
LINE 566
SUB-EXPRESSION (main_st == MainOutput)
-----------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T5,T8,T12 |
LINE 566
SUB-EXPRESSION (addr_q[9:0] == '1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T5,T12,T13 |
LINE 692
EXPRESSION (bitcnt == 3'b0)
--------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T5,T8,T12 |
| 1 | Covered | T5,T8,T12 |
LINE 735
EXPRESSION (sel_dp_i == DpReadSFDP)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T15,T17,T46 |
FSM Coverage for Module :
spi_readcmd
Summary for FSM :: main_st
| Total | Covered | Percent | |
| States |
5 |
4 |
80.00 |
(Not included in score) |
| Transitions |
5 |
4 |
80.00 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: main_st
| | | |
| MainAddress |
610 |
Covered |
T5,T8,T12 |
| MainDummy |
642 |
Covered |
T5,T8,T12 |
| MainError |
653 |
Not Covered |
|
| MainMByte |
649 |
Excluded |
|
| MainOutput |
635 |
Covered |
T5,T8,T12 |
| MainReset |
606 |
Covered |
T1,T2,T3 |
| | | |
| MainAddress->MainDummy |
642 |
Covered |
T5,T8,T12 |
| MainAddress->MainError |
653 |
Not Covered |
|
| MainAddress->MainMByte |
649 |
Excluded |
|
| MainAddress->MainOutput |
635 |
Covered |
T13,T15,T17 |
| MainDummy->MainOutput |
669 |
Covered |
T5,T8,T12 |
| MainMByte->MainDummy |
661 |
Excluded |
|
| MainReset->MainAddress |
610 |
Covered |
T5,T8,T12 |
Branch Coverage for Module :
spi_readcmd
| Line No. | Total | Covered | Percent |
| Branches |
|
65 |
55 |
84.62 |
| IF |
354 |
3 |
3 |
100.00 |
| IF |
370 |
3 |
3 |
100.00 |
| IF |
385 |
5 |
5 |
100.00 |
| IF |
428 |
2 |
2 |
100.00 |
| IF |
437 |
5 |
4 |
80.00 |
| IF |
457 |
4 |
4 |
100.00 |
| IF |
470 |
10 |
8 |
80.00 |
| IF |
514 |
5 |
5 |
100.00 |
| IF |
535 |
2 |
2 |
100.00 |
| IF |
553 |
3 |
3 |
100.00 |
| IF |
576 |
2 |
2 |
100.00 |
| CASE |
605 |
21 |
14 |
66.67 |
354 if (!rst_ni) begin
-1-
355 addr_q <= '0;
==>
356 end else if (addr_latch_en) begin
-2-
357 addr_q <= addr_d;
==>
358 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T5,T8,T12 |
| 0 |
0 |
Covered |
T5,T6,T8 |
370 if (!sys_rst_ni) begin
-1-
371 readbuf_addr <= '0;
==>
372 end else if ((main_st == MainOutput) && (sel_dp_i == DpReadCmd)
-2-
373 && addr_latch_en && !(mailbox_en_i && addr_q_in_mailbox)
374 && spid_in_flashmode) begin
375 readbuf_addr <= addr_q;
==>
376 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T13,T14,T45 |
| 0 |
0 |
Covered |
T3,T4,T5 |
385 if (addr_ready_in_word) begin
-1-
386 // Return word based address, but should not latch
387 addr_d = {addr_q[23:0], s2p_byte_i[5:0], 2'b00};
==>
388 end else if (addr_ready_in_halfword) begin
-2-
389 // When addr is a cycle earlier than full addr, sram req sent in
390 // spid_readsram
391 addr_d = {addr_q[23:0], s2p_byte_i[6:0], 1'b 0};
==>
392 end else if (addr_shift_en && s2p_valid_i) begin
-3-
393 // Latch
394 addr_d = {addr_q[23:0], s2p_byte_i[7:0]};
==>
395 addr_latch_en = 1'b 1;
396 end else if (addr_inc) begin
-4-
397 // Increase the address to next
398 addr_d = addr_q[31:0] + 1'b1;
==>
399 addr_latch_en = 1'b 1;
400 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | -4- | Status | Tests |
| 1 |
- |
- |
- |
Covered |
T5,T8,T12 |
| 0 |
1 |
- |
- |
Covered |
T5,T8,T12 |
| 0 |
0 |
1 |
- |
Covered |
T5,T8,T12 |
| 0 |
0 |
0 |
1 |
Covered |
T5,T8,T12 |
| 0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
428 if (!rst_ni) begin
-1-
429 addr_cnt_q <= '0;
==>
430 end else begin
431 addr_cnt_q <= addr_cnt_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T5,T6,T8 |
437 if (addr_cnt_set) begin
-1-
438 // Set to the addr size based on cmd_info_i
439 // If addr_mode && addr_4b_en is Addr4B, then 32, if not, 24
440 // addr_cnt_d starts from the max -1. As addr_cnt_set is asserted when
441 // FSM moves from Reset to Address. At that time of the transition, the
442 // datapath should latch the Address[31] or Address[23] too. So, it
443 // already counts one beat.
444 addr_cnt_d = (cmdinfo_addr_mode == Addr4B) ? 5'd 31 : 5'd 23;
-2-
==>
==>
445
446 end else if (addr_cnt_q == '0) begin
-3-
447 addr_cnt_d = addr_cnt_q;
==>
448 end else if (addr_shift_en) begin
-4-
449 // Stacking the address, decrease the address counter
450 addr_cnt_d = addr_cnt_q - 1'b 1;
==>
451 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | -4- | Status | Tests |
| 1 |
1 |
- |
- |
Covered |
T8,T12,T13 |
| 1 |
0 |
- |
- |
Covered |
T5,T8,T12 |
| 0 |
- |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
- |
0 |
1 |
Covered |
T5,T8,T12 |
| 0 |
- |
0 |
0 |
Not Covered |
|
457 if (!rst_ni) begin
-1-
458 dummycnt <= '0;
==>
459 end else if (load_dummycnt) begin
-2-
460 // load quad_io
461 dummycnt <= cmd_info_i.dummy_size;
==>
462 end else if (!dummycnt_eq_zero) begin
-3-
463 dummycnt <= dummycnt - 1'b 1;
==>
464 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T5,T8,T12 |
| 0 |
0 |
1 |
Covered |
T5,T8,T12 |
| 0 |
0 |
0 |
Covered |
T5,T6,T8 |
470 if (!rst_ni) begin
-1-
471 bitcnt <= '0;
==>
472 end else if (bitcnt_update) begin
-2-
473 unique case (cmd_info_i.payload_en)
-3-
474 4'b 0010: bitcnt <= 3'h 7;
==>
475 4'b 0011: bitcnt <= 3'h 6;
==>
476 4'b 1111: bitcnt <= 3'h 4;
==>
477 default: bitcnt <= 3'h 7;
==>
478 endcase
479 end else if (bitcnt_dec) begin
-4-
480 unique case (cmd_info_i.payload_en)
-5-
481 4'b 0010: bitcnt <= bitcnt - 3'h 1;
==>
482 4'b 0011: bitcnt <= bitcnt - 3'h 2;
==>
483 4'b 1111: bitcnt <= bitcnt - 3'h 4;
==>
484 default: bitcnt <= bitcnt - 3'h 1;
==>
485 endcase
486 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | Status | Tests |
| 1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
4'b0010 |
- |
- |
Covered |
T5,T8,T13 |
| 0 |
1 |
4'b0011 |
- |
- |
Covered |
T12,T13,T15 |
| 0 |
1 |
4'b1111 |
- |
- |
Covered |
T8,T12,T13 |
| 0 |
1 |
default |
- |
- |
Not Covered |
|
| 0 |
0 |
- |
1 |
4'b0010 |
Covered |
T5,T8,T13 |
| 0 |
0 |
- |
1 |
4'b0011 |
Covered |
T12,T13,T15 |
| 0 |
0 |
- |
1 |
4'b1111 |
Covered |
T8,T12,T13 |
| 0 |
0 |
- |
1 |
default |
Not Covered |
|
| 0 |
0 |
- |
0 |
- |
Covered |
T5,T6,T8 |
514 if (!rst_ni) mailbox_assumed_o <= 1'b 0;
-1-
==>
515 else if (sram_req && mailbox_en_i && cfg_intercept_en_mbx_i
-2-
516 && addr_d_in_mailbox) begin
517 mailbox_assumed_o <= 1'b 1;
==>
518 end else if (mailbox_en_i && cfg_intercept_en_mbx_i
-3-
519 && addr_d_in_mailbox && (bitcnt == 3'h 0)) begin
520 // Keep checking if the next byte falls into the mailbox region
521 mailbox_assumed_o <= 1'b 1;
==>
522 end else if (!addr_d_in_mailbox && (bitcnt == 3'h 0)) begin
-4-
523 // At every byte, Check the address goes out of mailbox region.
524 mailbox_assumed_o <= 1'b 0;
==>
525 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | -4- | Status | Tests |
| 1 |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
- |
Covered |
T12,T15,T17 |
| 0 |
0 |
1 |
- |
Covered |
T12,T15,T17 |
| 0 |
0 |
0 |
1 |
Covered |
T5,T6,T8 |
| 0 |
0 |
0 |
0 |
Covered |
T5,T8,T12 |
535 if (!rst_out_ni) begin
-1-
536 p2s_valid_o <= 1'b 0;
==>
537 p2s_byte_o <= '0 ;
538 end else begin
539 p2s_valid_o <= p2s_valid_inclk;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T5,T6,T8 |
553 if (!sys_rst_ni) begin
-1-
554 readbuf_idx <= 1'b 0;
==>
555 end else if (readbuf_flip) begin
-2-
556 // readbuf_flip happens when the module completes the second to the last
557 // byte of a buffer through SPI. There will be a chance that will be
558 // cancelled by de-asserting CSb. This logic does not guarantee to cover
559 // that corner case. It expects to complete a byte transfer if it sends
560 // the first beat of the byte.
561 readbuf_idx <= ~readbuf_idx;
==>
562 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T5,T12,T13 |
| 0 |
0 |
Covered |
T3,T4,T5 |
576 if (!rst_ni) begin
-1-
577 main_st <= MainReset;
==>
578 end else begin
579 main_st <= main_st_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T5,T6,T8 |
605 unique case (main_st)
-1-
606 MainReset: begin
607 if (sel_dp_i inside {DpReadCmd, DpReadSFDP}) begin
-2-
608 // Any readcommand goes to MainAddress state to latch address
609 // 3B, 4B handles inside address
610 main_st_d = MainAddress;
==>
611
612 addr_cnt_set = 1'b 1;
613 end
MISSING_ELSE
==>
614 end
615
616 MainAddress: begin
617 addr_shift_en = 1'b 1;
618
619 if (addr_ready_in_word) begin
-3-
620 sram_req = 1'b 1;
==>
621 end
MISSING_ELSE
==>
622
623 if (addr_latched) begin
-4-
624 // update bitcnt. If input address is not word aligned, bitcnt
625 // could be 23, 15, or 7
626 bitcnt_update = 1'b 1;
627
628 // Next state:
629 // MByte if mbyte enabled
630 // Dummy if mbyte = 0 and dummy_en = 1
631 // Output if mbyte = 0 and dummy_en = 0
632 unique casez ({cmd_info_i.mbyte_en, cmd_info_i.dummy_en})
-5-
633 2'b 00: begin
634 // Moves to Output directly
635 main_st_d = MainOutput;
==>
636 readbuf_start = 1'b 1;
637 readbuf_update = 1'b 1;
638 end
639
640 2'b 01: begin
641 // Dummy Enabled
642 main_st_d = MainDummy;
==>
643
644 load_dummycnt = 1'b 1;
645 end
646
647 2'b 1?: begin
648 // Regardless of Dummy
649 main_st_d = MainMByte;
==>
650 end
651
652 default: begin
653 main_st_d = MainError;
==>
654 end
655 endcase
656 end
MISSING_ELSE
==>
657 end
658
659 MainMByte: begin
660 if (s2p_valid_i) begin
-6-
661 main_st_d = MainDummy;
==>
662
663 load_dummycnt = 1'b 1;
664 end
MISSING_ELSE
==>
665 end
666
667 MainDummy: begin
668 if (dummycnt_eq_zero) begin
-7-
669 main_st_d = MainOutput;
==>
670 readbuf_start = 1'b 1;
671 readbuf_update = 1'b 1;
672 end
MISSING_ELSE
==>
673 end
674
675 MainOutput: begin
676 bitcnt_dec = 1'b 1;
677
678 // Note: p2s accepts the byte and latch inside at the first beat.
679 // So, it is safe to change the data at the next cycle.
680 p2s_valid_inclk = 1'b 1;
681
682 // DeadEnd until CSb deasserted
683 // Change Mode based on the payload_en[3:0]
684 // Return data from FIFO
685 unique case (cmd_info_i.payload_en)
-8-
686 4'b 0010: io_mode_o = SingleIO;
==>
687 4'b 0011: io_mode_o = DualIO;
==>
688 4'b 1111: io_mode_o = QuadIO;
==>
689 default: io_mode_o = SingleIO;
==>
690 endcase
691
692 if (bitcnt == 3'h 0) begin
-9-
693 // Increase addr by 1 byte
694 addr_inc = 1'b 1;
==>
695
696 // When address is begin updated, ask readbuf to update the state too
697 readbuf_update = 1'b 1;
698
699 // sent all words
700 bitcnt_update = 1'b 1;
701 fifo_pop = 1'b 1;
702 end
MISSING_ELSE
==>
703 end
704
705 MainError: begin
706 main_st_d = MainError;
==>
707 end
708
709 default: begin
710 main_st_d = MainReset;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | Status | Tests |
| MainReset |
1 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T5,T8,T12 |
| MainReset |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| MainAddress |
- |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T5,T8,T12 |
| MainAddress |
- |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T5,T8,T12 |
| MainAddress |
- |
- |
1 |
2'b00 |
- |
- |
- |
- |
Covered |
T13,T15,T17 |
| MainAddress |
- |
- |
1 |
2'b01 |
- |
- |
- |
- |
Covered |
T5,T8,T12 |
| MainAddress |
- |
- |
1 |
2'b1z |
- |
- |
- |
- |
Not Covered |
|
| MainAddress |
- |
- |
1 |
default |
- |
- |
- |
- |
Not Covered |
|
| MainAddress |
- |
- |
0 |
- |
- |
- |
- |
- |
Covered |
T5,T8,T12 |
| MainMByte |
- |
- |
- |
- |
1 |
- |
- |
- |
Not Covered |
|
| MainMByte |
- |
- |
- |
- |
0 |
- |
- |
- |
Not Covered |
|
| MainDummy |
- |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T5,T8,T12 |
| MainDummy |
- |
- |
- |
- |
- |
0 |
- |
- |
Covered |
T5,T8,T12 |
| MainOutput |
- |
- |
- |
- |
- |
- |
4'b0010 |
- |
Covered |
T5,T8,T13 |
| MainOutput |
- |
- |
- |
- |
- |
- |
4'b0011 |
- |
Covered |
T12,T13,T15 |
| MainOutput |
- |
- |
- |
- |
- |
- |
4'b1111 |
- |
Covered |
T8,T12,T13 |
| MainOutput |
- |
- |
- |
- |
- |
- |
default |
- |
Not Covered |
|
| MainOutput |
- |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T5,T8,T12 |
| MainOutput |
- |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T5,T8,T12 |
| MainError |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
| default |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
Assert Coverage for Module :
spi_readcmd
Assertion Details
AddrIncNotAssertInAddressState_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
151598662 |
4657245 |
0 |
0 |
| T5 |
21392 |
2398 |
0 |
0 |
| T6 |
25052 |
0 |
0 |
0 |
| T7 |
60348 |
0 |
0 |
0 |
| T8 |
26567 |
3072 |
0 |
0 |
| T9 |
2080 |
0 |
0 |
0 |
| T10 |
15126 |
0 |
0 |
0 |
| T11 |
213533 |
0 |
0 |
0 |
| T12 |
144616 |
11654 |
0 |
0 |
| T13 |
16133 |
3798 |
0 |
0 |
| T14 |
65873 |
6225 |
0 |
0 |
| T15 |
0 |
12759 |
0 |
0 |
| T17 |
0 |
3581 |
0 |
0 |
| T34 |
0 |
1630 |
0 |
0 |
| T35 |
0 |
1024 |
0 |
0 |
| T36 |
0 |
10 |
0 |
0 |
MailboxSizeMatch_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
151598662 |
121225703 |
0 |
0 |
| T5 |
21392 |
21392 |
0 |
0 |
| T6 |
25052 |
24592 |
0 |
0 |
| T7 |
60348 |
0 |
0 |
0 |
| T8 |
26567 |
26490 |
0 |
0 |
| T9 |
2080 |
2080 |
0 |
0 |
| T10 |
15126 |
15126 |
0 |
0 |
| T11 |
213533 |
0 |
0 |
0 |
| T12 |
144616 |
144500 |
0 |
0 |
| T13 |
16133 |
16133 |
0 |
0 |
| T14 |
65873 |
65873 |
0 |
0 |
| T15 |
0 |
248469 |
0 |
0 |
| T17 |
0 |
247197 |
0 |
0 |
ValidCmdConfig_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
151598662 |
213991 |
0 |
0 |
| T5 |
21392 |
46 |
0 |
0 |
| T6 |
25052 |
0 |
0 |
0 |
| T7 |
60348 |
0 |
0 |
0 |
| T8 |
26567 |
246 |
0 |
0 |
| T9 |
2080 |
0 |
0 |
0 |
| T10 |
15126 |
0 |
0 |
0 |
| T11 |
213533 |
0 |
0 |
0 |
| T12 |
144616 |
292 |
0 |
0 |
| T13 |
16133 |
224 |
0 |
0 |
| T14 |
65873 |
77 |
0 |
0 |
| T15 |
0 |
555 |
0 |
0 |
| T17 |
0 |
408 |
0 |
0 |
| T34 |
0 |
186 |
0 |
0 |
| T35 |
0 |
46 |
0 |
0 |
| T36 |
0 |
46 |
0 |
0 |