Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3889460	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4396534

1

T2

1

T4

15

T5

29

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4615695	1			T1	1		T2	1		T3	67
values[0x0]	1835205	1			T4	13		T5	10		T6	4
values[0x1]	1835094	1			T4	6		T5	12		T6	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2750492	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5535502

1

T2

1

T3

22

T4

16

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	33416	1			T13	1		T16	7		T26	21
valid_sources[0x01]	31479	1			T5	2		T15	1		T16	6
valid_sources[0x02]	33860	1			T5	3		T15	4		T16	3
valid_sources[0x03]	33078	1			T5	4		T16	2		T26	19
valid_sources[0x04]	30400	1			T5	3		T15	5		T16	2
valid_sources[0x05]	30367	1			T5	2		T17	15		T26	25
valid_sources[0x06]	30836	1			T5	9		T15	2		T16	5
valid_sources[0x07]	30838	1			T4	1		T5	4		T15	4
valid_sources[0x08]	30864	1			T5	1		T15	6		T16	3
valid_sources[0x09]	38498	1			T3	2		T5	8		T16	3
valid_sources[0x0a]	31673	1			T5	1		T13	1		T15	16
valid_sources[0x0b]	32103	1			T4	1		T15	2		T16	10
valid_sources[0x0c]	29556	1			T15	2		T16	5		T17	16
valid_sources[0x0d]	55784	1			T5	7		T16	1		T26	11
valid_sources[0x0e]	32281	1			T3	1		T15	3		T16	4
valid_sources[0x0f]	37092	1			T15	1		T16	3		T17	1
valid_sources[0x10]	31044	1			T5	19		T15	6		T17	1
valid_sources[0x11]	31373	1			T3	4		T15	2		T26	14
valid_sources[0x12]	36460	1			T5	4		T15	1		T16	1
valid_sources[0x13]	33818	1			T5	3		T15	3		T16	3
valid_sources[0x14]	30752	1			T5	4		T15	2		T16	2
valid_sources[0x15]	30861	1			T5	2		T16	10		T17	3
valid_sources[0x16]	29998	1			T15	8		T16	9		T17	5
valid_sources[0x17]	29151	1			T5	1		T15	3		T16	5
valid_sources[0x18]	29987	1			T5	1		T15	3		T16	1
valid_sources[0x19]	31549	1			T5	3		T15	16		T16	2
valid_sources[0x1a]	41833	1			T5	3		T15	7		T16	2
valid_sources[0x1b]	29896	1			T5	3		T15	1		T16	13
valid_sources[0x1c]	33848	1			T16	15		T26	10		T22	27
valid_sources[0x1d]	31400	1			T15	4		T16	4		T26	15
valid_sources[0x1e]	29622	1			T5	1		T15	6		T16	6
valid_sources[0x1f]	33019	1			T5	5		T15	4		T16	5
valid_sources[0x20]	33269	1			T5	2		T16	1		T26	24
valid_sources[0x21]	31193	1			T3	4		T5	2		T15	2
valid_sources[0x22]	30044	1			T5	2		T16	8		T26	15
valid_sources[0x23]	37696	1			T5	2		T26	17		T22	22
valid_sources[0x24]	30442	1			T3	1		T5	5		T15	3
valid_sources[0x25]	29688	1			T3	1		T15	2		T16	12
valid_sources[0x26]	30669	1			T16	11		T17	7		T26	21
valid_sources[0x27]	39577	1			T5	1		T15	4		T16	5
valid_sources[0x28]	31076	1			T4	1		T15	9		T16	6
valid_sources[0x29]	36408	1			T5	1		T15	7		T16	3
valid_sources[0x2a]	33222	1			T3	1		T5	2		T15	2
valid_sources[0x2b]	34270	1			T16	3		T26	16		T22	8
valid_sources[0x2c]	31513	1			T5	9		T16	1		T26	12
valid_sources[0x2d]	34442	1			T13	1		T15	4		T26	14
valid_sources[0x2e]	31975	1			T5	1		T15	6		T16	11
valid_sources[0x2f]	31190	1			T15	1		T16	4		T17	29
valid_sources[0x30]	32728	1			T15	4		T16	6		T26	15
valid_sources[0x31]	37669	1			T5	4		T15	1		T16	3
valid_sources[0x32]	31638	1			T5	2		T15	9		T16	1
valid_sources[0x33]	30415	1			T5	2		T15	7		T16	2
valid_sources[0x34]	29595	1			T26	18		T22	34		T23	6
valid_sources[0x35]	45327	1			T5	5		T15	6		T16	2
valid_sources[0x36]	30847	1			T3	1		T5	6		T15	11
valid_sources[0x37]	29484	1			T5	1		T15	1		T26	11
valid_sources[0x38]	47410	1			T5	6		T13	1		T15	5
valid_sources[0x39]	35227	1			T5	2		T15	3		T16	7
valid_sources[0x3a]	29664	1			T5	3		T15	5		T16	6
valid_sources[0x3b]	31353	1			T3	2		T5	1		T15	1
valid_sources[0x3c]	34410	1			T15	2		T16	2		T26	12
valid_sources[0x3d]	31806	1			T5	5		T15	1		T16	1
valid_sources[0x3e]	35153	1			T5	2		T15	5		T17	3
valid_sources[0x3f]	31586	1			T4	1		T5	3		T16	1
valid_sources[0x40]	32177	1			T16	7		T26	21		T22	16
valid_sources[0x41]	31500	1			T4	1		T5	9		T15	8
valid_sources[0x42]	34545	1			T3	1		T4	1		T15	6
valid_sources[0x43]	34574	1			T3	1		T5	1		T15	2
valid_sources[0x44]	30848	1			T5	3		T15	2		T16	3
valid_sources[0x45]	30942	1			T3	3		T5	2		T16	12
valid_sources[0x46]	37325	1			T5	1		T16	8		T17	6
valid_sources[0x47]	37361	1			T15	7		T16	5		T26	17
valid_sources[0x48]	33053	1			T5	1		T15	5		T16	5
valid_sources[0x49]	36193	1			T5	2		T13	1		T15	7
valid_sources[0x4a]	31027	1			T5	3		T15	15		T16	3
valid_sources[0x4b]	36136	1			T5	2		T15	6		T16	3
valid_sources[0x4c]	32251	1			T26	15		T22	12		T23	7
valid_sources[0x4d]	30575	1			T16	11		T26	20		T22	15
valid_sources[0x4e]	29647	1			T5	1		T15	8		T16	5
valid_sources[0x4f]	30238	1			T5	1		T26	18		T22	44
valid_sources[0x50]	32537	1			T15	9		T16	8		T17	7
valid_sources[0x51]	32723	1			T5	2		T15	1		T16	3
valid_sources[0x52]	30555	1			T4	1		T15	25		T17	2
valid_sources[0x53]	32841	1			T16	3		T17	2		T26	16
valid_sources[0x54]	29402	1			T5	9		T15	7		T16	3
valid_sources[0x55]	30921	1			T5	2		T15	1		T16	4
valid_sources[0x56]	30114	1			T5	1		T16	4		T17	3
valid_sources[0x57]	30777	1			T5	1		T15	3		T16	3
valid_sources[0x58]	31230	1			T15	1		T16	6		T26	24
valid_sources[0x59]	34603	1			T15	1		T16	5		T26	15
valid_sources[0x5a]	29889	1			T16	1		T26	26		T22	19
valid_sources[0x5b]	52525	1			T15	1		T26	15		T22	16
valid_sources[0x5c]	29982	1			T5	1		T15	2		T16	7
valid_sources[0x5d]	31733	1			T15	1		T16	3		T17	2
valid_sources[0x5e]	32852	1			T5	1		T16	4		T17	14
valid_sources[0x5f]	29900	1			T15	7		T17	4		T26	26
valid_sources[0x60]	29754	1			T5	1		T15	10		T16	6
valid_sources[0x61]	29378	1			T3	1		T5	5		T15	6
valid_sources[0x62]	52738	1			T5	9		T15	4		T16	6
valid_sources[0x63]	31008	1			T15	5		T16	5		T17	43
valid_sources[0x64]	39506	1			T15	4		T16	6		T26	6
valid_sources[0x65]	31252	1			T5	7		T15	2		T16	9
valid_sources[0x66]	30169	1			T3	1		T15	4		T16	2
valid_sources[0x67]	29642	1			T2	1		T5	6		T16	6
valid_sources[0x68]	34756	1			T15	2		T16	3		T26	18
valid_sources[0x69]	33221	1			T5	11		T15	5		T16	8
valid_sources[0x6a]	31437	1			T3	1		T16	3		T26	12
valid_sources[0x6b]	31566	1			T3	3		T13	1		T14	331
valid_sources[0x6c]	28993	1			T5	10		T13	1		T15	10
valid_sources[0x6d]	29760	1			T5	5		T15	2		T16	3
valid_sources[0x6e]	30730	1			T5	4		T15	8		T16	2
valid_sources[0x6f]	28449	1			T3	2		T16	2		T26	16
valid_sources[0x70]	30514	1			T5	9		T13	1		T16	8
valid_sources[0x71]	30358	1			T5	1		T15	1		T16	10
valid_sources[0x72]	29727	1			T5	1		T15	2		T16	6
valid_sources[0x73]	31490	1			T5	3		T15	1		T16	3
valid_sources[0x74]	30912	1			T5	3		T15	3		T16	9
valid_sources[0x75]	31730	1			T4	1		T5	1		T11	26
valid_sources[0x76]	30913	1			T4	1		T15	9		T16	5
valid_sources[0x77]	33740	1			T5	9		T15	5		T16	3
valid_sources[0x78]	32162	1			T16	3		T26	24		T22	18
valid_sources[0x79]	30083	1			T4	1		T5	9		T13	1
valid_sources[0x7a]	34684	1			T5	2		T16	3		T17	9
valid_sources[0x7b]	32643	1			T4	1		T15	7		T16	5
valid_sources[0x7c]	29571	1			T5	1		T16	6		T17	1
valid_sources[0x7d]	29755	1			T5	5		T13	1		T15	14
valid_sources[0x7e]	29531	1			T5	1		T11	428		T15	1
valid_sources[0x7f]	30443	1			T13	1		T15	8		T26	18
valid_sources[0x80]	29936	1			T5	3		T15	7		T16	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1076768

1

T2

1

T5

18

T6

1

values[0x0]

all_enables

biggest_size

1671838

1

T4

9

T5

7

T6

2

values[0x1]

all_enables

biggest_size

1647928

1

T4

6

T5

4

T8

2