Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3913223

1

T1

1

T3

67

T4

5

full_word

4397933

1

T2

1

T4

15

T5

29

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8310736	1			T1	1		T2	1		T3	67
auto[TlIntgErrCmd]	151	1			T123	1		T124	12		T125	5
auto[TlIntgErrData]	135	1			T123	4		T124	9		T125	2
auto[TlIntgErrBoth]	134	1			T123	5		T124	9		T125	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4621136

1

T1

1

T2

1

T3

67

auto[1]

3690020

1

T4

19

T5

22

T6

6

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3543779	1			T1	1		T3	67		T4	1
auto[TlIntgErrNone]	partial	auto[1]	369055	1			T4	4		T5	11		T6	4
auto[TlIntgErrNone]	full_word	auto[0]	1077188	1			T2	1		T5	18		T6	1
auto[TlIntgErrNone]	full_word	auto[1]	3320714	1			T4	15		T5	11		T6	2
auto[TlIntgErrCmd]	partial	auto[0]	56	1			T123	1		T124	7		T125	2
auto[TlIntgErrCmd]	partial	auto[1]	81	1			T124	4		T125	2		T140	8
auto[TlIntgErrCmd]	full_word	auto[0]	8	1			T140	1		T200	1		T196	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T124	1		T125	1		T140	1
auto[TlIntgErrData]	partial	auto[0]	52	1			T123	3		T124	6		T140	2
auto[TlIntgErrData]	partial	auto[1]	73	1			T123	1		T124	3		T125	1
auto[TlIntgErrData]	full_word	auto[0]	5	1			T201	2		T202	1		T203	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T125	1		T140	1		T202	1
auto[TlIntgErrBoth]	partial	auto[0]	45	1			T124	3		T140	2		T204	3
auto[TlIntgErrBoth]	partial	auto[1]	82	1			T123	5		T124	6		T125	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T204	2		T202	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T201	1		T205	1		T206	1