Unified Coverage Report :: Module :: prim_generic_ram_1r1w

Module : prim_generic_ram_1r1w

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

44                        logic unused_cfg;
45         1/1            assign unused_cfg = ^cfg_i;
           Tests:       T2 
46                      
47                        // Width of internal write mask. Note *_wmask_i input into the module is always assumed
48                        // to be the full bit mask.
49                        localparam int MaskWidth = Width / DataBitsPerMask;
50                      
51                        logic [Width-1:0]     mem [Depth];
52                        logic [MaskWidth-1:0] a_wmask;
53                        for (genvar k = 0; k < MaskWidth; k++) begin : gen_wmask
54         4/4              assign a_wmask[k] = &a_wmask_i[k*DataBitsPerMask +: DataBitsPerMask];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
55                      
56                          // Ensure that all mask bits within a group have the same value for a write
57                          `ASSERT(MaskCheckPortA_A, a_req_i |->
58                              a_wmask_i[k*DataBitsPerMask +: DataBitsPerMask] inside {{DataBitsPerMask{1'b1}}, '0},
59                              clk_a_i, '0)
60                        end
61                      
62                        // Xilinx FPGA specific Two-port RAM coding style
63                        // using always instead of always_ff to avoid 'ICPD  - illegal combination of drivers' error
64                        // thrown due to 'mem' being driven by two always processes below
65                        always @(posedge clk_a_i) begin
66         1/1              if (a_req_i) begin
           Tests:       T1 T2 T3 
67         1/1                for (int i=0; i < MaskWidth; i = i + 1) begin
           Tests:       T5 T11 T14 
68         1/1                  if (a_wmask[i]) begin
           Tests:       T5 T11 T14 
69         1/1                    mem[a_addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
           Tests:       T5 T11 T14 
70                                  a_wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
71                              end
                        MISSING_ELSE
72                            end
73                          end
                        MISSING_ELSE
74                        end
75                      
76                        always @(posedge clk_b_i) begin
77         1/1              if (b_req_i) begin
           Tests:       T1 T2 T3 
78         1/1                b_rdata_o <= mem[b_addr_i];
           Tests:       T5 T14 T15 
79                          end
                        MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

66             if (a_req_i) begin
               -1-  
67               for (int i=0; i < MaskWidth; i = i + 1) begin
                 ==>
68                 if (a_wmask[i]) begin
69                   mem[a_addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
70                     a_wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
71                 end
72               end
73             end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T5,T11,T14
0	Covered	T1,T2,T3

77             if (b_req_i) begin
               -1-  
78               b_rdata_o <= mem[b_addr_i];
                 ==>
79             end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T5,T14,T15
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1r1w

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	656538184	3361248	0	0
gen_wmask[1].MaskCheckPortA_A	656538184	3361248	0	0
gen_wmask[2].MaskCheckPortA_A	656538184	3361248	0	0
gen_wmask[3].MaskCheckPortA_A	656538184	3361248	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	656538184	3361248	0	0
T5	2913	58	0	0
T6	1339	0	0	0
T7	1300	0	0	0
T8	1043	0	0	0
T9	1754	0	0	0
T10	2086	0	0	0
T11	3629	832	0	0
T12	3439	0	0	0
T13	2991	0	0	0
T14	5244	10	0	0
T15	46329	832	0	0
T16	2698	832	0	0
T17	121528	0	0	0
T18	1120	832	0	0
T19	16416	832	0	0
T20	192	832	0	0
T22	0	832	0	0
T26	0	1299	0	0
T41	0	514	0	0
T42	0	2779	0	0
T43	0	3918	0	0
T46	0	5073	0	0
T47	0	64	0	0
T48	0	1479	0	0
T49	0	4869	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	656538184	3361248	0	0
T5	2913	58	0	0
T6	1339	0	0	0
T7	1300	0	0	0
T8	1043	0	0	0
T9	1754	0	0	0
T10	2086	0	0	0
T11	3629	832	0	0
T12	3439	0	0	0
T13	2991	0	0	0
T14	5244	10	0	0
T15	46329	832	0	0
T16	2698	832	0	0
T17	121528	0	0	0
T18	1120	832	0	0
T19	16416	832	0	0
T20	192	832	0	0
T22	0	832	0	0
T26	0	1299	0	0
T41	0	514	0	0
T42	0	2779	0	0
T43	0	3918	0	0
T46	0	5073	0	0
T47	0	64	0	0
T48	0	1479	0	0
T49	0	4869	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	656538184	3361248	0	0
T5	2913	58	0	0
T6	1339	0	0	0
T7	1300	0	0	0
T8	1043	0	0	0
T9	1754	0	0	0
T10	2086	0	0	0
T11	3629	832	0	0
T12	3439	0	0	0
T13	2991	0	0	0
T14	5244	10	0	0
T15	46329	832	0	0
T16	2698	832	0	0
T17	121528	0	0	0
T18	1120	832	0	0
T19	16416	832	0	0
T20	192	832	0	0
T22	0	832	0	0
T26	0	1299	0	0
T41	0	514	0	0
T42	0	2779	0	0
T43	0	3918	0	0
T46	0	5073	0	0
T47	0	64	0	0
T48	0	1479	0	0
T49	0	4869	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	656538184	3361248	0	0
T5	2913	58	0	0
T6	1339	0	0	0
T7	1300	0	0	0
T8	1043	0	0	0
T9	1754	0	0	0
T10	2086	0	0	0
T11	3629	832	0	0
T12	3439	0	0	0
T13	2991	0	0	0
T14	5244	10	0	0
T15	46329	832	0	0
T16	2698	832	0	0
T17	121528	0	0	0
T18	1120	832	0	0
T19	16416	832	0	0
T20	192	832	0	0
T22	0	832	0	0
T26	0	1299	0	0
T41	0	514	0	0
T42	0	2779	0	0
T43	0	3918	0	0
T46	0	5073	0	0
T47	0	64	0	0
T48	0	1479	0	0
T49	0	4869	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

44                        logic unused_cfg;
45         1/1            assign unused_cfg = ^cfg_i;
           Tests:       T2 
46                      
47                        // Width of internal write mask. Note *_wmask_i input into the module is always assumed
48                        // to be the full bit mask.
49                        localparam int MaskWidth = Width / DataBitsPerMask;
50                      
51                        logic [Width-1:0]     mem [Depth];
52                        logic [MaskWidth-1:0] a_wmask;
53                        for (genvar k = 0; k < MaskWidth; k++) begin : gen_wmask
54         4/4              assign a_wmask[k] = &a_wmask_i[k*DataBitsPerMask +: DataBitsPerMask];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
55                      
56                          // Ensure that all mask bits within a group have the same value for a write
57                          `ASSERT(MaskCheckPortA_A, a_req_i |->
58                              a_wmask_i[k*DataBitsPerMask +: DataBitsPerMask] inside {{DataBitsPerMask{1'b1}}, '0},
59                              clk_a_i, '0)
60                        end
61                      
62                        // Xilinx FPGA specific Two-port RAM coding style
63                        // using always instead of always_ff to avoid 'ICPD  - illegal combination of drivers' error
64                        // thrown due to 'mem' being driven by two always processes below
65                        always @(posedge clk_a_i) begin
66         1/1              if (a_req_i) begin
           Tests:       T1 T2 T3 
67         1/1                for (int i=0; i < MaskWidth; i = i + 1) begin
           Tests:       T5 T11 T14 
68         1/1                  if (a_wmask[i]) begin
           Tests:       T5 T11 T14 
69         1/1                    mem[a_addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
           Tests:       T5 T11 T14 
70                                  a_wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
71                              end
                   ==>  MISSING_ELSE
72                            end
73                          end
                        MISSING_ELSE
74                        end
75                      
76                        always @(posedge clk_b_i) begin
77         1/1              if (b_req_i) begin
           Tests:       T4 T5 T11 
78         1/1                b_rdata_o <= mem[b_addr_i];
           Tests:       T5 T14 T15 
79                          end
                        MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

66             if (a_req_i) begin
               -1-  
67               for (int i=0; i < MaskWidth; i = i + 1) begin
                 ==>
68                 if (a_wmask[i]) begin
69                   mem[a_addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
70                     a_wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
71                 end
72               end
73             end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T5,T11,T14
0	Covered	T1,T2,T3

77             if (b_req_i) begin
               -1-  
78               b_rdata_o <= mem[b_addr_i];
                 ==>
79             end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T5,T14,T15
0	Covered	T4,T5,T11

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	505580215	2095742	0	0
gen_wmask[1].MaskCheckPortA_A	505580215	2095742	0	0
gen_wmask[2].MaskCheckPortA_A	505580215	2095742	0	0
gen_wmask[3].MaskCheckPortA_A	505580215	2095742	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505580215	2095742	0	0
T5	2209	2	0	0
T6	1339	0	0	0
T7	1300	0	0	0
T8	1043	0	0	0
T9	1754	0	0	0
T10	2086	0	0	0
T11	3501	832	0	0
T12	3439	0	0	0
T13	2415	0	0	0
T14	4756	6	0	0
T15	0	832	0	0
T16	0	832	0	0
T18	0	832	0	0
T19	0	832	0	0
T20	0	832	0	0
T22	0	832	0	0
T26	0	468	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505580215	2095742	0	0
T5	2209	2	0	0
T6	1339	0	0	0
T7	1300	0	0	0
T8	1043	0	0	0
T9	1754	0	0	0
T10	2086	0	0	0
T11	3501	832	0	0
T12	3439	0	0	0
T13	2415	0	0	0
T14	4756	6	0	0
T15	0	832	0	0
T16	0	832	0	0
T18	0	832	0	0
T19	0	832	0	0
T20	0	832	0	0
T22	0	832	0	0
T26	0	468	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505580215	2095742	0	0
T5	2209	2	0	0
T6	1339	0	0	0
T7	1300	0	0	0
T8	1043	0	0	0
T9	1754	0	0	0
T10	2086	0	0	0
T11	3501	832	0	0
T12	3439	0	0	0
T13	2415	0	0	0
T14	4756	6	0	0
T15	0	832	0	0
T16	0	832	0	0
T18	0	832	0	0
T19	0	832	0	0
T20	0	832	0	0
T22	0	832	0	0
T26	0	468	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505580215	2095742	0	0
T5	2209	2	0	0
T6	1339	0	0	0
T7	1300	0	0	0
T8	1043	0	0	0
T9	1754	0	0	0
T10	2086	0	0	0
T11	3501	832	0	0
T12	3439	0	0	0
T13	2415	0	0	0
T14	4756	6	0	0
T15	0	832	0	0
T16	0	832	0	0
T18	0	832	0	0
T19	0	832	0	0
T20	0	832	0	0
T22	0	832	0	0
T26	0	468	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

44                        logic unused_cfg;
45         1/1            assign unused_cfg = ^cfg_i;
           Tests:       T2 
46                      
47                        // Width of internal write mask. Note *_wmask_i input into the module is always assumed
48                        // to be the full bit mask.
49                        localparam int MaskWidth = Width / DataBitsPerMask;
50                      
51                        logic [Width-1:0]     mem [Depth];
52                        logic [MaskWidth-1:0] a_wmask;
53                        for (genvar k = 0; k < MaskWidth; k++) begin : gen_wmask
54         4/4              assign a_wmask[k] = &a_wmask_i[k*DataBitsPerMask +: DataBitsPerMask];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
55                      
56                          // Ensure that all mask bits within a group have the same value for a write
57                          `ASSERT(MaskCheckPortA_A, a_req_i |->
58                              a_wmask_i[k*DataBitsPerMask +: DataBitsPerMask] inside {{DataBitsPerMask{1'b1}}, '0},
59                              clk_a_i, '0)
60                        end
61                      
62                        // Xilinx FPGA specific Two-port RAM coding style
63                        // using always instead of always_ff to avoid 'ICPD  - illegal combination of drivers' error
64                        // thrown due to 'mem' being driven by two always processes below
65                        always @(posedge clk_a_i) begin
66         1/1              if (a_req_i) begin
           Tests:       T4 T5 T11 
67         1/1                for (int i=0; i < MaskWidth; i = i + 1) begin
           Tests:       T5 T14 T26 
68         1/1                  if (a_wmask[i]) begin
           Tests:       T5 T14 T26 
69         1/1                    mem[a_addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
           Tests:       T5 T14 T26 
70                                  a_wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
71                              end
                        MISSING_ELSE
72                            end
73                          end
                        MISSING_ELSE
74                        end
75                      
76                        always @(posedge clk_b_i) begin
77         1/1              if (b_req_i) begin
           Tests:       T1 T2 T3 
78         1/1                b_rdata_o <= mem[b_addr_i];
           Tests:       T5 T14 T26 
79                          end
                        MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

66             if (a_req_i) begin
               -1-  
67               for (int i=0; i < MaskWidth; i = i + 1) begin
                 ==>
68                 if (a_wmask[i]) begin
69                   mem[a_addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
70                     a_wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
71                 end
72               end
73             end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T5,T14,T26
0	Covered	T4,T5,T11

77             if (b_req_i) begin
               -1-  
78               b_rdata_o <= mem[b_addr_i];
                 ==>
79             end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T5,T14,T26
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	150957969	1265506	0	0
gen_wmask[1].MaskCheckPortA_A	150957969	1265506	0	0
gen_wmask[2].MaskCheckPortA_A	150957969	1265506	0	0
gen_wmask[3].MaskCheckPortA_A	150957969	1265506	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150957969	1265506	0	0
T5	704	56	0	0
T11	128	0	0	0
T13	576	0	0	0
T14	488	4	0	0
T15	46329	0	0	0
T16	2698	0	0	0
T17	121528	0	0	0
T18	1120	0	0	0
T19	16416	0	0	0
T20	192	0	0	0
T26	0	831	0	0
T41	0	514	0	0
T42	0	2779	0	0
T43	0	3918	0	0
T46	0	5073	0	0
T47	0	64	0	0
T48	0	1479	0	0
T49	0	4869	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150957969	1265506	0	0
T5	704	56	0	0
T11	128	0	0	0
T13	576	0	0	0
T14	488	4	0	0
T15	46329	0	0	0
T16	2698	0	0	0
T17	121528	0	0	0
T18	1120	0	0	0
T19	16416	0	0	0
T20	192	0	0	0
T26	0	831	0	0
T41	0	514	0	0
T42	0	2779	0	0
T43	0	3918	0	0
T46	0	5073	0	0
T47	0	64	0	0
T48	0	1479	0	0
T49	0	4869	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150957969	1265506	0	0
T5	704	56	0	0
T11	128	0	0	0
T13	576	0	0	0
T14	488	4	0	0
T15	46329	0	0	0
T16	2698	0	0	0
T17	121528	0	0	0
T18	1120	0	0	0
T19	16416	0	0	0
T20	192	0	0	0
T26	0	831	0	0
T41	0	514	0	0
T42	0	2779	0	0
T43	0	3918	0	0
T46	0	5073	0	0
T47	0	64	0	0
T48	0	1479	0	0
T49	0	4869	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150957969	1265506	0	0
T5	704	56	0	0
T11	128	0	0	0
T13	576	0	0	0
T14	488	4	0	0
T15	46329	0	0	0
T16	2698	0	0	0
T17	121528	0	0	0
T18	1120	0	0	0
T19	16416	0	0	0
T20	192	0	0	0
T26	0	831	0	0
T41	0	514	0	0
T42	0	2779	0	0
T43	0	3918	0	0
T46	0	5073	0	0
T47	0	64	0	0
T48	0	1479	0	0
T49	0	4869	0	0